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46 #define AR5K_NOQCU_TXDP0 0x0000
47 #define AR5K_NOQCU_TXDP1 0x0004
52 #define AR5K_CR 0x0008
53 #define AR5K_CR_TXE0 0x00000001
54 #define AR5K_CR_TXE1 0x00000002
55 #define AR5K_CR_RXE 0x00000004
56 #define AR5K_CR_TXD0 0x00000008
57 #define AR5K_CR_TXD1 0x00000010
58 #define AR5K_CR_RXD 0x00000020
59 #define AR5K_CR_SWI 0x00000040
64 #define AR5K_RXDP 0x000c
69 #define AR5K_CFG 0x0014
70 #define AR5K_CFG_SWTD 0x00000001
71 #define AR5K_CFG_SWTB 0x00000002
72 #define AR5K_CFG_SWRD 0x00000004
73 #define AR5K_CFG_SWRB 0x00000008
74 #define AR5K_CFG_SWRG 0x00000010
75 #define AR5K_CFG_IBSS 0x00000020
76 #define AR5K_CFG_PHY_OK 0x00000100
77 #define AR5K_CFG_EEBS 0x00000200
78 #define AR5K_CFG_CLKGD 0x00000400
79 #define AR5K_CFG_TXCNT 0x00007800
80 #define AR5K_CFG_TXCNT_S 11
81 #define AR5K_CFG_TXFSTAT 0x00008000
82 #define AR5K_CFG_TXFSTRT 0x00010000
83 #define AR5K_CFG_PCI_THRES 0x00060000
84 #define AR5K_CFG_PCI_THRES_S 17
89 #define AR5K_IER 0x0024
90 #define AR5K_IER_DISABLE 0x00000000
91 #define AR5K_IER_ENABLE 0x00000001
102 #define AR5K_BCR 0x0028
103 #define AR5K_BCR_AP 0x00000000
104 #define AR5K_BCR_ADHOC 0x00000001
105 #define AR5K_BCR_BDMAE 0x00000002
106 #define AR5K_BCR_TQ1FV 0x00000004
107 #define AR5K_BCR_TQ1V 0x00000008
108 #define AR5K_BCR_BCGET 0x00000010
113 #define AR5K_RTSD0 0x0028
114 #define AR5K_RTSD0_6 0x000000ff
115 #define AR5K_RTSD0_6_S 0
116 #define AR5K_RTSD0_9 0x0000ff00
117 #define AR5K_RTSD0_9_S 8
118 #define AR5K_RTSD0_12 0x00ff0000
119 #define AR5K_RTSD0_12_S 16
120 #define AR5K_RTSD0_18 0xff000000
121 #define AR5K_RTSD0_18_S 24
139 #define AR5K_BSR 0x002c
140 #define AR5K_BSR_BDLYSW 0x00000001
141 #define AR5K_BSR_BDLYDMA 0x00000002
142 #define AR5K_BSR_TXQ1F 0x00000004
143 #define AR5K_BSR_ATIMDLY 0x00000008
144 #define AR5K_BSR_SNPADHOC 0x00000100
145 #define AR5K_BSR_SNPBDMAE 0x00000200
146 #define AR5K_BSR_SNPTQ1FV 0x00000400
147 #define AR5K_BSR_SNPTQ1V 0x00000800
148 #define AR5K_BSR_SNAPSHOTSVALID 0x00001000
149 #define AR5K_BSR_SWBA_CNT 0x00ff0000
154 #define AR5K_RTSD1 0x002c
155 #define AR5K_RTSD1_24 0x000000ff
156 #define AR5K_RTSD1_24_S 0
157 #define AR5K_RTSD1_36 0x0000ff00
158 #define AR5K_RTSD1_36_S 8
159 #define AR5K_RTSD1_48 0x00ff0000
160 #define AR5K_RTSD1_48_S 16
161 #define AR5K_RTSD1_54 0xff000000
162 #define AR5K_RTSD1_54_S 24
168 #define AR5K_TXCFG 0x0030
169 #define AR5K_TXCFG_SDMAMR 0x00000007
170 #define AR5K_TXCFG_SDMAMR_S 0
171 #define AR5K_TXCFG_B_MODE 0x00000008
172 #define AR5K_TXCFG_TXFSTP 0x00000008
173 #define AR5K_TXCFG_TXFULL 0x000003f0
174 #define AR5K_TXCFG_TXFULL_S 4
175 #define AR5K_TXCFG_TXFULL_0B 0x00000000
176 #define AR5K_TXCFG_TXFULL_64B 0x00000010
177 #define AR5K_TXCFG_TXFULL_128B 0x00000020
178 #define AR5K_TXCFG_TXFULL_192B 0x00000030
179 #define AR5K_TXCFG_TXFULL_256B 0x00000040
180 #define AR5K_TXCFG_TXCONT_EN 0x00000080
181 #define AR5K_TXCFG_DMASIZE 0x00000100
182 #define AR5K_TXCFG_JUMBO_DESC_EN 0x00000400
183 #define AR5K_TXCFG_ADHOC_BCN_ATIM 0x00000800
184 #define AR5K_TXCFG_ATIM_WINDOW_DEF_DIS 0x00001000
185 #define AR5K_TXCFG_RTSRND 0x00001000
186 #define AR5K_TXCFG_FRMPAD_DIS 0x00002000
187 #define AR5K_TXCFG_RDY_CBR_DIS 0x00004000
188 #define AR5K_TXCFG_JUMBO_FRM_MODE 0x00008000
189 #define AR5K_TXCFG_DCU_DBL_BUF_DIS 0x00008000
190 #define AR5K_TXCFG_DCU_CACHING_DIS 0x00010000
195 #define AR5K_RXCFG 0x0034
196 #define AR5K_RXCFG_SDMAMW 0x00000007
197 #define AR5K_RXCFG_SDMAMW_S 0
198 #define AR5K_RXCFG_ZLFDMA 0x00000008
199 #define AR5K_RXCFG_DEF_ANTENNA 0x00000010
200 #define AR5K_RXCFG_JUMBO_RXE 0x00000020
201 #define AR5K_RXCFG_JUMBO_WRAP 0x00000040
202 #define AR5K_RXCFG_SLE_ENTRY 0x00000080
208 #define AR5K_RXJLA 0x0038
213 #define AR5K_MIBC 0x0040
214 #define AR5K_MIBC_COW 0x00000001
215 #define AR5K_MIBC_FMC 0x00000002
216 #define AR5K_MIBC_CMC 0x00000004
217 #define AR5K_MIBC_MCS 0x00000008
222 #define AR5K_TOPS 0x0044
223 #define AR5K_TOPS_M 0x0000ffff
228 #define AR5K_RXNOFRM 0x0048
229 #define AR5K_RXNOFRM_M 0x000003ff
234 #define AR5K_TXNOFRM 0x004c
235 #define AR5K_TXNOFRM_M 0x000003ff
236 #define AR5K_TXNOFRM_QCU 0x000ffc00
237 #define AR5K_TXNOFRM_QCU_S 10
242 #define AR5K_RPGTO 0x0050
243 #define AR5K_RPGTO_M 0x000003ff
248 #define AR5K_RFCNT 0x0054
249 #define AR5K_RFCNT_M 0x0000001f
250 #define AR5K_RFCNT_RFCL 0x0000000f
256 #define AR5K_MISC 0x0058
257 #define AR5K_MISC_DMA_OBS_M 0x000001e0
258 #define AR5K_MISC_DMA_OBS_S 5
259 #define AR5K_MISC_MISC_OBS_M 0x00000e00
260 #define AR5K_MISC_MISC_OBS_S 9
261 #define AR5K_MISC_MAC_OBS_LSB_M 0x00007000
262 #define AR5K_MISC_MAC_OBS_LSB_S 12
263 #define AR5K_MISC_MAC_OBS_MSB_M 0x00038000
264 #define AR5K_MISC_MAC_OBS_MSB_S 15
265 #define AR5K_MISC_LED_DECAY 0x001c0000
266 #define AR5K_MISC_LED_BLINK 0x00e00000
272 #define AR5K_QCUDCU_CLKGT 0x005c
273 #define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff
274 #define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000
288 #define AR5K_ISR 0x001c
289 #define AR5K_PISR 0x0080
290 #define AR5K_ISR_RXOK 0x00000001
291 #define AR5K_ISR_RXDESC 0x00000002
292 #define AR5K_ISR_RXERR 0x00000004
293 #define AR5K_ISR_RXNOFRM 0x00000008
294 #define AR5K_ISR_RXEOL 0x00000010
295 #define AR5K_ISR_RXORN 0x00000020
296 #define AR5K_ISR_TXOK 0x00000040
297 #define AR5K_ISR_TXDESC 0x00000080
298 #define AR5K_ISR_TXERR 0x00000100
299 #define AR5K_ISR_TXNOFRM 0x00000200
303 #define AR5K_ISR_TXEOL 0x00000400
304 #define AR5K_ISR_TXURN 0x00000800
305 #define AR5K_ISR_MIB 0x00001000
306 #define AR5K_ISR_SWI 0x00002000
307 #define AR5K_ISR_RXPHY 0x00004000
308 #define AR5K_ISR_RXKCM 0x00008000
309 #define AR5K_ISR_SWBA 0x00010000
310 #define AR5K_ISR_BRSSI 0x00020000
311 #define AR5K_ISR_BMISS 0x00040000
312 #define AR5K_ISR_HIUERR 0x00080000
314 #define AR5K_ISR_BNR 0x00100000
315 #define AR5K_ISR_MCABT 0x00100000
316 #define AR5K_ISR_RXCHIRP 0x00200000
317 #define AR5K_ISR_SSERR 0x00200000
318 #define AR5K_ISR_DPERR 0x00400000
319 #define AR5K_ISR_RXDOPPLER 0x00400000
320 #define AR5K_ISR_TIM 0x00800000
321 #define AR5K_ISR_BCNMISC 0x00800000
324 #define AR5K_ISR_GPIO 0x01000000
325 #define AR5K_ISR_QCBRORN 0x02000000
326 #define AR5K_ISR_QCBRURN 0x04000000
327 #define AR5K_ISR_QTRIG 0x08000000
329 #define AR5K_ISR_BITS_FROM_SISRS (AR5K_ISR_TXOK | AR5K_ISR_TXDESC |\
330 AR5K_ISR_TXERR | AR5K_ISR_TXEOL |\
331 AR5K_ISR_TXURN | AR5K_ISR_HIUERR |\
332 AR5K_ISR_BCNMISC | AR5K_ISR_QCBRORN |\
333 AR5K_ISR_QCBRURN | AR5K_ISR_QTRIG)
341 #define AR5K_SISR0 0x0084
342 #define AR5K_SISR0_QCU_TXOK 0x000003ff
343 #define AR5K_SISR0_QCU_TXOK_S 0
344 #define AR5K_SISR0_QCU_TXDESC 0x03ff0000
345 #define AR5K_SISR0_QCU_TXDESC_S 16
347 #define AR5K_SISR1 0x0088
348 #define AR5K_SISR1_QCU_TXERR 0x000003ff
349 #define AR5K_SISR1_QCU_TXERR_S 0
350 #define AR5K_SISR1_QCU_TXEOL 0x03ff0000
351 #define AR5K_SISR1_QCU_TXEOL_S 16
353 #define AR5K_SISR2 0x008c
354 #define AR5K_SISR2_QCU_TXURN 0x000003ff
355 #define AR5K_SISR2_QCU_TXURN_S 0
356 #define AR5K_SISR2_MCABT 0x00010000
357 #define AR5K_SISR2_SSERR 0x00020000
358 #define AR5K_SISR2_DPERR 0x00040000
359 #define AR5K_SISR2_TIM 0x01000000
360 #define AR5K_SISR2_CAB_END 0x02000000
361 #define AR5K_SISR2_DTIM_SYNC 0x04000000
362 #define AR5K_SISR2_BCN_TIMEOUT 0x08000000
363 #define AR5K_SISR2_CAB_TIMEOUT 0x10000000
364 #define AR5K_SISR2_DTIM 0x20000000
365 #define AR5K_SISR2_TSFOOR 0x80000000
367 #define AR5K_SISR3 0x0090
368 #define AR5K_SISR3_QCBRORN 0x000003ff
369 #define AR5K_SISR3_QCBRORN_S 0
370 #define AR5K_SISR3_QCBRURN 0x03ff0000
371 #define AR5K_SISR3_QCBRURN_S 16
373 #define AR5K_SISR4 0x0094
374 #define AR5K_SISR4_QTRIG 0x000003ff
375 #define AR5K_SISR4_QTRIG_S 0
380 #define AR5K_RAC_PISR 0x00c0
381 #define AR5K_RAC_SISR0 0x00c4
382 #define AR5K_RAC_SISR1 0x00c8
383 #define AR5K_RAC_SISR2 0x00cc
384 #define AR5K_RAC_SISR3 0x00d0
385 #define AR5K_RAC_SISR4 0x00d4
393 #define AR5K_IMR 0x0020
394 #define AR5K_PIMR 0x00a0
395 #define AR5K_IMR_RXOK 0x00000001
396 #define AR5K_IMR_RXDESC 0x00000002
397 #define AR5K_IMR_RXERR 0x00000004
398 #define AR5K_IMR_RXNOFRM 0x00000008
399 #define AR5K_IMR_RXEOL 0x00000010
400 #define AR5K_IMR_RXORN 0x00000020
401 #define AR5K_IMR_TXOK 0x00000040
402 #define AR5K_IMR_TXDESC 0x00000080
403 #define AR5K_IMR_TXERR 0x00000100
404 #define AR5K_IMR_TXNOFRM 0x00000200
405 #define AR5K_IMR_TXEOL 0x00000400
406 #define AR5K_IMR_TXURN 0x00000800
407 #define AR5K_IMR_MIB 0x00001000
408 #define AR5K_IMR_SWI 0x00002000
409 #define AR5K_IMR_RXPHY 0x00004000
410 #define AR5K_IMR_RXKCM 0x00008000
411 #define AR5K_IMR_SWBA 0x00010000
412 #define AR5K_IMR_BRSSI 0x00020000
413 #define AR5K_IMR_BMISS 0x00040000
414 #define AR5K_IMR_HIUERR 0x00080000
415 #define AR5K_IMR_BNR 0x00100000
416 #define AR5K_IMR_MCABT 0x00100000
417 #define AR5K_IMR_RXCHIRP 0x00200000
418 #define AR5K_IMR_SSERR 0x00200000
419 #define AR5K_IMR_DPERR 0x00400000
420 #define AR5K_IMR_RXDOPPLER 0x00400000
421 #define AR5K_IMR_TIM 0x00800000
422 #define AR5K_IMR_BCNMISC 0x00800000
424 #define AR5K_IMR_GPIO 0x01000000
425 #define AR5K_IMR_QCBRORN 0x02000000
426 #define AR5K_IMR_QCBRURN 0x04000000
427 #define AR5K_IMR_QTRIG 0x08000000
432 #define AR5K_SIMR0 0x00a4
433 #define AR5K_SIMR0_QCU_TXOK 0x000003ff
434 #define AR5K_SIMR0_QCU_TXOK_S 0
435 #define AR5K_SIMR0_QCU_TXDESC 0x03ff0000
436 #define AR5K_SIMR0_QCU_TXDESC_S 16
438 #define AR5K_SIMR1 0x00a8
439 #define AR5K_SIMR1_QCU_TXERR 0x000003ff
440 #define AR5K_SIMR1_QCU_TXERR_S 0
441 #define AR5K_SIMR1_QCU_TXEOL 0x03ff0000
442 #define AR5K_SIMR1_QCU_TXEOL_S 16
444 #define AR5K_SIMR2 0x00ac
445 #define AR5K_SIMR2_QCU_TXURN 0x000003ff
446 #define AR5K_SIMR2_QCU_TXURN_S 0
447 #define AR5K_SIMR2_MCABT 0x00010000
448 #define AR5K_SIMR2_SSERR 0x00020000
449 #define AR5K_SIMR2_DPERR 0x00040000
450 #define AR5K_SIMR2_TIM 0x01000000
451 #define AR5K_SIMR2_CAB_END 0x02000000
452 #define AR5K_SIMR2_DTIM_SYNC 0x04000000
453 #define AR5K_SIMR2_BCN_TIMEOUT 0x08000000
454 #define AR5K_SIMR2_CAB_TIMEOUT 0x10000000
455 #define AR5K_SIMR2_DTIM 0x20000000
456 #define AR5K_SIMR2_TSFOOR 0x80000000
458 #define AR5K_SIMR3 0x00b0
459 #define AR5K_SIMR3_QCBRORN 0x000003ff
460 #define AR5K_SIMR3_QCBRORN_S 0
461 #define AR5K_SIMR3_QCBRURN 0x03ff0000
462 #define AR5K_SIMR3_QCBRURN_S 16
464 #define AR5K_SIMR4 0x00b4
465 #define AR5K_SIMR4_QTRIG 0x000003ff
466 #define AR5K_SIMR4_QTRIG_S 0
476 #define AR5K_DCM_ADDR 0x0400
477 #define AR5K_DCM_DATA 0x0404
482 #define AR5K_WOW_PCFG 0x0410
483 #define AR5K_WOW_PCFG_PAT_MATCH_EN 0x00000001
484 #define AR5K_WOW_PCFG_LONG_FRAME_POL 0x00000002
485 #define AR5K_WOW_PCFG_WOBMISS 0x00000004
486 #define AR5K_WOW_PCFG_PAT_0_EN 0x00000100
487 #define AR5K_WOW_PCFG_PAT_1_EN 0x00000200
488 #define AR5K_WOW_PCFG_PAT_2_EN 0x00000400
489 #define AR5K_WOW_PCFG_PAT_3_EN 0x00000800
490 #define AR5K_WOW_PCFG_PAT_4_EN 0x00001000
491 #define AR5K_WOW_PCFG_PAT_5_EN 0x00002000
496 #define AR5K_WOW_PAT_IDX 0x0414
501 #define AR5K_WOW_PAT_DATA 0x0418
502 #define AR5K_WOW_PAT_DATA_0_3_V 0x00000001
503 #define AR5K_WOW_PAT_DATA_1_4_V 0x00000100
504 #define AR5K_WOW_PAT_DATA_2_5_V 0x00010000
505 #define AR5K_WOW_PAT_DATA_0_3_M 0x01000000
506 #define AR5K_WOW_PAT_DATA_1_4_M 0x04000000
507 #define AR5K_WOW_PAT_DATA_2_5_M 0x10000000
512 #define AR5K_DCCFG 0x0420
513 #define AR5K_DCCFG_GLOBAL_EN 0x00000001
514 #define AR5K_DCCFG_BYPASS_EN 0x00000002
515 #define AR5K_DCCFG_BCAST_EN 0x00000004
516 #define AR5K_DCCFG_MCAST_EN 0x00000008
521 #define AR5K_CCFG 0x0600
522 #define AR5K_CCFG_WINDOW_SIZE 0x00000007
523 #define AR5K_CCFG_CPC_EN 0x00000008
525 #define AR5K_CCFG_CCU 0x0604
526 #define AR5K_CCFG_CCU_CUP_EN 0x00000001
527 #define AR5K_CCFG_CCU_CREDIT 0x00000002
528 #define AR5K_CCFG_CCU_CD_THRES 0x00000080
529 #define AR5K_CCFG_CCU_CUP_LCNT 0x00010000
530 #define AR5K_CCFG_CCU_INIT 0x00100200
535 #define AR5K_CPC0 0x0610
536 #define AR5K_CPC1 0x0614
537 #define AR5K_CPC2 0x0618
538 #define AR5K_CPC3 0x061c
539 #define AR5K_CPCOVF 0x0620
560 #define AR5K_QUEUE_REG(_r, _q) (((_q) << 2) + _r)
561 #define AR5K_QCU_GLOBAL_READ(_r, _q) (AR5K_REG_READ(_r) & (1 << _q))
562 #define AR5K_QCU_GLOBAL_WRITE(_r, _q) AR5K_REG_WRITE(_r, (1 << _q))
567 #define AR5K_QCU_TXDP_BASE 0x0800
568 #define AR5K_QUEUE_TXDP(_q) AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q)
573 #define AR5K_QCU_TXE 0x0840
574 #define AR5K_ENABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q)
575 #define AR5K_QUEUE_ENABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q)
580 #define AR5K_QCU_TXD 0x0880
581 #define AR5K_DISABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q)
582 #define AR5K_QUEUE_DISABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q)
587 #define AR5K_QCU_CBRCFG_BASE 0x08c0
588 #define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff
589 #define AR5K_QCU_CBRCFG_INTVAL_S 0
590 #define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000
591 #define AR5K_QCU_CBRCFG_ORN_THRES_S 24
592 #define AR5K_QUEUE_CBRCFG(_q) AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q)
597 #define AR5K_QCU_RDYTIMECFG_BASE 0x0900
598 #define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff
599 #define AR5K_QCU_RDYTIMECFG_INTVAL_S 0
600 #define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000
601 #define AR5K_QUEUE_RDYTIMECFG(_q) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q)
606 #define AR5K_QCU_ONESHOTARM_SET 0x0940
607 #define AR5K_QCU_ONESHOTARM_SET_M 0x0000ffff
612 #define AR5K_QCU_ONESHOTARM_CLEAR 0x0980
613 #define AR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff
618 #define AR5K_QCU_MISC_BASE 0x09c0
619 #define AR5K_QCU_MISC_FRSHED_M 0x0000000f
620 #define AR5K_QCU_MISC_FRSHED_ASAP 0
621 #define AR5K_QCU_MISC_FRSHED_CBR 1
622 #define AR5K_QCU_MISC_FRSHED_DBA_GT 2
623 #define AR5K_QCU_MISC_FRSHED_TIM_GT 3
624 #define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4
625 #define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010
626 #define AR5K_QCU_MISC_CBREXP_DIS 0x00000020
627 #define AR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040
628 #define AR5K_QCU_MISC_BCN_ENABLE 0x00000080
629 #define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100
630 #define AR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200
631 #define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400
632 #define AR5K_QCU_MISC_DCU_EARLY 0x00000800
633 #define AR5K_QCU_MISC_DCU_CMP_EN 0x00001000
634 #define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q)
640 #define AR5K_QCU_STS_BASE 0x0a00
641 #define AR5K_QCU_STS_FRMPENDCNT 0x00000003
642 #define AR5K_QCU_STS_CBREXPCNT 0x0000ff00
643 #define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q)
648 #define AR5K_QCU_RDYTIMESHDN 0x0a40
649 #define AR5K_QCU_RDYTIMESHDN_M 0x000003ff
654 #define AR5K_QCU_CBB_SELECT 0x0b00
655 #define AR5K_QCU_CBB_ADDR 0x0b04
656 #define AR5K_QCU_CBB_ADDR_S 9
662 #define AR5K_QCU_CBCFG 0x0b08
685 #define AR5K_DCU_QCUMASK_BASE 0x1000
686 #define AR5K_DCU_QCUMASK_M 0x000003ff
687 #define AR5K_QUEUE_QCUMASK(_q) AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q)
692 #define AR5K_DCU_LCL_IFS_BASE 0x1040
693 #define AR5K_DCU_LCL_IFS_CW_MIN 0x000003ff
694 #define AR5K_DCU_LCL_IFS_CW_MIN_S 0
695 #define AR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00
696 #define AR5K_DCU_LCL_IFS_CW_MAX_S 10
697 #define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000
698 #define AR5K_DCU_LCL_IFS_AIFS_S 20
699 #define AR5K_DCU_LCL_IFS_AIFS_MAX 0xfc
700 #define AR5K_QUEUE_DFS_LOCAL_IFS(_q) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q)
706 #define AR5K_DCU_RETRY_LMT_BASE 0x1080
707 #define AR5K_DCU_RETRY_LMT_RTS 0x0000000f
708 #define AR5K_DCU_RETRY_LMT_RTS_S 0
709 #define AR5K_DCU_RETRY_LMT_STA_RTS 0x00003f00
710 #define AR5K_DCU_RETRY_LMT_STA_RTS_S 8
711 #define AR5K_DCU_RETRY_LMT_STA_DATA 0x000fc000
712 #define AR5K_DCU_RETRY_LMT_STA_DATA_S 14
713 #define AR5K_QUEUE_DFS_RETRY_LIMIT(_q) AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q)
718 #define AR5K_DCU_CHAN_TIME_BASE 0x10c0
719 #define AR5K_DCU_CHAN_TIME_DUR 0x000fffff
720 #define AR5K_DCU_CHAN_TIME_DUR_S 0
721 #define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000
722 #define AR5K_QUEUE_DFS_CHANNEL_TIME(_q) AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q)
736 #define AR5K_DCU_MISC_BASE 0x1100
737 #define AR5K_DCU_MISC_BACKOFF 0x0000003f
738 #define AR5K_DCU_MISC_ETS_RTS_POL 0x00000040
741 #define AR5K_DCU_MISC_ETS_CW_POL 0x00000080
743 #define AR5K_DCU_MISC_FRAG_WAIT 0x00000100
744 #define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200
745 #define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800
746 #define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000
747 #define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000
748 #define AR5K_DCU_MISC_VIRTCOL 0x0000c000
749 #define AR5K_DCU_MISC_VIRTCOL_NORMAL 0
750 #define AR5K_DCU_MISC_VIRTCOL_IGNORE 1
751 #define AR5K_DCU_MISC_BCN_ENABLE 0x00010000
752 #define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000
753 #define AR5K_DCU_MISC_ARBLOCK_CTL_S 17
754 #define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0
755 #define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1
756 #define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2
757 #define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000
758 #define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000
759 #define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000
760 #define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000
761 #define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000
762 #define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000
763 #define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q)
768 #define AR5K_DCU_SEQNUM_BASE 0x1140
769 #define AR5K_DCU_SEQNUM_M 0x00000fff
770 #define AR5K_QUEUE_DCU_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q)
775 #define AR5K_DCU_GBL_IFS_SIFS 0x1030
776 #define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff
781 #define AR5K_DCU_GBL_IFS_SLOT 0x1070
782 #define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff
787 #define AR5K_DCU_GBL_IFS_EIFS 0x10b0
788 #define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff
800 #define AR5K_DCU_GBL_IFS_MISC 0x10f0
801 #define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007
802 #define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008
803 #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0
804 #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC_S 4
805 #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00
806 #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S 10
807 #define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000
808 #define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST 0x00400000
809 #define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST 0x00800000
810 #define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS 0x01000000
815 #define AR5K_DCU_FP 0x1230
816 #define AR5K_DCU_FP_NOBURST_DCU_EN 0x00000001
817 #define AR5K_DCU_FP_NOBURST_EN 0x00000010
818 #define AR5K_DCU_FP_BURST_DCU_EN 0x00000020
823 #define AR5K_DCU_TXP 0x1270
824 #define AR5K_DCU_TXP_M 0x000003ff
825 #define AR5K_DCU_TXP_STATUS 0x00010000
832 #define AR5K_DCU_TX_FILTER_0_BASE 0x1038
833 #define AR5K_DCU_TX_FILTER_0(_n) (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64))
838 #define AR5K_DCU_TX_FILTER_1_BASE 0x103c
839 #define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + (_n * 64))
844 #define AR5K_DCU_TX_FILTER_CLR 0x143c
849 #define AR5K_DCU_TX_FILTER_SET 0x147c
854 #define AR5K_RESET_CTL 0x4000
855 #define AR5K_RESET_CTL_PCU 0x00000001
856 #define AR5K_RESET_CTL_DMA 0x00000002
857 #define AR5K_RESET_CTL_BASEBAND 0x00000002
858 #define AR5K_RESET_CTL_MAC 0x00000004
859 #define AR5K_RESET_CTL_PHY 0x00000008
860 #define AR5K_RESET_CTL_PCI 0x00000010
865 #define AR5K_SLEEP_CTL 0x4004
866 #define AR5K_SLEEP_CTL_SLDUR 0x0000ffff
867 #define AR5K_SLEEP_CTL_SLDUR_S 0
868 #define AR5K_SLEEP_CTL_SLE 0x00030000
869 #define AR5K_SLEEP_CTL_SLE_S 16
870 #define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000
871 #define AR5K_SLEEP_CTL_SLE_SLP 0x00010000
872 #define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000
873 #define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008
874 #define AR5K_SLEEP_CTL_DUR_TIM_POL 0x00040000
875 #define AR5K_SLEEP_CTL_DUR_WRITE_POL 0x00080000
876 #define AR5K_SLEEP_CTL_SLE_POL 0x00100000
881 #define AR5K_INTPEND 0x4008
882 #define AR5K_INTPEND_M 0x00000001
887 #define AR5K_SFR 0x400c
888 #define AR5K_SFR_EN 0x00000001
894 #define AR5K_PCICFG 0x4010
895 #define AR5K_PCICFG_EEAE 0x00000001
896 #define AR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002
897 #define AR5K_PCICFG_CLKRUNEN 0x00000004
898 #define AR5K_PCICFG_EESIZE 0x00000018
899 #define AR5K_PCICFG_EESIZE_S 3
900 #define AR5K_PCICFG_EESIZE_4K 0
901 #define AR5K_PCICFG_EESIZE_8K 1
902 #define AR5K_PCICFG_EESIZE_16K 2
903 #define AR5K_PCICFG_EESIZE_FAIL 3
904 #define AR5K_PCICFG_LED 0x00000060
905 #define AR5K_PCICFG_LED_NONE 0x00000000
906 #define AR5K_PCICFG_LED_PEND 0x00000020
907 #define AR5K_PCICFG_LED_ASSOC 0x00000040
908 #define AR5K_PCICFG_BUS_SEL 0x00000380
909 #define AR5K_PCICFG_CBEFIX_DIS 0x00000400
910 #define AR5K_PCICFG_SL_INTEN 0x00000800
911 #define AR5K_PCICFG_LED_BCTL 0x00001000
912 #define AR5K_PCICFG_RETRY_FIX 0x00001000
913 #define AR5K_PCICFG_SL_INPEN 0x00002000
914 #define AR5K_PCICFG_SPWR_DN 0x00010000
915 #define AR5K_PCICFG_LEDMODE 0x000e0000
916 #define AR5K_PCICFG_LEDMODE_PROP 0x00000000
917 #define AR5K_PCICFG_LEDMODE_PROM 0x00020000
918 #define AR5K_PCICFG_LEDMODE_PWR 0x00040000
919 #define AR5K_PCICFG_LEDMODE_RAND 0x00060000
920 #define AR5K_PCICFG_LEDBLINK 0x00700000
921 #define AR5K_PCICFG_LEDBLINK_S 20
922 #define AR5K_PCICFG_LEDSLOW 0x00800000
923 #define AR5K_PCICFG_LEDSTATE \
924 (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \
925 AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW)
926 #define AR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000
927 #define AR5K_PCICFG_SLEEP_CLOCK_RATE_S 24
945 #define AR5K_NUM_GPIO 6
947 #define AR5K_GPIOCR 0x4014
948 #define AR5K_GPIOCR_INT_ENA 0x00008000
949 #define AR5K_GPIOCR_INT_SELL 0x00000000
950 #define AR5K_GPIOCR_INT_SELH 0x00010000
951 #define AR5K_GPIOCR_IN(n) (0 << ((n) * 2))
952 #define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2))
953 #define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2))
954 #define AR5K_GPIOCR_OUT(n) (3 << ((n) * 2))
955 #define AR5K_GPIOCR_INT_SEL(n) ((n) << 12)
960 #define AR5K_GPIODO 0x4018
965 #define AR5K_GPIODI 0x401c
966 #define AR5K_GPIODI_M 0x0000002f
971 #define AR5K_SREV 0x4020
972 #define AR5K_SREV_REV 0x0000000f
973 #define AR5K_SREV_REV_S 0
974 #define AR5K_SREV_VER 0x000000ff
975 #define AR5K_SREV_VER_S 4
980 #define AR5K_TXEPOST 0x4028
985 #define AR5K_QCU_SLEEP_MASK 0x402c
995 #define AR5K_5414_CBCFG 0x4068
996 #define AR5K_5414_CBCFG_BUF_DIS 0x10
1002 #define AR5K_PCIE_PM_CTL 0x4068
1004 #define AR5K_PCIE_PM_CTL_L1_WHEN_D2 0x00000001
1006 #define AR5K_PCIE_PM_CTL_L0_L0S_CLEAR 0x00000002
1007 #define AR5K_PCIE_PM_CTL_L0_L0S_EN 0x00000004
1008 #define AR5K_PCIE_PM_CTL_LDRESET_EN 0x00000008
1011 #define AR5K_PCIE_PM_CTL_PME_EN 0x00000010
1012 #define AR5K_PCIE_PM_CTL_AUX_PWR_DET 0x00000020
1013 #define AR5K_PCIE_PM_CTL_PME_CLEAR 0x00000040
1014 #define AR5K_PCIE_PM_CTL_PSM_D0 0x00000080
1015 #define AR5K_PCIE_PM_CTL_PSM_D1 0x00000100
1016 #define AR5K_PCIE_PM_CTL_PSM_D2 0x00000200
1017 #define AR5K_PCIE_PM_CTL_PSM_D3 0x00000400
1022 #define AR5K_PCIE_WAEN 0x407c
1028 #define AR5K_PCIE_SERDES 0x4080
1029 #define AR5K_PCIE_SERDES_RESET 0x4084
1068 #define AR5K_EEPROM_BASE 0x6000
1073 #define AR5K_EEPROM_DATA_5211 0x6004
1074 #define AR5K_EEPROM_DATA_5210 0x6800
1075 #define AR5K_EEPROM_DATA (ah->ah_version == AR5K_AR5210 ? \
1076 AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211)
1081 #define AR5K_EEPROM_CMD 0x6008
1082 #define AR5K_EEPROM_CMD_READ 0x00000001
1083 #define AR5K_EEPROM_CMD_WRITE 0x00000002
1084 #define AR5K_EEPROM_CMD_RESET 0x00000004
1089 #define AR5K_EEPROM_STAT_5210 0x6c00
1090 #define AR5K_EEPROM_STAT_5211 0x600c
1091 #define AR5K_EEPROM_STATUS (ah->ah_version == AR5K_AR5210 ? \
1092 AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211)
1093 #define AR5K_EEPROM_STAT_RDERR 0x00000001
1094 #define AR5K_EEPROM_STAT_RDDONE 0x00000002
1095 #define AR5K_EEPROM_STAT_WRERR 0x00000004
1096 #define AR5K_EEPROM_STAT_WRDONE 0x00000008
1101 #define AR5K_EEPROM_CFG 0x6010
1102 #define AR5K_EEPROM_CFG_SIZE 0x00000003
1103 #define AR5K_EEPROM_CFG_SIZE_AUTO 0
1104 #define AR5K_EEPROM_CFG_SIZE_4KBIT 1
1105 #define AR5K_EEPROM_CFG_SIZE_8KBIT 2
1106 #define AR5K_EEPROM_CFG_SIZE_16KBIT 3
1107 #define AR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004
1108 #define AR5K_EEPROM_CFG_CLK_RATE 0x00000018
1109 #define AR5K_EEPROM_CFG_CLK_RATE_S 3
1110 #define AR5K_EEPROM_CFG_CLK_RATE_156KHZ 0
1111 #define AR5K_EEPROM_CFG_CLK_RATE_312KHZ 1
1112 #define AR5K_EEPROM_CFG_CLK_RATE_625KHZ 2
1113 #define AR5K_EEPROM_CFG_PROT_KEY 0x00ffff00
1114 #define AR5K_EEPROM_CFG_PROT_KEY_S 8
1115 #define AR5K_EEPROM_CFG_LIND_EN 0x01000000
1130 #define AR5K_PCU_MIN 0x8000
1131 #define AR5K_PCU_MAX 0x8fff
1136 #define AR5K_STA_ID0 0x8000
1137 #define AR5K_STA_ID0_ARRD_L32 0xffffffff
1142 #define AR5K_STA_ID1 0x8004
1143 #define AR5K_STA_ID1_ADDR_U16 0x0000ffff
1144 #define AR5K_STA_ID1_AP 0x00010000
1145 #define AR5K_STA_ID1_ADHOC 0x00020000
1146 #define AR5K_STA_ID1_PWR_SV 0x00040000
1147 #define AR5K_STA_ID1_NO_KEYSRCH 0x00080000
1148 #define AR5K_STA_ID1_NO_PSPOLL 0x00100000
1149 #define AR5K_STA_ID1_PCF_5211 0x00100000
1150 #define AR5K_STA_ID1_PCF_5210 0x00200000
1151 #define AR5K_STA_ID1_PCF (ah->ah_version == AR5K_AR5210 ? \
1152 AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211)
1153 #define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000
1154 #define AR5K_STA_ID1_DESC_ANTENNA 0x00400000
1155 #define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000
1156 #define AR5K_STA_ID1_ACKCTS_6MB 0x01000000
1157 #define AR5K_STA_ID1_BASE_RATE_11B 0x02000000
1158 #define AR5K_STA_ID1_SELFGEN_DEF_ANT 0x04000000
1159 #define AR5K_STA_ID1_CRYPT_MIC_EN 0x08000000
1160 #define AR5K_STA_ID1_KEYSRCH_MODE 0x10000000
1161 #define AR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000
1162 #define AR5K_STA_ID1_CBCIV_ENDIAN 0x40000000
1163 #define AR5K_STA_ID1_KEYSRCH_MCAST 0x80000000
1165 #define AR5K_STA_ID1_ANTENNA_SETTINGS (AR5K_STA_ID1_DEFAULT_ANTENNA | \
1166 AR5K_STA_ID1_DESC_ANTENNA | \
1167 AR5K_STA_ID1_RTS_DEF_ANTENNA | \
1168 AR5K_STA_ID1_SELFGEN_DEF_ANT)
1173 #define AR5K_BSS_ID0 0x8008
1180 #define AR5K_BSS_ID1 0x800c
1181 #define AR5K_BSS_ID1_AID 0xffff0000
1182 #define AR5K_BSS_ID1_AID_S 16
1187 #define AR5K_SLOT_TIME 0x8010
1192 #define AR5K_TIME_OUT 0x8014
1193 #define AR5K_TIME_OUT_ACK 0x00001fff
1194 #define AR5K_TIME_OUT_ACK_S 0
1195 #define AR5K_TIME_OUT_CTS 0x1fff0000
1196 #define AR5K_TIME_OUT_CTS_S 16
1201 #define AR5K_RSSI_THR 0x8018
1202 #define AR5K_RSSI_THR_M 0x000000ff
1203 #define AR5K_RSSI_THR_BMISS_5210 0x00000700
1204 #define AR5K_RSSI_THR_BMISS_5210_S 8
1205 #define AR5K_RSSI_THR_BMISS_5211 0x0000ff00
1206 #define AR5K_RSSI_THR_BMISS_5211_S 8
1207 #define AR5K_RSSI_THR_BMISS (ah->ah_version == AR5K_AR5210 ? \
1208 AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211)
1209 #define AR5K_RSSI_THR_BMISS_S 8
1224 #define AR5K_NODCU_RETRY_LMT 0x801c
1225 #define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f
1226 #define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0
1227 #define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0
1228 #define AR5K_NODCU_RETRY_LMT_LG_RETRY_S 4
1229 #define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00
1230 #define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S 8
1231 #define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000
1232 #define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S 14
1233 #define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000
1234 #define AR5K_NODCU_RETRY_LMT_CW_MIN_S 20
1239 #define AR5K_USEC_5210 0x8020
1240 #define AR5K_USEC_5211 0x801c
1241 #define AR5K_USEC (ah->ah_version == AR5K_AR5210 ? \
1242 AR5K_USEC_5210 : AR5K_USEC_5211)
1243 #define AR5K_USEC_1 0x0000007f
1244 #define AR5K_USEC_1_S 0
1245 #define AR5K_USEC_32 0x00003f80
1246 #define AR5K_USEC_32_S 7
1247 #define AR5K_USEC_TX_LATENCY_5211 0x007fc000
1248 #define AR5K_USEC_TX_LATENCY_5211_S 14
1249 #define AR5K_USEC_RX_LATENCY_5211 0x1f800000
1250 #define AR5K_USEC_RX_LATENCY_5211_S 23
1251 #define AR5K_USEC_TX_LATENCY_5210 0x000fc000
1252 #define AR5K_USEC_TX_LATENCY_5210_S 14
1253 #define AR5K_USEC_RX_LATENCY_5210 0x03f00000
1254 #define AR5K_USEC_RX_LATENCY_5210_S 20
1259 #define AR5K_BEACON_5210 0x8024
1260 #define AR5K_BEACON_5211 0x8020
1261 #define AR5K_BEACON (ah->ah_version == AR5K_AR5210 ? \
1262 AR5K_BEACON_5210 : AR5K_BEACON_5211)
1263 #define AR5K_BEACON_PERIOD 0x0000ffff
1264 #define AR5K_BEACON_PERIOD_S 0
1265 #define AR5K_BEACON_TIM 0x007f0000
1266 #define AR5K_BEACON_TIM_S 16
1267 #define AR5K_BEACON_ENABLE 0x00800000
1268 #define AR5K_BEACON_RESET_TSF 0x01000000
1273 #define AR5K_CFP_PERIOD_5210 0x8028
1274 #define AR5K_CFP_PERIOD_5211 0x8024
1275 #define AR5K_CFP_PERIOD (ah->ah_version == AR5K_AR5210 ? \
1276 AR5K_CFP_PERIOD_5210 : AR5K_CFP_PERIOD_5211)
1281 #define AR5K_TIMER0_5210 0x802c
1282 #define AR5K_TIMER0_5211 0x8028
1283 #define AR5K_TIMER0 (ah->ah_version == AR5K_AR5210 ? \
1284 AR5K_TIMER0_5210 : AR5K_TIMER0_5211)
1289 #define AR5K_TIMER1_5210 0x8030
1290 #define AR5K_TIMER1_5211 0x802c
1291 #define AR5K_TIMER1 (ah->ah_version == AR5K_AR5210 ? \
1292 AR5K_TIMER1_5210 : AR5K_TIMER1_5211)
1297 #define AR5K_TIMER2_5210 0x8034
1298 #define AR5K_TIMER2_5211 0x8030
1299 #define AR5K_TIMER2 (ah->ah_version == AR5K_AR5210 ? \
1300 AR5K_TIMER2_5210 : AR5K_TIMER2_5211)
1305 #define AR5K_TIMER3_5210 0x8038
1306 #define AR5K_TIMER3_5211 0x8034
1307 #define AR5K_TIMER3 (ah->ah_version == AR5K_AR5210 ? \
1308 AR5K_TIMER3_5210 : AR5K_TIMER3_5211)
1314 #define AR5K_IFS0 0x8040
1315 #define AR5K_IFS0_SIFS 0x000007ff
1316 #define AR5K_IFS0_SIFS_S 0
1317 #define AR5K_IFS0_DIFS 0x007ff800
1318 #define AR5K_IFS0_DIFS_S 11
1323 #define AR5K_IFS1 0x8044
1324 #define AR5K_IFS1_PIFS 0x00000fff
1325 #define AR5K_IFS1_PIFS_S 0
1326 #define AR5K_IFS1_EIFS 0x03fff000
1327 #define AR5K_IFS1_EIFS_S 12
1328 #define AR5K_IFS1_CS_EN 0x04000000
1329 #define AR5K_IFS1_CS_EN_S 26
1334 #define AR5K_CFP_DUR_5210 0x8048
1335 #define AR5K_CFP_DUR_5211 0x8038
1336 #define AR5K_CFP_DUR (ah->ah_version == AR5K_AR5210 ? \
1337 AR5K_CFP_DUR_5210 : AR5K_CFP_DUR_5211)
1342 #define AR5K_RX_FILTER_5210 0x804c
1343 #define AR5K_RX_FILTER_5211 0x803c
1344 #define AR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \
1345 AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211)
1346 #define AR5K_RX_FILTER_UCAST 0x00000001
1347 #define AR5K_RX_FILTER_MCAST 0x00000002
1348 #define AR5K_RX_FILTER_BCAST 0x00000004
1349 #define AR5K_RX_FILTER_CONTROL 0x00000008
1350 #define AR5K_RX_FILTER_BEACON 0x00000010
1351 #define AR5K_RX_FILTER_PROM 0x00000020
1352 #define AR5K_RX_FILTER_XRPOLL 0x00000040
1353 #define AR5K_RX_FILTER_PROBEREQ 0x00000080
1354 #define AR5K_RX_FILTER_PHYERR_5212 0x00000100
1355 #define AR5K_RX_FILTER_RADARERR_5212 0x00000200
1356 #define AR5K_RX_FILTER_PHYERR_5211 0x00000040
1357 #define AR5K_RX_FILTER_RADARERR_5211 0x00000080
1358 #define AR5K_RX_FILTER_PHYERR \
1359 ((ah->ah_version == AR5K_AR5211 ? \
1360 AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212))
1361 #define AR5K_RX_FILTER_RADARERR \
1362 ((ah->ah_version == AR5K_AR5211 ? \
1363 AR5K_RX_FILTER_RADARERR_5211 : AR5K_RX_FILTER_RADARERR_5212))
1368 #define AR5K_MCAST_FILTER0_5210 0x8050
1369 #define AR5K_MCAST_FILTER0_5211 0x8040
1370 #define AR5K_MCAST_FILTER0 (ah->ah_version == AR5K_AR5210 ? \
1371 AR5K_MCAST_FILTER0_5210 : AR5K_MCAST_FILTER0_5211)
1376 #define AR5K_MCAST_FILTER1_5210 0x8054
1377 #define AR5K_MCAST_FILTER1_5211 0x8044
1378 #define AR5K_MCAST_FILTER1 (ah->ah_version == AR5K_AR5210 ? \
1379 AR5K_MCAST_FILTER1_5210 : AR5K_MCAST_FILTER1_5211)
1385 #define AR5K_TX_MASK0 0x8058
1390 #define AR5K_TX_MASK1 0x805c
1395 #define AR5K_CLR_TMASK 0x8060
1400 #define AR5K_TRIG_LVL 0x8064
1408 #define AR5K_DIAG_SW_5210 0x8068
1409 #define AR5K_DIAG_SW_5211 0x8048
1410 #define AR5K_DIAG_SW (ah->ah_version == AR5K_AR5210 ? \
1411 AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211)
1412 #define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001
1413 #define AR5K_DIAG_SW_DIS_ACK 0x00000002
1414 #define AR5K_DIAG_SW_DIS_CTS 0x00000004
1415 #define AR5K_DIAG_SW_DIS_ENC 0x00000008
1416 #define AR5K_DIAG_SW_DIS_DEC 0x00000010
1417 #define AR5K_DIAG_SW_DIS_TX_5210 0x00000020
1418 #define AR5K_DIAG_SW_DIS_RX_5210 0x00000040
1419 #define AR5K_DIAG_SW_DIS_RX_5211 0x00000020
1420 #define AR5K_DIAG_SW_DIS_RX (ah->ah_version == AR5K_AR5210 ? \
1421 AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211)
1422 #define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080
1423 #define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040
1424 #define AR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \
1425 AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211)
1426 #define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100
1427 #define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080
1428 #define AR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \
1429 AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211)
1430 #define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200
1431 #define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100
1432 #define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \
1433 AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211)
1434 #define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400
1435 #define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200
1436 #define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \
1437 AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211)
1438 #define AR5K_DIAG_SW_ECO_ENABLE 0x00000400
1439 #define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800
1440 #define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00
1441 #define AR5K_DIAG_SW_SCRAM_SEED_S 10
1442 #define AR5K_DIAG_SW_DIS_SEQ_INC_5210 0x00040000
1443 #define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000
1444 #define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000
1445 #define AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \
1446 AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211)
1447 #define AR5K_DIAG_SW_OBSPT_M 0x000c0000
1448 #define AR5K_DIAG_SW_OBSPT_S 18
1449 #define AR5K_DIAG_SW_RX_CLEAR_HIGH 0x00100000
1450 #define AR5K_DIAG_SW_IGNORE_CARR_SENSE 0x00200000
1451 #define AR5K_DIAG_SW_CHANNEL_IDLE_HIGH 0x00400000
1452 #define AR5K_DIAG_SW_PHEAR_ME 0x00800000
1457 #define AR5K_TSF_L32_5210 0x806c
1458 #define AR5K_TSF_L32_5211 0x804c
1459 #define AR5K_TSF_L32 (ah->ah_version == AR5K_AR5210 ? \
1460 AR5K_TSF_L32_5210 : AR5K_TSF_L32_5211)
1465 #define AR5K_TSF_U32_5210 0x8070
1466 #define AR5K_TSF_U32_5211 0x8050
1467 #define AR5K_TSF_U32 (ah->ah_version == AR5K_AR5210 ? \
1468 AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211)
1473 #define AR5K_LAST_TSTP 0x8080
1478 #define AR5K_ADDAC_TEST 0x8054
1479 #define AR5K_ADDAC_TEST_TXCONT 0x00000001
1480 #define AR5K_ADDAC_TEST_TST_MODE 0x00000002
1481 #define AR5K_ADDAC_TEST_LOOP_EN 0x00000004
1482 #define AR5K_ADDAC_TEST_LOOP_LEN 0x00000008
1483 #define AR5K_ADDAC_TEST_USE_U8 0x00004000
1484 #define AR5K_ADDAC_TEST_MSB 0x00008000
1485 #define AR5K_ADDAC_TEST_TRIG_SEL 0x00010000
1486 #define AR5K_ADDAC_TEST_TRIG_PTY 0x00020000
1487 #define AR5K_ADDAC_TEST_RXCONT 0x00040000
1488 #define AR5K_ADDAC_TEST_CAPTURE 0x00080000
1489 #define AR5K_ADDAC_TEST_TST_ARM 0x00100000
1494 #define AR5K_DEFAULT_ANTENNA 0x8058
1500 #define AR5K_FRAME_CTL_QOSM 0x805c
1505 #define AR5K_SEQ_MASK 0x8060
1510 #define AR5K_RETRY_CNT 0x8084
1511 #define AR5K_RETRY_CNT_SSH 0x0000003f
1512 #define AR5K_RETRY_CNT_SLG 0x00000fc0
1517 #define AR5K_BACKOFF 0x8088
1518 #define AR5K_BACKOFF_CW 0x000003ff
1519 #define AR5K_BACKOFF_CNT 0x03ff0000
1526 #define AR5K_NAV_5210 0x808c
1527 #define AR5K_NAV_5211 0x8084
1528 #define AR5K_NAV (ah->ah_version == AR5K_AR5210 ? \
1529 AR5K_NAV_5210 : AR5K_NAV_5211)
1541 #define AR5K_RTS_OK_5210 0x8090
1542 #define AR5K_RTS_OK_5211 0x8088
1543 #define AR5K_RTS_OK (ah->ah_version == AR5K_AR5210 ? \
1544 AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211)
1549 #define AR5K_RTS_FAIL_5210 0x8094
1550 #define AR5K_RTS_FAIL_5211 0x808c
1551 #define AR5K_RTS_FAIL (ah->ah_version == AR5K_AR5210 ? \
1552 AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211)
1557 #define AR5K_ACK_FAIL_5210 0x8098
1558 #define AR5K_ACK_FAIL_5211 0x8090
1559 #define AR5K_ACK_FAIL (ah->ah_version == AR5K_AR5210 ? \
1560 AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211)
1565 #define AR5K_FCS_FAIL_5210 0x809c
1566 #define AR5K_FCS_FAIL_5211 0x8094
1567 #define AR5K_FCS_FAIL (ah->ah_version == AR5K_AR5210 ? \
1568 AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211)
1573 #define AR5K_BEACON_CNT_5210 0x80a0
1574 #define AR5K_BEACON_CNT_5211 0x8098
1575 #define AR5K_BEACON_CNT (ah->ah_version == AR5K_AR5210 ? \
1576 AR5K_BEACON_CNT_5210 : AR5K_BEACON_CNT_5211)
1584 #define AR5K_TPC 0x80e8
1585 #define AR5K_TPC_ACK 0x0000003f
1586 #define AR5K_TPC_ACK_S 0
1587 #define AR5K_TPC_CTS 0x00003f00
1588 #define AR5K_TPC_CTS_S 8
1589 #define AR5K_TPC_CHIRP 0x003f0000
1590 #define AR5K_TPC_CHIRP_S 16
1591 #define AR5K_TPC_DOPPLER 0x0f000000
1592 #define AR5K_TPC_DOPPLER_S 24
1597 #define AR5K_XRMODE 0x80c0
1598 #define AR5K_XRMODE_POLL_TYPE_M 0x0000003f
1599 #define AR5K_XRMODE_POLL_TYPE_S 0
1600 #define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c
1601 #define AR5K_XRMODE_POLL_SUBTYPE_S 2
1602 #define AR5K_XRMODE_POLL_WAIT_ALL 0x00000080
1603 #define AR5K_XRMODE_SIFS_DELAY 0x000fff00
1604 #define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000
1605 #define AR5K_XRMODE_FRAME_HOLD_S 20
1610 #define AR5K_XRDELAY 0x80c4
1611 #define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff
1612 #define AR5K_XRDELAY_SLOT_DELAY_S 0
1613 #define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000
1614 #define AR5K_XRDELAY_CHIRP_DELAY_S 16
1619 #define AR5K_XRTIMEOUT 0x80c8
1620 #define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff
1621 #define AR5K_XRTIMEOUT_CHIRP_S 0
1622 #define AR5K_XRTIMEOUT_POLL_M 0xffff0000
1623 #define AR5K_XRTIMEOUT_POLL_S 16
1628 #define AR5K_XRCHIRP 0x80cc
1629 #define AR5K_XRCHIRP_SEND 0x00000001
1630 #define AR5K_XRCHIRP_GAP 0xffff0000
1635 #define AR5K_XRSTOMP 0x80d0
1636 #define AR5K_XRSTOMP_TX 0x00000001
1637 #define AR5K_XRSTOMP_RX 0x00000002
1638 #define AR5K_XRSTOMP_TX_RSSI 0x00000004
1639 #define AR5K_XRSTOMP_TX_BSSID 0x00000008
1640 #define AR5K_XRSTOMP_DATA 0x00000010
1641 #define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00
1646 #define AR5K_SLEEP0 0x80d4
1647 #define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff
1648 #define AR5K_SLEEP0_NEXT_DTIM_S 0
1649 #define AR5K_SLEEP0_ASSUME_DTIM 0x00080000
1650 #define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000
1651 #define AR5K_SLEEP0_CABTO 0xff000000
1652 #define AR5K_SLEEP0_CABTO_S 24
1657 #define AR5K_SLEEP1 0x80d8
1658 #define AR5K_SLEEP1_NEXT_TIM 0x0007ffff
1659 #define AR5K_SLEEP1_NEXT_TIM_S 0
1660 #define AR5K_SLEEP1_BEACON_TO 0xff000000
1661 #define AR5K_SLEEP1_BEACON_TO_S 24
1666 #define AR5K_SLEEP2 0x80dc
1667 #define AR5K_SLEEP2_TIM_PER 0x0000ffff
1668 #define AR5K_SLEEP2_TIM_PER_S 0
1669 #define AR5K_SLEEP2_DTIM_PER 0xffff0000
1670 #define AR5K_SLEEP2_DTIM_PER_S 16
1678 #define AR5K_TXPC 0x80e8
1679 #define AR5K_TXPC_ACK_M 0x0000003f
1680 #define AR5K_TXPC_ACK_S 0
1681 #define AR5K_TXPC_CTS_M 0x00003f00
1682 #define AR5K_TXPC_CTS_S 8
1683 #define AR5K_TXPC_CHIRP_M 0x003f0000
1684 #define AR5K_TXPC_CHIRP_S 16
1685 #define AR5K_TXPC_DOPPLER 0x0f000000
1686 #define AR5K_TXPC_DOPPLER_S 24
1697 #define AR5K_PROFCNT_TX 0x80ec
1698 #define AR5K_PROFCNT_RX 0x80f0
1699 #define AR5K_PROFCNT_RXCLR 0x80f4
1700 #define AR5K_PROFCNT_CYCLE 0x80f8
1705 #define AR5K_QUIET_CTL1 0x80fc
1706 #define AR5K_QUIET_CTL1_NEXT_QT_TSF 0x0000ffff
1707 #define AR5K_QUIET_CTL1_NEXT_QT_TSF_S 0
1708 #define AR5K_QUIET_CTL1_QT_EN 0x00010000
1709 #define AR5K_QUIET_CTL1_ACK_CTS_EN 0x00020000
1711 #define AR5K_QUIET_CTL2 0x8100
1712 #define AR5K_QUIET_CTL2_QT_PER 0x0000ffff
1713 #define AR5K_QUIET_CTL2_QT_PER_S 0
1714 #define AR5K_QUIET_CTL2_QT_DUR 0xffff0000
1715 #define AR5K_QUIET_CTL2_QT_DUR_S 16
1720 #define AR5K_TSF_PARM 0x8104
1721 #define AR5K_TSF_PARM_INC 0x000000ff
1722 #define AR5K_TSF_PARM_INC_S 0
1727 #define AR5K_QOS_NOACK 0x8108
1728 #define AR5K_QOS_NOACK_2BIT_VALUES 0x0000000f
1729 #define AR5K_QOS_NOACK_2BIT_VALUES_S 0
1730 #define AR5K_QOS_NOACK_BIT_OFFSET 0x00000070
1731 #define AR5K_QOS_NOACK_BIT_OFFSET_S 4
1732 #define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000180
1733 #define AR5K_QOS_NOACK_BYTE_OFFSET_S 7
1738 #define AR5K_PHY_ERR_FIL 0x810c
1739 #define AR5K_PHY_ERR_FIL_RADAR 0x00000020
1740 #define AR5K_PHY_ERR_FIL_OFDM 0x00020000
1741 #define AR5K_PHY_ERR_FIL_CCK 0x02000000
1746 #define AR5K_XRLAT_TX 0x8110
1751 #define AR5K_ACKSIFS 0x8114
1752 #define AR5K_ACKSIFS_INC 0x00000000
1757 #define AR5K_MIC_QOS_CTL 0x8118
1758 #define AR5K_MIC_QOS_CTL_OFF(_n) (1 << (_n * 2))
1759 #define AR5K_MIC_QOS_CTL_MQ_EN 0x00010000
1764 #define AR5K_MIC_QOS_SEL 0x811c
1765 #define AR5K_MIC_QOS_SEL_OFF(_n) (1 << (_n * 4))
1770 #define AR5K_MISC_MODE 0x8120
1771 #define AR5K_MISC_MODE_FBSSID_MATCH 0x00000001
1772 #define AR5K_MISC_MODE_ACKSIFS_MEM 0x00000002
1773 #define AR5K_MISC_MODE_COMBINED_MIC 0x00000004
1779 #define AR5K_OFDM_FIL_CNT 0x8124
1784 #define AR5K_CCK_FIL_CNT 0x8128
1789 #define AR5K_PHYERR_CNT1 0x812c
1790 #define AR5K_PHYERR_CNT1_MASK 0x8130
1792 #define AR5K_PHYERR_CNT2 0x8134
1793 #define AR5K_PHYERR_CNT2_MASK 0x8138
1796 #define ATH5K_PHYERR_CNT_MAX 0x00c00000
1801 #define AR5K_TSF_THRES 0x813c
1811 #define AR5K_RATE_ACKSIFS_BASE 0x8680
1812 #define AR5K_RATE_ACKSIFS(_n) (AR5K_RATE_ACKSIFS_BSE + ((_n) << 2))
1813 #define AR5K_RATE_ACKSIFS_NORMAL 0x00000001
1814 #define AR5K_RATE_ACKSIFS_TURBO 0x00000400
1819 #define AR5K_RATE_DUR_BASE 0x8700
1820 #define AR5K_RATE_DUR(_n) (AR5K_RATE_DUR_BASE + ((_n) << 2))
1826 #define AR5K_RATE2DB_BASE 0x87c0
1827 #define AR5K_RATE2DB(_n) (AR5K_RATE2DB_BASE + ((_n) << 2))
1833 #define AR5K_DB2RATE_BASE 0x87e0
1834 #define AR5K_DB2RATE(_n) (AR5K_DB2RATE_BASE + ((_n) << 2))
1838 #define AR5K_KEYTABLE_SIZE_5210 64
1839 #define AR5K_KEYTABLE_SIZE_5211 128
1846 #define AR5K_PHY_BASE 0x9800
1847 #define AR5K_PHY(_n) (AR5K_PHY_BASE + ((_n) << 2))
1852 #define AR5K_PHY_TST2 0x9800
1853 #define AR5K_PHY_TST2_TRIG_SEL 0x00000007
1854 #define AR5K_PHY_TST2_TRIG 0x00000010
1855 #define AR5K_PHY_TST2_CBUS_MODE 0x00000060
1856 #define AR5K_PHY_TST2_CLK32 0x00000400
1857 #define AR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800
1858 #define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000
1859 #define AR5K_PHY_TST2_RFSILENT_EN 0x00002000
1860 #define AR5K_PHY_TST2_ALT_RFDATA 0x00004000
1861 #define AR5K_PHY_TST2_MINI_OBS_EN 0x00008000
1862 #define AR5K_PHY_TST2_RX2_IS_RX5_INV 0x00010000
1863 #define AR5K_PHY_TST2_SLOW_CLK160 0x00020000
1864 #define AR5K_PHY_TST2_AGC_OBS_SEL_3 0x00040000
1865 #define AR5K_PHY_TST2_BBB_OBS_SEL 0x00080000
1866 #define AR5K_PHY_TST2_ADC_OBS_SEL 0x00800000
1867 #define AR5K_PHY_TST2_RX_CLR_SEL 0x08000000
1868 #define AR5K_PHY_TST2_FORCE_AGC_CLR 0x10000000
1869 #define AR5K_PHY_SHIFT_2GHZ 0x00004007
1870 #define AR5K_PHY_SHIFT_5GHZ 0x00000007
1882 #define AR5K_PHY_TURBO 0x9804
1883 #define AR5K_PHY_TURBO_MODE 0x00000001
1884 #define AR5K_PHY_TURBO_SHORT 0x00000002
1885 #define AR5K_PHY_TURBO_MIMO 0x00000004
1891 #define AR5K_PHY_AGC 0x9808
1892 #define AR5K_PHY_TST1 0x9808
1893 #define AR5K_PHY_AGC_DISABLE 0x08000000
1894 #define AR5K_PHY_TST1_TXHOLD 0x00003800
1895 #define AR5K_PHY_TST1_TXSRC_SRC 0x00000002
1896 #define AR5K_PHY_TST1_TXSRC_SRC_S 1
1897 #define AR5K_PHY_TST1_TXSRC_ALT 0x00000080
1898 #define AR5K_PHY_TST1_TXSRC_ALT_S 7
1904 #define AR5K_PHY_TIMING_3 0x9814
1905 #define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000
1906 #define AR5K_PHY_TIMING_3_DSC_MAN_S 17
1907 #define AR5K_PHY_TIMING_3_DSC_EXP 0x0001e000
1908 #define AR5K_PHY_TIMING_3_DSC_EXP_S 13
1913 #define AR5K_PHY_CHIP_ID 0x9818
1918 #define AR5K_PHY_ACT 0x981c
1919 #define AR5K_PHY_ACT_ENABLE 0x00000001
1920 #define AR5K_PHY_ACT_DISABLE 0x00000002
1925 #define AR5K_PHY_RF_CTL2 0x9824
1926 #define AR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f
1927 #define AR5K_PHY_RF_CTL2_TXF2TXD_START_S 0
1929 #define AR5K_PHY_RF_CTL3 0x9828
1930 #define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000ff00
1931 #define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 8
1933 #define AR5K_PHY_ADC_CTL 0x982c
1934 #define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF 0x00000003
1935 #define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_S 0
1936 #define AR5K_PHY_ADC_CTL_PWD_DAC_OFF 0x00002000
1937 #define AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OFF 0x00004000
1938 #define AR5K_PHY_ADC_CTL_PWD_ADC_OFF 0x00008000
1939 #define AR5K_PHY_ADC_CTL_INBUFGAIN_ON 0x00030000
1940 #define AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S 16
1942 #define AR5K_PHY_RF_CTL4 0x9834
1943 #define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001
1944 #define AR5K_PHY_RF_CTL4_TXF2XPA_B_ON 0x00000100
1945 #define AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF 0x00010000
1946 #define AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF 0x01000000
1952 #define AR5K_PHY_PA_CTL 0x9838
1953 #define AR5K_PHY_PA_CTL_XPA_A_HI 0x00000001
1954 #define AR5K_PHY_PA_CTL_XPA_B_HI 0x00000002
1955 #define AR5K_PHY_PA_CTL_XPA_A_EN 0x00000004
1956 #define AR5K_PHY_PA_CTL_XPA_B_EN 0x00000008
1961 #define AR5K_PHY_SETTLING 0x9844
1962 #define AR5K_PHY_SETTLING_AGC 0x0000007f
1963 #define AR5K_PHY_SETTLING_AGC_S 0
1964 #define AR5K_PHY_SETTLING_SWITCH 0x00003f80
1965 #define AR5K_PHY_SETTLING_SWITCH_S 7
1970 #define AR5K_PHY_GAIN 0x9848
1971 #define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000
1972 #define AR5K_PHY_GAIN_TXRX_ATTEN_S 12
1973 #define AR5K_PHY_GAIN_TXRX_RF_MAX 0x007c0000
1974 #define AR5K_PHY_GAIN_TXRX_RF_MAX_S 18
1976 #define AR5K_PHY_GAIN_OFFSET 0x984c
1977 #define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000
1983 #define AR5K_PHY_DESIRED_SIZE 0x9850
1984 #define AR5K_PHY_DESIRED_SIZE_ADC 0x000000ff
1985 #define AR5K_PHY_DESIRED_SIZE_ADC_S 0
1986 #define AR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00
1987 #define AR5K_PHY_DESIRED_SIZE_PGA_S 8
1988 #define AR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000
1989 #define AR5K_PHY_DESIRED_SIZE_TOT_S 20
1995 #define AR5K_PHY_SIG 0x9858
1996 #define AR5K_PHY_SIG_FIRSTEP 0x0003f000
1997 #define AR5K_PHY_SIG_FIRSTEP_S 12
1998 #define AR5K_PHY_SIG_FIRPWR 0x03fc0000
1999 #define AR5K_PHY_SIG_FIRPWR_S 18
2005 #define AR5K_PHY_AGCCOARSE 0x985c
2006 #define AR5K_PHY_AGCCOARSE_LO 0x00007f80
2007 #define AR5K_PHY_AGCCOARSE_LO_S 7
2008 #define AR5K_PHY_AGCCOARSE_HI 0x003f8000
2009 #define AR5K_PHY_AGCCOARSE_HI_S 15
2014 #define AR5K_PHY_AGCCTL 0x9860
2015 #define AR5K_PHY_AGCCTL_CAL 0x00000001
2016 #define AR5K_PHY_AGCCTL_NF 0x00000002
2017 #define AR5K_PHY_AGCCTL_OFDM_DIV_DIS 0x00000008
2018 #define AR5K_PHY_AGCCTL_NF_EN 0x00008000
2019 #define AR5K_PHY_AGCTL_FLTR_CAL 0x00010000
2020 #define AR5K_PHY_AGCCTL_NF_NOUPDATE 0x00020000
2025 #define AR5K_PHY_NF 0x9864
2026 #define AR5K_PHY_NF_M 0x000001ff
2027 #define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9))
2028 #define AR5K_PHY_NF_THRESH62 0x0007f000
2029 #define AR5K_PHY_NF_THRESH62_S 12
2030 #define AR5K_PHY_NF_MINCCA_PWR 0x0ff80000
2031 #define AR5K_PHY_NF_MINCCA_PWR_S 19
2036 #define AR5K_PHY_ADCSAT 0x9868
2037 #define AR5K_PHY_ADCSAT_ICNT 0x0001f800
2038 #define AR5K_PHY_ADCSAT_ICNT_S 11
2039 #define AR5K_PHY_ADCSAT_THR 0x000007e0
2040 #define AR5K_PHY_ADCSAT_THR_S 5
2047 #define AR5K_PHY_WEAK_OFDM_HIGH_THR 0x9868
2048 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT 0x0000001f
2049 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT_S 0
2050 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1 0x00fe0000
2051 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_S 17
2052 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2 0x7f000000
2053 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S 24
2056 #define AR5K_PHY_WEAK_OFDM_LOW_THR 0x986c
2057 #define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN 0x00000001
2058 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT 0x00003f00
2059 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S 8
2060 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M1 0x001fc000
2061 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S 14
2062 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2 0x0fe00000
2063 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S 21
2069 #define AR5K_PHY_SCR 0x9870
2071 #define AR5K_PHY_SLMT 0x9874
2072 #define AR5K_PHY_SLMT_32MHZ 0x0000007f
2074 #define AR5K_PHY_SCAL 0x9878
2075 #define AR5K_PHY_SCAL_32MHZ 0x0000000e
2076 #define AR5K_PHY_SCAL_32MHZ_5311 0x00000008
2077 #define AR5K_PHY_SCAL_32MHZ_2417 0x0000000a
2078 #define AR5K_PHY_SCAL_32MHZ_HB63 0x00000032
2083 #define AR5K_PHY_PLL 0x987c
2084 #define AR5K_PHY_PLL_20MHZ 0x00000013
2086 #define AR5K_PHY_PLL_40MHZ_5211 0x00000018
2087 #define AR5K_PHY_PLL_40MHZ_5212 0x000000aa
2088 #define AR5K_PHY_PLL_40MHZ_5413 0x00000004
2089 #define AR5K_PHY_PLL_40MHZ (ah->ah_version == AR5K_AR5211 ? \
2090 AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212)
2092 #define AR5K_PHY_PLL_44MHZ_5211 0x00000019
2093 #define AR5K_PHY_PLL_44MHZ_5212 0x000000ab
2094 #define AR5K_PHY_PLL_44MHZ (ah->ah_version == AR5K_AR5211 ? \
2095 AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212)
2097 #define AR5K_PHY_PLL_RF5111 0x00000000
2098 #define AR5K_PHY_PLL_RF5112 0x00000040
2099 #define AR5K_PHY_PLL_HALF_RATE 0x00000100
2100 #define AR5K_PHY_PLL_QUARTER_RATE 0x00000200
2111 #define AR5K_RF_BUFFER 0x989c
2112 #define AR5K_RF_BUFFER_CONTROL_0 0x98c0
2113 #define AR5K_RF_BUFFER_CONTROL_1 0x98c4
2114 #define AR5K_RF_BUFFER_CONTROL_2 0x98cc
2116 #define AR5K_RF_BUFFER_CONTROL_3 0x98d0
2120 #define AR5K_RF_BUFFER_CONTROL_4 0x98d4
2125 #define AR5K_RF_BUFFER_CONTROL_5 0x98d8
2130 #define AR5K_RF_BUFFER_CONTROL_6 0x98dc
2135 #define AR5K_PHY_RFSTG 0x98d4
2136 #define AR5K_PHY_RFSTG_DISABLE 0x00000021
2141 #define AR5K_PHY_BIN_MASK_1 0x9900
2142 #define AR5K_PHY_BIN_MASK_2 0x9904
2143 #define AR5K_PHY_BIN_MASK_3 0x9908
2145 #define AR5K_PHY_BIN_MASK_CTL 0x990c
2146 #define AR5K_PHY_BIN_MASK_CTL_MASK_4 0x00003fff
2147 #define AR5K_PHY_BIN_MASK_CTL_MASK_4_S 0
2148 #define AR5K_PHY_BIN_MASK_CTL_RATE 0xff000000
2149 #define AR5K_PHY_BIN_MASK_CTL_RATE_S 24
2154 #define AR5K_PHY_ANT_CTL 0x9910
2155 #define AR5K_PHY_ANT_CTL_TXRX_EN 0x00000001
2156 #define AR5K_PHY_ANT_CTL_SECTORED_ANT 0x00000004
2157 #define AR5K_PHY_ANT_CTL_HITUNE5 0x00000008
2158 #define AR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x000003f0
2159 #define AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S 4
2164 #define AR5K_PHY_RX_DELAY 0x9914
2165 #define AR5K_PHY_RX_DELAY_M 0x00003fff
2170 #define AR5K_PHY_MAX_RX_LEN 0x991c
2176 #define AR5K_PHY_IQ 0x9920
2177 #define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f
2178 #define AR5K_PHY_IQ_CORR_Q_Q_COFF_S 0
2179 #define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0
2180 #define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5
2181 #define AR5K_PHY_IQ_CORR_ENABLE 0x00000800
2182 #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000
2183 #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12
2184 #define AR5K_PHY_IQ_RUN 0x00010000
2185 #define AR5K_PHY_IQ_USE_PT_DF 0x00020000
2186 #define AR5K_PHY_IQ_EARLY_TRIG_THR 0x00200000
2187 #define AR5K_PHY_IQ_PILOT_MASK_EN 0x10000000
2188 #define AR5K_PHY_IQ_CHAN_MASK_EN 0x20000000
2189 #define AR5K_PHY_IQ_SPUR_FILT_EN 0x40000000
2190 #define AR5K_PHY_IQ_SPUR_RSSI_EN 0x80000000
2197 #define AR5K_PHY_OFDM_SELFCORR 0x9924
2198 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001
2199 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe
2200 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S 1
2201 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100
2202 #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000
2203 #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000
2204 #define AR5K_PHY_OFDM_SELFCORR_LSCTHR_HIRSSI 0x00800000
2209 #define AR5K_PHY_WARM_RESET 0x9928
2214 #define AR5K_PHY_CTL 0x992c
2215 #define AR5K_PHY_CTL_RX_DRAIN_RATE 0x00000001
2216 #define AR5K_PHY_CTL_LATE_TX_SIG_SYM 0x00000002
2217 #define AR5K_PHY_CTL_GEN_SCRAMBLER 0x00000004
2218 #define AR5K_PHY_CTL_TX_ANT_SEL 0x00000008
2219 #define AR5K_PHY_CTL_TX_ANT_STATIC 0x00000010
2220 #define AR5K_PHY_CTL_RX_ANT_SEL 0x00000020
2221 #define AR5K_PHY_CTL_RX_ANT_STATIC 0x00000040
2222 #define AR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080
2227 #define AR5K_PHY_PAPD_PROBE 0x9930
2228 #define AR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001
2229 #define AR5K_PHY_PAPD_PROBE_PCDAC_BIAS 0x00000002
2230 #define AR5K_PHY_PAPD_PROBE_COMP_GAIN 0x00000040
2231 #define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00
2232 #define AR5K_PHY_PAPD_PROBE_TXPOWER_S 9
2233 #define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000
2234 #define AR5K_PHY_PAPD_PROBE_PREDIST_EN 0x00010000
2235 #define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000
2236 #define AR5K_PHY_PAPD_PROBE_TYPE_S 23
2237 #define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 0
2238 #define AR5K_PHY_PAPD_PROBE_TYPE_XR 1
2239 #define AR5K_PHY_PAPD_PROBE_TYPE_CCK 2
2240 #define AR5K_PHY_PAPD_PROBE_GAINF 0xfe000000
2241 #define AR5K_PHY_PAPD_PROBE_GAINF_S 25
2242 #define AR5K_PHY_PAPD_PROBE_INI_5111 0x00004883
2243 #define AR5K_PHY_PAPD_PROBE_INI_5112 0x00004882
2248 #define AR5K_PHY_TXPOWER_RATE1 0x9934
2249 #define AR5K_PHY_TXPOWER_RATE2 0x9938
2250 #define AR5K_PHY_TXPOWER_RATE_MAX 0x993c
2251 #define AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE 0x00000040
2252 #define AR5K_PHY_TXPOWER_RATE3 0xa234
2253 #define AR5K_PHY_TXPOWER_RATE4 0xa238
2258 #define AR5K_PHY_FRAME_CTL_5210 0x9804
2259 #define AR5K_PHY_FRAME_CTL_5211 0x9944
2260 #define AR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \
2261 AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211)
2263 #define AR5K_PHY_FRAME_CTL_WIN_LEN 0x00000003
2264 #define AR5K_PHY_FRAME_CTL_WIN_LEN_S 0
2265 #define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038
2266 #define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3
2267 #define AR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000
2268 #define AR5K_PHY_FRAME_CTL_EMU 0x80000000
2269 #define AR5K_PHY_FRAME_CTL_EMU_S 31
2271 #define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000
2272 #define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000
2273 #define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000
2274 #define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000
2275 #define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000
2276 #define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000
2277 #define AR5K_PHY_FRAME_CTL_INI \
2278 (AR5K_PHY_FRAME_CTL_SERVICE_ERR | \
2279 AR5K_PHY_FRAME_CTL_TXURN_ERR | \
2280 AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \
2281 AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \
2282 AR5K_PHY_FRAME_CTL_PARITY_ERR | \
2283 AR5K_PHY_FRAME_CTL_TIMING_ERR)
2288 #define AR5K_PHY_TX_PWR_ADJ 0x994c
2289 #define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA 0x00000fc0
2290 #define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA_S 6
2291 #define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX 0x00fc0000
2292 #define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX_S 18
2297 #define AR5K_PHY_RADAR 0x9954
2298 #define AR5K_PHY_RADAR_ENABLE 0x00000001
2299 #define AR5K_PHY_RADAR_DISABLE 0x00000000
2300 #define AR5K_PHY_RADAR_INBANDTHR 0x0000003e
2303 #define AR5K_PHY_RADAR_INBANDTHR_S 1
2305 #define AR5K_PHY_RADAR_PRSSI_THR 0x00000fc0
2308 #define AR5K_PHY_RADAR_PRSSI_THR_S 6
2310 #define AR5K_PHY_RADAR_PHEIGHT_THR 0x0003f000
2313 #define AR5K_PHY_RADAR_PHEIGHT_THR_S 12
2315 #define AR5K_PHY_RADAR_RSSI_THR 0x00fc0000
2318 #define AR5K_PHY_RADAR_RSSI_THR_S 18
2320 #define AR5K_PHY_RADAR_FIRPWR_THR 0x7f000000
2324 #define AR5K_PHY_RADAR_FIRPWR_THRS 24
2329 #define AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960
2330 #define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964
2335 #define AR5K_PHY_NFTHRES 0x9968
2340 #define AR5K_PHY_SIGMA_DELTA 0x996C
2341 #define AR5K_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
2342 #define AR5K_PHY_SIGMA_DELTA_ADC_SEL_S 0
2343 #define AR5K_PHY_SIGMA_DELTA_FILT2 0x000000f8
2344 #define AR5K_PHY_SIGMA_DELTA_FILT2_S 3
2345 #define AR5K_PHY_SIGMA_DELTA_FILT1 0x00001f00
2346 #define AR5K_PHY_SIGMA_DELTA_FILT1_S 8
2347 #define AR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000
2348 #define AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S 13
2353 #define AR5K_PHY_RESTART 0x9970
2354 #define AR5K_PHY_RESTART_DIV_GC 0x001c0000
2355 #define AR5K_PHY_RESTART_DIV_GC_S 18
2360 #define AR5K_PHY_RFBUS_REQ 0x997C
2361 #define AR5K_PHY_RFBUS_REQ_REQUEST 0x00000001
2366 #define AR5K_PHY_TIMING_7 0x9980
2367 #define AR5K_PHY_TIMING_8 0x9984
2368 #define AR5K_PHY_TIMING_8_PILOT_MASK_2 0x000fffff
2369 #define AR5K_PHY_TIMING_8_PILOT_MASK_2_S 0
2371 #define AR5K_PHY_BIN_MASK2_1 0x9988
2372 #define AR5K_PHY_BIN_MASK2_2 0x998c
2373 #define AR5K_PHY_BIN_MASK2_3 0x9990
2375 #define AR5K_PHY_BIN_MASK2_4 0x9994
2376 #define AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff
2377 #define AR5K_PHY_BIN_MASK2_4_MASK_4_S 0
2379 #define AR5K_PHY_TIMING_9 0x9998
2380 #define AR5K_PHY_TIMING_10 0x999c
2381 #define AR5K_PHY_TIMING_10_PILOT_MASK_2 0x000fffff
2382 #define AR5K_PHY_TIMING_10_PILOT_MASK_2_S 0
2387 #define AR5K_PHY_TIMING_11 0x99a0
2388 #define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff
2389 #define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE_S 0
2390 #define AR5K_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000
2391 #define AR5K_PHY_TIMING_11_SPUR_FREQ_SD_S 20
2392 #define AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000
2393 #define AR5K_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000
2398 #define AR5K_BB_GAIN_BASE 0x9b00
2399 #define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2))
2400 #define AR5K_RF_GAIN_BASE 0x9a00
2401 #define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2))
2406 #define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10
2407 #define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14
2408 #define AR5K_PHY_IQRES_CAL_CORR 0x9c18
2413 #define AR5K_PHY_CURRENT_RSSI 0x9c1c
2418 #define AR5K_PHY_RFBUS_GRANT 0x9c20
2419 #define AR5K_PHY_RFBUS_GRANT_OK 0x00000001
2424 #define AR5K_PHY_ADC_TEST 0x9c24
2425 #define AR5K_PHY_ADC_TEST_I 0x00000001
2426 #define AR5K_PHY_ADC_TEST_Q 0x00000200
2431 #define AR5K_PHY_DAC_TEST 0x9c28
2432 #define AR5K_PHY_DAC_TEST_I 0x00000001
2433 #define AR5K_PHY_DAC_TEST_Q 0x00000200
2438 #define AR5K_PHY_PTAT 0x9c2c
2443 #define AR5K_PHY_BAD_TX_RATE 0x9c30
2448 #define AR5K_PHY_SPUR_PWR 0x9c34
2449 #define AR5K_PHY_SPUR_PWR_I 0x00000001
2450 #define AR5K_PHY_SPUR_PWR_Q 0x00000100
2451 #define AR5K_PHY_SPUR_PWR_FILT 0x00010000
2456 #define AR5K_PHY_CHAN_STATUS 0x9c38
2457 #define AR5K_PHY_CHAN_STATUS_BT_ACT 0x00000001
2458 #define AR5K_PHY_CHAN_STATUS_RX_CLR_RAW 0x00000002
2459 #define AR5K_PHY_CHAN_STATUS_RX_CLR_MAC 0x00000004
2460 #define AR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x00000008
2465 #define AR5K_PHY_HEAVY_CLIP_ENABLE 0x99e0
2470 #define AR5K_PHY_SCLOCK 0x99f0
2471 #define AR5K_PHY_SCLOCK_32MHZ 0x0000000c
2472 #define AR5K_PHY_SDELAY 0x99f4
2473 #define AR5K_PHY_SDELAY_32MHZ 0x000000ff
2474 #define AR5K_PHY_SPENDING 0x99f8
2481 #define AR5K_PHY_PAPD_I_BASE 0xa000
2482 #define AR5K_PHY_PAPD_I(_n) (AR5K_PHY_PAPD_I_BASE + ((_n) << 2))
2487 #define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180
2488 #define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2))
2493 #define AR5K_PHY_MODE 0x0a200
2494 #define AR5K_PHY_MODE_MOD 0x00000001
2495 #define AR5K_PHY_MODE_MOD_OFDM 0
2496 #define AR5K_PHY_MODE_MOD_CCK 1
2497 #define AR5K_PHY_MODE_FREQ 0x00000002
2498 #define AR5K_PHY_MODE_FREQ_5GHZ 0
2499 #define AR5K_PHY_MODE_FREQ_2GHZ 2
2500 #define AR5K_PHY_MODE_MOD_DYN 0x00000004
2501 #define AR5K_PHY_MODE_RAD 0x00000008
2502 #define AR5K_PHY_MODE_RAD_RF5111 0
2503 #define AR5K_PHY_MODE_RAD_RF5112 8
2504 #define AR5K_PHY_MODE_XR 0x00000010
2505 #define AR5K_PHY_MODE_HALF_RATE 0x00000020
2506 #define AR5K_PHY_MODE_QUARTER_RATE 0x00000040
2511 #define AR5K_PHY_CCKTXCTL 0xa204
2512 #define AR5K_PHY_CCKTXCTL_WORLD 0x00000000
2513 #define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010
2514 #define AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS 0x00000001
2515 #define AR5K_PHY_CCKTXCTK_DAC_SCALE 0x00000004
2520 #define AR5K_PHY_CCK_CROSSCORR 0xa208
2521 #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR 0x0000003f
2522 #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S 0
2525 #define AR5K_PHY_FAST_ANT_DIV 0xa208
2526 #define AR5K_PHY_FAST_ANT_DIV_EN 0x00002000
2531 #define AR5K_PHY_GAIN_2GHZ 0xa20c
2532 #define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000
2533 #define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18
2534 #define AR5K_PHY_GAIN_2GHZ_INI_5111 0x6480416c
2536 #define AR5K_PHY_CCK_RX_CTL_4 0xa21c
2537 #define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT 0x01f80000
2538 #define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT_S 19
2540 #define AR5K_PHY_DAG_CCK_CTL 0xa228
2541 #define AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR 0x00000200
2542 #define AR5K_PHY_DAG_CCK_CTL_RSSI_THR 0x0001fc00
2543 #define AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S 10
2545 #define AR5K_PHY_FAST_ADC 0xa24c
2547 #define AR5K_PHY_BLUETOOTH 0xa254
2553 #define AR5K_PHY_TPC_RG1 0xa258
2554 #define AR5K_PHY_TPC_RG1_NUM_PD_GAIN 0x0000c000
2555 #define AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S 14
2556 #define AR5K_PHY_TPC_RG1_PDGAIN_1 0x00030000
2557 #define AR5K_PHY_TPC_RG1_PDGAIN_1_S 16
2558 #define AR5K_PHY_TPC_RG1_PDGAIN_2 0x000c0000
2559 #define AR5K_PHY_TPC_RG1_PDGAIN_2_S 18
2560 #define AR5K_PHY_TPC_RG1_PDGAIN_3 0x00300000
2561 #define AR5K_PHY_TPC_RG1_PDGAIN_3_S 20
2563 #define AR5K_PHY_TPC_RG5 0xa26C
2564 #define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP 0x0000000F
2565 #define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP_S 0
2566 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1 0x000003F0
2567 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1_S 4
2568 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2 0x0000FC00
2569 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2_S 10
2570 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3 0x003F0000
2571 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S 16
2572 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC00000
2573 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S 22
2578 #define AR5K_PHY_PDADC_TXPOWER_BASE 0xa280
2579 #define AR5K_PHY_PDADC_TXPOWER(_n) (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2))
2584 #define AR5K_AR5312_RESET 0xbc003020
2585 #define AR5K_AR5312_RESET_BB0_COLD 0x00000004
2586 #define AR5K_AR5312_RESET_BB1_COLD 0x00000200
2587 #define AR5K_AR5312_RESET_WMAC0 0x00002000
2588 #define AR5K_AR5312_RESET_BB0_WARM 0x00004000
2589 #define AR5K_AR5312_RESET_WMAC1 0x00020000
2590 #define AR5K_AR5312_RESET_BB1_WARM 0x00040000
2592 #define AR5K_AR5312_ENABLE 0xbc003080
2593 #define AR5K_AR5312_ENABLE_WLAN0 0x00000001
2594 #define AR5K_AR5312_ENABLE_WLAN1 0x00000008
2596 #define AR5K_AR2315_RESET 0xb1000004
2597 #define AR5K_AR2315_RESET_WMAC 0x00000001
2598 #define AR5K_AR2315_RESET_BB_WARM 0x00000002
2600 #define AR5K_AR2315_AHB_ARB_CTL 0xb1000008
2601 #define AR5K_AR2315_AHB_ARB_CTL_WLAN 0x00000002
2603 #define AR5K_AR2315_BYTESWAP 0xb100000c
2604 #define AR5K_AR2315_BYTESWAP_WMAC 0x00000002