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common.h
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1 /*
2  * Renesas USB driver
3  *
4  * Copyright (C) 2011 Renesas Solutions Corp.
5  * Kuninori Morimoto <[email protected]>
6  *
7  * This program is distributed in the hope that it will be useful,
8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10  * GNU General Public License for more details.
11  *
12  * You should have received a copy of the GNU General Public License
13  * along with this program; if not, write to the Free Software
14  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
15  *
16  */
17 #ifndef RENESAS_USB_DRIVER_H
18 #define RENESAS_USB_DRIVER_H
19 
20 #include <linux/platform_device.h>
22 
23 struct usbhs_priv;
24 
25 #include "mod.h"
26 #include "pipe.h"
27 
28 /*
29  *
30  * register define
31  *
32  */
33 #define SYSCFG 0x0000
34 #define BUSWAIT 0x0002
35 #define DVSTCTR 0x0008
36 #define TESTMODE 0x000C
37 #define CFIFO 0x0014
38 #define CFIFOSEL 0x0020
39 #define CFIFOCTR 0x0022
40 #define D0FIFO 0x0100
41 #define D0FIFOSEL 0x0028
42 #define D0FIFOCTR 0x002A
43 #define D1FIFO 0x0120
44 #define D1FIFOSEL 0x002C
45 #define D1FIFOCTR 0x002E
46 #define INTENB0 0x0030
47 #define INTENB1 0x0032
48 #define BRDYENB 0x0036
49 #define NRDYENB 0x0038
50 #define BEMPENB 0x003A
51 #define INTSTS0 0x0040
52 #define INTSTS1 0x0042
53 #define BRDYSTS 0x0046
54 #define NRDYSTS 0x0048
55 #define BEMPSTS 0x004A
56 #define FRMNUM 0x004C
57 #define USBREQ 0x0054 /* USB request type register */
58 #define USBVAL 0x0056 /* USB request value register */
59 #define USBINDX 0x0058 /* USB request index register */
60 #define USBLENG 0x005A /* USB request length register */
61 #define DCPCFG 0x005C
62 #define DCPMAXP 0x005E
63 #define DCPCTR 0x0060
64 #define PIPESEL 0x0064
65 #define PIPECFG 0x0068
66 #define PIPEBUF 0x006A
67 #define PIPEMAXP 0x006C
68 #define PIPEPERI 0x006E
69 #define PIPEnCTR 0x0070
70 #define PIPE1TRE 0x0090
71 #define PIPE1TRN 0x0092
72 #define PIPE2TRE 0x0094
73 #define PIPE2TRN 0x0096
74 #define PIPE3TRE 0x0098
75 #define PIPE3TRN 0x009A
76 #define PIPE4TRE 0x009C
77 #define PIPE4TRN 0x009E
78 #define PIPE5TRE 0x00A0
79 #define PIPE5TRN 0x00A2
80 #define PIPEBTRE 0x00A4
81 #define PIPEBTRN 0x00A6
82 #define PIPECTRE 0x00A8
83 #define PIPECTRN 0x00AA
84 #define PIPEDTRE 0x00AC
85 #define PIPEDTRN 0x00AE
86 #define PIPEETRE 0x00B0
87 #define PIPEETRN 0x00B2
88 #define PIPEFTRE 0x00B4
89 #define PIPEFTRN 0x00B6
90 #define PIPE9TRE 0x00B8
91 #define PIPE9TRN 0x00BA
92 #define PIPEATRE 0x00BC
93 #define PIPEATRN 0x00BE
94 #define DEVADD0 0x00D0 /* Device address n configuration */
95 #define DEVADD1 0x00D2
96 #define DEVADD2 0x00D4
97 #define DEVADD3 0x00D6
98 #define DEVADD4 0x00D8
99 #define DEVADD5 0x00DA
100 #define DEVADD6 0x00DC
101 #define DEVADD7 0x00DE
102 #define DEVADD8 0x00E0
103 #define DEVADD9 0x00E2
104 #define DEVADDA 0x00E4
105 
106 /* SYSCFG */
107 #define SCKE (1 << 10) /* USB Module Clock Enable */
108 #define HSE (1 << 7) /* High-Speed Operation Enable */
109 #define DCFM (1 << 6) /* Controller Function Select */
110 #define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */
111 #define DPRPU (1 << 4) /* D+ Line Resistance Control */
112 #define USBE (1 << 0) /* USB Module Operation Enable */
113 
114 /* DVSTCTR */
115 #define EXTLP (1 << 10) /* Controls the EXTLP pin output state */
116 #define PWEN (1 << 9) /* Controls the PWEN pin output state */
117 #define USBRST (1 << 6) /* Bus Reset Output */
118 #define UACT (1 << 4) /* USB Bus Enable */
119 #define RHST (0x7) /* Reset Handshake */
120 #define RHST_LOW_SPEED 1 /* Low-speed connection */
121 #define RHST_FULL_SPEED 2 /* Full-speed connection */
122 #define RHST_HIGH_SPEED 3 /* High-speed connection */
123 
124 /* CFIFOSEL */
125 #define DREQE (1 << 12) /* DMA Transfer Request Enable */
126 #define MBW_32 (0x2 << 10) /* CFIFO Port Access Bit Width */
127 
128 /* CFIFOCTR */
129 #define BVAL (1 << 15) /* Buffer Memory Enable Flag */
130 #define BCLR (1 << 14) /* CPU buffer clear */
131 #define FRDY (1 << 13) /* FIFO Port Ready */
132 #define DTLN_MASK (0x0FFF) /* Receive Data Length */
133 
134 /* INTENB0 */
135 #define VBSE (1 << 15) /* Enable IRQ VBUS_0 and VBUSIN_0 */
136 #define RSME (1 << 14) /* Enable IRQ Resume */
137 #define SOFE (1 << 13) /* Enable IRQ Frame Number Update */
138 #define DVSE (1 << 12) /* Enable IRQ Device State Transition */
139 #define CTRE (1 << 11) /* Enable IRQ Control Stage Transition */
140 #define BEMPE (1 << 10) /* Enable IRQ Buffer Empty */
141 #define NRDYE (1 << 9) /* Enable IRQ Buffer Not Ready Response */
142 #define BRDYE (1 << 8) /* Enable IRQ Buffer Ready */
143 
144 /* INTENB1 */
145 #define BCHGE (1 << 14) /* USB Bus Change Interrupt Enable */
146 #define DTCHE (1 << 12) /* Disconnection Detect Interrupt Enable */
147 #define ATTCHE (1 << 11) /* Connection Detect Interrupt Enable */
148 #define EOFERRE (1 << 6) /* EOF Error Detect Interrupt Enable */
149 #define SIGNE (1 << 5) /* Setup Transaction Error Interrupt Enable */
150 #define SACKE (1 << 4) /* Setup Transaction ACK Interrupt Enable */
151 
152 /* INTSTS0 */
153 #define VBINT (1 << 15) /* VBUS0_0 and VBUS1_0 Interrupt Status */
154 #define DVST (1 << 12) /* Device State Transition Interrupt Status */
155 #define CTRT (1 << 11) /* Control Stage Interrupt Status */
156 #define BEMP (1 << 10) /* Buffer Empty Interrupt Status */
157 #define BRDY (1 << 8) /* Buffer Ready Interrupt Status */
158 #define VBSTS (1 << 7) /* VBUS_0 and VBUSIN_0 Input Status */
159 #define VALID (1 << 3) /* USB Request Receive */
160 
161 #define DVSQ_MASK (0x3 << 4) /* Device State */
162 #define POWER_STATE (0 << 4)
163 #define DEFAULT_STATE (1 << 4)
164 #define ADDRESS_STATE (2 << 4)
165 #define CONFIGURATION_STATE (3 << 4)
166 
167 #define CTSQ_MASK (0x7) /* Control Transfer Stage */
168 #define IDLE_SETUP_STAGE 0 /* Idle stage or setup stage */
169 #define READ_DATA_STAGE 1 /* Control read data stage */
170 #define READ_STATUS_STAGE 2 /* Control read status stage */
171 #define WRITE_DATA_STAGE 3 /* Control write data stage */
172 #define WRITE_STATUS_STAGE 4 /* Control write status stage */
173 #define NODATA_STATUS_STAGE 5 /* Control write NoData status stage */
174 #define SEQUENCE_ERROR 6 /* Control transfer sequence error */
175 
176 /* INTSTS1 */
177 #define OVRCR (1 << 15) /* OVRCR Interrupt Status */
178 #define BCHG (1 << 14) /* USB Bus Change Interrupt Status */
179 #define DTCH (1 << 12) /* USB Disconnection Detect Interrupt Status */
180 #define ATTCH (1 << 11) /* ATTCH Interrupt Status */
181 #define EOFERR (1 << 6) /* EOF Error Detect Interrupt Status */
182 #define SIGN (1 << 5) /* Setup Transaction Error Interrupt Status */
183 #define SACK (1 << 4) /* Setup Transaction ACK Response Interrupt Status */
184 
185 /* PIPECFG */
186 /* DCPCFG */
187 #define TYPE_NONE (0 << 14) /* Transfer Type */
188 #define TYPE_BULK (1 << 14)
189 #define TYPE_INT (2 << 14)
190 #define TYPE_ISO (3 << 14)
191 #define DBLB (1 << 9) /* Double Buffer Mode */
192 #define SHTNAK (1 << 7) /* Pipe Disable in Transfer End */
193 #define DIR_OUT (1 << 4) /* Transfer Direction */
194 
195 /* PIPEMAXP */
196 /* DCPMAXP */
197 #define DEVSEL_MASK (0xF << 12) /* Device Select */
198 #define DCP_MAXP_MASK (0x7F)
199 #define PIPE_MAXP_MASK (0x7FF)
200 
201 /* PIPEBUF */
202 #define BUFSIZE_SHIFT 10
203 #define BUFSIZE_MASK (0x1F << BUFSIZE_SHIFT)
204 #define BUFNMB_MASK (0xFF)
205 
206 /* PIPEnCTR */
207 /* DCPCTR */
208 #define BSTS (1 << 15) /* Buffer Status */
209 #define SUREQ (1 << 14) /* Sending SETUP Token */
210 #define CSSTS (1 << 12) /* CSSTS Status */
211 #define ACLRM (1 << 9) /* Buffer Auto-Clear Mode */
212 #define SQCLR (1 << 8) /* Toggle Bit Clear */
213 #define SQSET (1 << 7) /* Toggle Bit Set */
214 #define PBUSY (1 << 5) /* Pipe Busy */
215 #define PID_MASK (0x3) /* Response PID */
216 #define PID_NAK 0
217 #define PID_BUF 1
218 #define PID_STALL10 2
219 #define PID_STALL11 3
220 
221 #define CCPL (1 << 2) /* Control Transfer End Enable */
222 
223 /* PIPEnTRE */
224 #define TRENB (1 << 9) /* Transaction Counter Enable */
225 #define TRCLR (1 << 8) /* Transaction Counter Clear */
226 
227 /* FRMNUM */
228 #define FRNM_MASK (0x7FF)
229 
230 /* DEVADDn */
231 #define UPPHUB(x) (((x) & 0xF) << 11) /* HUB Register */
232 #define HUBPORT(x) (((x) & 0x7) << 8) /* HUB Port for Target Device */
233 #define USBSPD(x) (((x) & 0x3) << 6) /* Device Transfer Rate */
234 #define USBSPD_SPEED_LOW 0x1
235 #define USBSPD_SPEED_FULL 0x2
236 #define USBSPD_SPEED_HIGH 0x3
237 
238 /*
239  * struct
240  */
241 struct usbhs_priv {
242 
243  void __iomem *base;
244  unsigned int irq;
245  unsigned long irqflags;
246 
249 
252 
254 
256 
257  /*
258  * module control
259  */
261 
262  /*
263  * pipe control
264  */
266 
267  /*
268  * fifo control
269  */
271 };
272 
273 /*
274  * common
275  */
276 u16 usbhs_read(struct usbhs_priv *priv, u32 reg);
277 void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data);
278 void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data);
279 
280 #define usbhs_lock(p, f) spin_lock_irqsave(usbhs_priv_to_lock(p), f)
281 #define usbhs_unlock(p, f) spin_unlock_irqrestore(usbhs_priv_to_lock(p), f)
282 
283 /*
284  * sysconfig
285  */
286 void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable);
287 void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable);
289 
290 /*
291  * usb request
292  */
295 
296 /*
297  * bus
298  */
300 void usbhs_bus_send_reset(struct usbhs_priv *priv);
301 int usbhs_bus_get_speed(struct usbhs_priv *priv);
302 int usbhs_vbus_ctrl(struct usbhs_priv *priv, int enable);
303 
304 /*
305  * frame
306  */
307 int usbhs_frame_get_num(struct usbhs_priv *priv);
308 
309 /*
310  * device config
311  */
312 int usbhs_set_device_config(struct usbhs_priv *priv, int devnum, u16 upphub,
313  u16 hubport, u16 speed);
314 
315 /*
316  * data
317  */
319 #define usbhs_get_dparam(priv, param) (priv->dparam.param)
320 #define usbhs_priv_to_pdev(priv) (priv->pdev)
321 #define usbhs_priv_to_dev(priv) (&priv->pdev->dev)
322 #define usbhs_priv_to_lock(priv) (&priv->lock)
323 
324 #endif /* RENESAS_USB_DRIVER_H */