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exception-64e.h
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1 /*
2  * Definitions for use by exception code on Book3-E
3  *
4  * Copyright (C) 2008 Ben. Herrenschmidt ([email protected]), IBM Corp.
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * as published by the Free Software Foundation; either version
9  * 2 of the License, or (at your option) any later version.
10  */
11 #ifndef _ASM_POWERPC_EXCEPTION_64E_H
12 #define _ASM_POWERPC_EXCEPTION_64E_H
13 
14 /*
15  * SPRGs usage an other considerations...
16  *
17  * Since TLB miss and other standard exceptions can be interrupted by
18  * critical exceptions which can themselves be interrupted by machine
19  * checks, and since the two later can themselves cause a TLB miss when
20  * hitting the linear mapping for the kernel stacks, we need to be a bit
21  * creative on how we use SPRGs.
22  *
23  * The base idea is that we have one SRPG reserved for critical and one
24  * for machine check interrupts. Those are used to save a GPR that can
25  * then be used to get the PACA, and store as much context as we need
26  * to save in there. That includes saving the SPRGs used by the TLB miss
27  * handler for linear mapping misses and the associated SRR0/1 due to
28  * the above re-entrancy issue.
29  *
30  * So here's the current usage pattern. It's done regardless of which
31  * SPRGs are user-readable though, thus we might have to change some of
32  * this later. In order to do that more easily, we use special constants
33  * for naming them
34  *
35  * WARNING: Some of these SPRGs are user readable. We need to do something
36  * about it as some point by making sure they can't be used to leak kernel
37  * critical data
38  */
39 
40 #define PACA_EXGDBELL PACA_EXGEN
41 
42 /* We are out of SPRGs so we save some things in the PACA. The normal
43  * exception frame is smaller than the CRIT or MC one though
44  */
45 #define EX_R1 (0 * 8)
46 #define EX_CR (1 * 8)
47 #define EX_R10 (2 * 8)
48 #define EX_R11 (3 * 8)
49 #define EX_R13 (4 * 8)
50 #define EX_R14 (5 * 8)
51 #define EX_R15 (6 * 8)
52 
53 /*
54  * The TLB miss exception uses different slots.
55  *
56  * The bolted variant uses only the first six fields,
57  * which in combination with pgd and kernel_pgd fits in
58  * one 64-byte cache line.
59  */
60 
61 #define EX_TLB_R10 ( 0 * 8)
62 #define EX_TLB_R11 ( 1 * 8)
63 #define EX_TLB_R14 ( 2 * 8)
64 #define EX_TLB_R15 ( 3 * 8)
65 #define EX_TLB_R16 ( 4 * 8)
66 #define EX_TLB_CR ( 5 * 8)
67 #define EX_TLB_R12 ( 6 * 8)
68 #define EX_TLB_R13 ( 7 * 8)
69 #define EX_TLB_DEAR ( 8 * 8) /* Level 0 and 2 only */
70 #define EX_TLB_ESR ( 9 * 8) /* Level 0 and 2 only */
71 #define EX_TLB_SRR0 (10 * 8)
72 #define EX_TLB_SRR1 (11 * 8)
73 #ifdef CONFIG_BOOK3E_MMU_TLB_STATS
74 #define EX_TLB_R8 (12 * 8)
75 #define EX_TLB_R9 (13 * 8)
76 #define EX_TLB_LR (14 * 8)
77 #define EX_TLB_SIZE (15 * 8)
78 #else
79 #define EX_TLB_SIZE (12 * 8)
80 #endif
81 
82 #define START_EXCEPTION(label) \
83  .globl exc_##label##_book3e; \
84 exc_##label##_book3e:
85 
86 /* TLB miss exception prolog
87  *
88  * This prolog handles re-entrancy (up to 3 levels supported in the PACA
89  * though we currently don't test for overflow). It provides you with a
90  * re-entrancy safe working space of r10...r16 and CR with r12 being used
91  * as the exception area pointer in the PACA for that level of re-entrancy
92  * and r13 containing the PACA pointer.
93  *
94  * SRR0 and SRR1 are saved, but DEAR and ESR are not, since they don't apply
95  * as-is for instruction exceptions. It's up to the actual exception code
96  * to save them as well if required.
97  */
98 #define TLB_MISS_PROLOG \
99  mtspr SPRN_SPRG_TLB_SCRATCH,r12; \
100  mfspr r12,SPRN_SPRG_TLB_EXFRAME; \
101  std r10,EX_TLB_R10(r12); \
102  mfcr r10; \
103  std r11,EX_TLB_R11(r12); \
104  mfspr r11,SPRN_SPRG_TLB_SCRATCH; \
105  std r13,EX_TLB_R13(r12); \
106  mfspr r13,SPRN_SPRG_PACA; \
107  std r14,EX_TLB_R14(r12); \
108  addi r14,r12,EX_TLB_SIZE; \
109  std r15,EX_TLB_R15(r12); \
110  mfspr r15,SPRN_SRR1; \
111  std r16,EX_TLB_R16(r12); \
112  mfspr r16,SPRN_SRR0; \
113  std r10,EX_TLB_CR(r12); \
114  std r11,EX_TLB_R12(r12); \
115  mtspr SPRN_SPRG_TLB_EXFRAME,r14; \
116  std r15,EX_TLB_SRR1(r12); \
117  std r16,EX_TLB_SRR0(r12); \
118  TLB_MISS_PROLOG_STATS
119 
120 /* And these are the matching epilogs that restores things
121  *
122  * There are 3 epilogs:
123  *
124  * - SUCCESS : Unwinds one level
125  * - ERROR : restore from level 0 and reset
126  * - ERROR_SPECIAL : restore from current level and reset
127  *
128  * Normal errors use ERROR, that is, they restore the initial fault context
129  * and trigger a fault. However, there is a special case for linear mapping
130  * errors. Those should basically never happen, but if they do happen, we
131  * want the error to point out the context that did that linear mapping
132  * fault, not the initial level 0 (basically, we got a bogus PGF or something
133  * like that). For userland errors on the linear mapping, there is no
134  * difference since those are always level 0 anyway
135  */
136 
137 #define TLB_MISS_RESTORE(freg) \
138  ld r14,EX_TLB_CR(r12); \
139  ld r10,EX_TLB_R10(r12); \
140  ld r15,EX_TLB_SRR0(r12); \
141  ld r16,EX_TLB_SRR1(r12); \
142  mtspr SPRN_SPRG_TLB_EXFRAME,freg; \
143  ld r11,EX_TLB_R11(r12); \
144  mtcr r14; \
145  ld r13,EX_TLB_R13(r12); \
146  ld r14,EX_TLB_R14(r12); \
147  mtspr SPRN_SRR0,r15; \
148  ld r15,EX_TLB_R15(r12); \
149  mtspr SPRN_SRR1,r16; \
150  TLB_MISS_RESTORE_STATS \
151  ld r16,EX_TLB_R16(r12); \
152  ld r12,EX_TLB_R12(r12); \
153 
154 #define TLB_MISS_EPILOG_SUCCESS \
155  TLB_MISS_RESTORE(r12)
156 
157 #define TLB_MISS_EPILOG_ERROR \
158  addi r12,r13,PACA_EXTLB; \
159  TLB_MISS_RESTORE(r12)
160 
161 #define TLB_MISS_EPILOG_ERROR_SPECIAL \
162  addi r11,r13,PACA_EXTLB; \
163  TLB_MISS_RESTORE(r11)
164 
165 #ifdef CONFIG_BOOK3E_MMU_TLB_STATS
166 #define TLB_MISS_PROLOG_STATS \
167  mflr r10; \
168  std r8,EX_TLB_R8(r12); \
169  std r9,EX_TLB_R9(r12); \
170  std r10,EX_TLB_LR(r12);
171 #define TLB_MISS_RESTORE_STATS \
172  ld r16,EX_TLB_LR(r12); \
173  ld r9,EX_TLB_R9(r12); \
174  ld r8,EX_TLB_R8(r12); \
175  mtlr r16;
176 #define TLB_MISS_PROLOG_STATS_BOLTED \
177  mflr r10; \
178  std r8,PACA_EXTLB+EX_TLB_R8(r13); \
179  std r9,PACA_EXTLB+EX_TLB_R9(r13); \
180  std r10,PACA_EXTLB+EX_TLB_LR(r13);
181 #define TLB_MISS_RESTORE_STATS_BOLTED \
182  ld r16,PACA_EXTLB+EX_TLB_LR(r13); \
183  ld r9,PACA_EXTLB+EX_TLB_R9(r13); \
184  ld r8,PACA_EXTLB+EX_TLB_R8(r13); \
185  mtlr r16;
186 #define TLB_MISS_STATS_D(name) \
187  addi r9,r13,MMSTAT_DSTATS+name; \
188  bl .tlb_stat_inc;
189 #define TLB_MISS_STATS_I(name) \
190  addi r9,r13,MMSTAT_ISTATS+name; \
191  bl .tlb_stat_inc;
192 #define TLB_MISS_STATS_X(name) \
193  ld r8,PACA_EXTLB+EX_TLB_ESR(r13); \
194  cmpdi cr2,r8,-1; \
195  beq cr2,61f; \
196  addi r9,r13,MMSTAT_DSTATS+name; \
197  b 62f; \
198 61: addi r9,r13,MMSTAT_ISTATS+name; \
199 62: bl .tlb_stat_inc;
200 #define TLB_MISS_STATS_SAVE_INFO \
201  std r14,EX_TLB_ESR(r12); /* save ESR */
202 #define TLB_MISS_STATS_SAVE_INFO_BOLTED \
203  std r14,PACA_EXTLB+EX_TLB_ESR(r13); /* save ESR */
204 #else
205 #define TLB_MISS_PROLOG_STATS
206 #define TLB_MISS_RESTORE_STATS
207 #define TLB_MISS_PROLOG_STATS_BOLTED
208 #define TLB_MISS_RESTORE_STATS_BOLTED
209 #define TLB_MISS_STATS_D(name)
210 #define TLB_MISS_STATS_I(name)
211 #define TLB_MISS_STATS_X(name)
212 #define TLB_MISS_STATS_Y(name)
213 #define TLB_MISS_STATS_SAVE_INFO
214 #define TLB_MISS_STATS_SAVE_INFO_BOLTED
215 #endif
216 
217 #define SET_IVOR(vector_number, vector_offset) \
218  li r3,vector_offset@l; \
219  ori r3,r3,interrupt_base_book3e@l; \
220  mtspr SPRN_IVOR##vector_number,r3;
221 
222 #endif /* _ASM_POWERPC_EXCEPTION_64E_H */
223 
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