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nv84.c
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1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 
25 #include <core/os.h>
26 #include <core/client.h>
27 #include <core/engctx.h>
28 #include <core/ramht.h>
29 #include <core/class.h>
30 #include <core/math.h>
31 
32 #include <subdev/timer.h>
33 #include <subdev/bar.h>
34 
35 #include <engine/dmaobj.h>
36 #include <engine/fifo.h>
37 
38 #include "nv50.h"
39 
40 /*******************************************************************************
41  * FIFO channel objects
42  ******************************************************************************/
43 
44 static int
45 nv84_fifo_context_attach(struct nouveau_object *parent,
46  struct nouveau_object *object)
47 {
48  struct nouveau_bar *bar = nouveau_bar(parent);
49  struct nv50_fifo_base *base = (void *)parent->parent;
50  struct nouveau_gpuobj *ectx = (void *)object;
51  u64 limit = ectx->addr + ectx->size - 1;
52  u64 start = ectx->addr;
53  u32 addr;
54 
55  switch (nv_engidx(object->engine)) {
56  case NVDEV_ENGINE_SW : return 0;
57  case NVDEV_ENGINE_GR : addr = 0x0020; break;
58  case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
59  case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break;
60  case NVDEV_ENGINE_COPY0: addr = 0x00c0; break;
61  default:
62  return -EINVAL;
63  }
64 
65  nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
66  nv_wo32(base->eng, addr + 0x00, 0x00190000);
67  nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));
68  nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));
69  nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 |
70  upper_32_bits(start));
71  nv_wo32(base->eng, addr + 0x10, 0x00000000);
72  nv_wo32(base->eng, addr + 0x14, 0x00000000);
73  bar->flush(bar);
74  return 0;
75 }
76 
77 static int
78 nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
79  struct nouveau_object *object)
80 {
81  struct nouveau_bar *bar = nouveau_bar(parent);
82  struct nv50_fifo_priv *priv = (void *)parent->engine;
83  struct nv50_fifo_base *base = (void *)parent->parent;
84  struct nv50_fifo_chan *chan = (void *)parent;
85  u32 addr, save, engn;
86  bool done;
87 
88  switch (nv_engidx(object->engine)) {
89  case NVDEV_ENGINE_SW : return 0;
90  case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break;
91  case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
92  case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break;
93  case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break;
94  default:
95  return -EINVAL;
96  }
97 
98  nv_wo32(base->eng, addr + 0x00, 0x00000000);
99  nv_wo32(base->eng, addr + 0x04, 0x00000000);
100  nv_wo32(base->eng, addr + 0x08, 0x00000000);
101  nv_wo32(base->eng, addr + 0x0c, 0x00000000);
102  nv_wo32(base->eng, addr + 0x10, 0x00000000);
103  nv_wo32(base->eng, addr + 0x14, 0x00000000);
104  bar->flush(bar);
105 
106  save = nv_mask(priv, 0x002520, 0x0000003f, 1 << engn);
107  nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);
108  done = nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff);
109  nv_wr32(priv, 0x002520, save);
110  if (!done) {
111  nv_error(priv, "channel %d unload timeout\n", chan->base.chid);
112  if (suspend)
113  return -EBUSY;
114  }
115  return 0;
116 }
117 
118 static int
119 nv84_fifo_object_attach(struct nouveau_object *parent,
120  struct nouveau_object *object, u32 handle)
121 {
122  struct nv50_fifo_chan *chan = (void *)parent;
123  u32 context;
124 
125  if (nv_iclass(object, NV_GPUOBJ_CLASS))
126  context = nv_gpuobj(object)->node->offset >> 4;
127  else
128  context = 0x00000004; /* just non-zero */
129 
130  switch (nv_engidx(object->engine)) {
131  case NVDEV_ENGINE_DMAOBJ:
132  case NVDEV_ENGINE_SW : context |= 0x00000000; break;
133  case NVDEV_ENGINE_GR : context |= 0x00100000; break;
134  case NVDEV_ENGINE_MPEG :
135  case NVDEV_ENGINE_PPP : context |= 0x00200000; break;
136  case NVDEV_ENGINE_ME :
137  case NVDEV_ENGINE_COPY0 : context |= 0x00300000; break;
138  case NVDEV_ENGINE_VP : context |= 0x00400000; break;
139  case NVDEV_ENGINE_CRYPT :
140  case NVDEV_ENGINE_UNK1C1: context |= 0x00500000; break;
141  case NVDEV_ENGINE_BSP : context |= 0x00600000; break;
142  default:
143  return -EINVAL;
144  }
145 
146  return nouveau_ramht_insert(chan->ramht, 0, handle, context);
147 }
148 
149 static int
150 nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
151  struct nouveau_object *engine,
152  struct nouveau_oclass *oclass, void *data, u32 size,
153  struct nouveau_object **pobject)
154 {
155  struct nouveau_bar *bar = nouveau_bar(parent);
156  struct nv50_fifo_base *base = (void *)parent;
157  struct nv50_fifo_chan *chan;
158  struct nv03_channel_dma_class *args = data;
159  int ret;
160 
161  if (size < sizeof(*args))
162  return -EINVAL;
163 
164  ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
165  0x2000, args->pushbuf,
166  (1 << NVDEV_ENGINE_DMAOBJ) |
167  (1 << NVDEV_ENGINE_SW) |
168  (1 << NVDEV_ENGINE_GR) |
169  (1 << NVDEV_ENGINE_MPEG) |
170  (1 << NVDEV_ENGINE_ME) |
171  (1 << NVDEV_ENGINE_VP) |
172  (1 << NVDEV_ENGINE_CRYPT) |
173  (1 << NVDEV_ENGINE_BSP) |
174  (1 << NVDEV_ENGINE_PPP) |
175  (1 << NVDEV_ENGINE_COPY0) |
176  (1 << NVDEV_ENGINE_UNK1C1), &chan);
177  *pobject = nv_object(chan);
178  if (ret)
179  return ret;
180 
181  ret = nouveau_ramht_new(parent, parent, 0x8000, 16, &chan->ramht);
182  if (ret)
183  return ret;
184 
185  nv_parent(chan)->context_attach = nv84_fifo_context_attach;
186  nv_parent(chan)->context_detach = nv84_fifo_context_detach;
187  nv_parent(chan)->object_attach = nv84_fifo_object_attach;
188  nv_parent(chan)->object_detach = nv50_fifo_object_detach;
189 
190  nv_wo32(base->ramfc, 0x08, lower_32_bits(args->offset));
191  nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->offset));
192  nv_wo32(base->ramfc, 0x10, lower_32_bits(args->offset));
193  nv_wo32(base->ramfc, 0x14, upper_32_bits(args->offset));
194  nv_wo32(base->ramfc, 0x3c, 0x003f6078);
195  nv_wo32(base->ramfc, 0x44, 0x01003fff);
196  nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
197  nv_wo32(base->ramfc, 0x4c, 0xffffffff);
198  nv_wo32(base->ramfc, 0x60, 0x7fffffff);
199  nv_wo32(base->ramfc, 0x78, 0x00000000);
200  nv_wo32(base->ramfc, 0x7c, 0x30000001);
201  nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
202  (4 << 24) /* SEARCH_FULL */ |
203  (chan->ramht->base.node->offset >> 4));
204  nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
205  nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
206  bar->flush(bar);
207  return 0;
208 }
209 
210 static int
211 nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
212  struct nouveau_object *engine,
213  struct nouveau_oclass *oclass, void *data, u32 size,
214  struct nouveau_object **pobject)
215 {
216  struct nouveau_bar *bar = nouveau_bar(parent);
217  struct nv50_fifo_base *base = (void *)parent;
218  struct nv50_fifo_chan *chan;
219  struct nv50_channel_ind_class *args = data;
220  u64 ioffset, ilength;
221  int ret;
222 
223  if (size < sizeof(*args))
224  return -EINVAL;
225 
226  ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
227  0x2000, args->pushbuf,
228  (1 << NVDEV_ENGINE_DMAOBJ) |
229  (1 << NVDEV_ENGINE_SW) |
230  (1 << NVDEV_ENGINE_GR) |
231  (1 << NVDEV_ENGINE_MPEG) |
232  (1 << NVDEV_ENGINE_ME) |
233  (1 << NVDEV_ENGINE_VP) |
234  (1 << NVDEV_ENGINE_CRYPT) |
235  (1 << NVDEV_ENGINE_BSP) |
236  (1 << NVDEV_ENGINE_PPP) |
237  (1 << NVDEV_ENGINE_COPY0) |
238  (1 << NVDEV_ENGINE_UNK1C1), &chan);
239  *pobject = nv_object(chan);
240  if (ret)
241  return ret;
242 
243  ret = nouveau_ramht_new(parent, parent, 0x8000, 16, &chan->ramht);
244  if (ret)
245  return ret;
246 
247  nv_parent(chan)->context_attach = nv84_fifo_context_attach;
248  nv_parent(chan)->context_detach = nv84_fifo_context_detach;
249  nv_parent(chan)->object_attach = nv84_fifo_object_attach;
250  nv_parent(chan)->object_detach = nv50_fifo_object_detach;
251 
252  ioffset = args->ioffset;
253  ilength = log2i(args->ilength / 8);
254 
255  nv_wo32(base->ramfc, 0x3c, 0x403f6078);
256  nv_wo32(base->ramfc, 0x44, 0x01003fff);
257  nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
258  nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));
259  nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
260  nv_wo32(base->ramfc, 0x60, 0x7fffffff);
261  nv_wo32(base->ramfc, 0x78, 0x00000000);
262  nv_wo32(base->ramfc, 0x7c, 0x30000001);
263  nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
264  (4 << 24) /* SEARCH_FULL */ |
265  (chan->ramht->base.node->offset >> 4));
266  nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
267  nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
268  bar->flush(bar);
269  return 0;
270 }
271 
272 static int
273 nv84_fifo_chan_init(struct nouveau_object *object)
274 {
275  struct nv50_fifo_priv *priv = (void *)object->engine;
276  struct nv50_fifo_base *base = (void *)object->parent;
277  struct nv50_fifo_chan *chan = (void *)object;
278  struct nouveau_gpuobj *ramfc = base->ramfc;
279  u32 chid = chan->base.chid;
280  int ret;
281 
282  ret = nouveau_fifo_channel_init(&chan->base);
283  if (ret)
284  return ret;
285 
286  nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8);
287  nv50_fifo_playlist_update(priv);
288  return 0;
289 }
290 
291 static struct nouveau_ofuncs
292 nv84_fifo_ofuncs_dma = {
293  .ctor = nv84_fifo_chan_ctor_dma,
294  .dtor = nv50_fifo_chan_dtor,
295  .init = nv84_fifo_chan_init,
296  .fini = nv50_fifo_chan_fini,
297  .rd32 = _nouveau_fifo_channel_rd32,
298  .wr32 = _nouveau_fifo_channel_wr32,
299 };
300 
301 static struct nouveau_ofuncs
302 nv84_fifo_ofuncs_ind = {
303  .ctor = nv84_fifo_chan_ctor_ind,
304  .dtor = nv50_fifo_chan_dtor,
305  .init = nv84_fifo_chan_init,
306  .fini = nv50_fifo_chan_fini,
307  .rd32 = _nouveau_fifo_channel_rd32,
308  .wr32 = _nouveau_fifo_channel_wr32,
309 };
310 
311 static struct nouveau_oclass
312 nv84_fifo_sclass[] = {
313  { NV84_CHANNEL_DMA_CLASS, &nv84_fifo_ofuncs_dma },
314  { NV84_CHANNEL_IND_CLASS, &nv84_fifo_ofuncs_ind },
315  {}
316 };
317 
318 /*******************************************************************************
319  * FIFO context - basically just the instmem reserved for the channel
320  ******************************************************************************/
321 
322 static int
323 nv84_fifo_context_ctor(struct nouveau_object *parent,
324  struct nouveau_object *engine,
325  struct nouveau_oclass *oclass, void *data, u32 size,
326  struct nouveau_object **pobject)
327 {
328  struct nv50_fifo_base *base;
329  int ret;
330 
331  ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
332  0x1000, NVOBJ_FLAG_HEAP, &base);
333  *pobject = nv_object(base);
334  if (ret)
335  return ret;
336 
337  ret = nouveau_gpuobj_new(parent, nv_object(base), 0x0200, 0,
338  NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
339  if (ret)
340  return ret;
341 
342  ret = nouveau_gpuobj_new(parent, nv_object(base), 0x4000, 0,
343  0, &base->pgd);
344  if (ret)
345  return ret;
346 
347  ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
348  if (ret)
349  return ret;
350 
351  ret = nouveau_gpuobj_new(parent, nv_object(base), 0x1000, 0x400,
352  NVOBJ_FLAG_ZERO_ALLOC, &base->cache);
353  if (ret)
354  return ret;
355 
356  ret = nouveau_gpuobj_new(parent, nv_object(base), 0x0100, 0x100,
357  NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
358  if (ret)
359  return ret;
360 
361  return 0;
362 }
363 
364 static struct nouveau_oclass
365 nv84_fifo_cclass = {
366  .handle = NV_ENGCTX(FIFO, 0x84),
367  .ofuncs = &(struct nouveau_ofuncs) {
368  .ctor = nv84_fifo_context_ctor,
369  .dtor = nv50_fifo_context_dtor,
370  .init = _nouveau_fifo_context_init,
371  .fini = _nouveau_fifo_context_fini,
372  .rd32 = _nouveau_fifo_context_rd32,
373  .wr32 = _nouveau_fifo_context_wr32,
374  },
375 };
376 
377 /*******************************************************************************
378  * PFIFO engine
379  ******************************************************************************/
380 
381 static int
382 nv84_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
383  struct nouveau_oclass *oclass, void *data, u32 size,
384  struct nouveau_object **pobject)
385 {
386  struct nv50_fifo_priv *priv;
387  int ret;
388 
389  ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv);
390  *pobject = nv_object(priv);
391  if (ret)
392  return ret;
393 
394  ret = nouveau_gpuobj_new(parent, NULL, 128 * 4, 0x1000, 0,
395  &priv->playlist[0]);
396  if (ret)
397  return ret;
398 
399  ret = nouveau_gpuobj_new(parent, NULL, 128 * 4, 0x1000, 0,
400  &priv->playlist[1]);
401  if (ret)
402  return ret;
403 
404  nv_subdev(priv)->unit = 0x00000100;
405  nv_subdev(priv)->intr = nv04_fifo_intr;
406  nv_engine(priv)->cclass = &nv84_fifo_cclass;
407  nv_engine(priv)->sclass = nv84_fifo_sclass;
408  return 0;
409 }
410 
411 struct nouveau_oclass
412 nv84_fifo_oclass = {
413  .handle = NV_ENGINE(FIFO, 0x84),
414  .ofuncs = &(struct nouveau_ofuncs) {
415  .ctor = nv84_fifo_ctor,
416  .dtor = nv50_fifo_dtor,
417  .init = nv50_fifo_init,
418  .fini = _nouveau_fifo_fini,
419  },
420 };
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