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10 #ifndef __BFIN_ASM_FIXED_CODE_H__
11 #define __BFIN_ASM_FIXED_CODE_H__
15 #include <linux/linkage.h>
16 #include <linux/ptrace.h>
18 extern char fixed_code_start;
19 extern char fixed_code_end;
20 extern int atomic_xchg32(
void);
21 extern int atomic_cas32(
void);
22 extern int atomic_add32(
void);
23 extern int atomic_sub32(
void);
24 extern int atomic_ior32(
void);
25 extern int atomic_and32(
void);
26 extern int atomic_xor32(
void);
27 extern void safe_user_instruction(
void);
28 extern void sigreturn_stub(
void);
32 #ifndef CONFIG_PHY_RAM_BASE_ADDRESS
33 #define CONFIG_PHY_RAM_BASE_ADDRESS 0x0
36 #define FIXED_CODE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
38 #define SIGRETURN_STUB (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
40 #define ATOMIC_SEQS_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
42 #define ATOMIC_XCHG32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
43 #define ATOMIC_CAS32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x420)
44 #define ATOMIC_ADD32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x430)
45 #define ATOMIC_SUB32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x440)
46 #define ATOMIC_IOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x450)
47 #define ATOMIC_AND32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x460)
48 #define ATOMIC_XOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x470)
50 #define ATOMIC_SEQS_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
52 #define SAFE_USER_INSTRUCTION (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
54 #define FIXED_CODE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x490)