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fsl_guts.h
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1 
15 #ifndef __ASM_POWERPC_FSL_GUTS_H__
16 #define __ASM_POWERPC_FSL_GUTS_H__
17 #ifdef __KERNEL__
18 
30 struct ccsr_guts {
31  __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
32  __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
33  __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
34  __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
35  __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
36  __be32 pordevsr2; /* 0x.0014 - POR device status register 2 */
37  u8 res018[0x20 - 0x18];
38  __be32 porcir; /* 0x.0020 - POR Configuration Information Register */
39  u8 res024[0x30 - 0x24];
40  __be32 gpiocr; /* 0x.0030 - GPIO Control Register */
41  u8 res034[0x40 - 0x34];
42  __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
43  u8 res044[0x50 - 0x44];
44  __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */
45  u8 res054[0x60 - 0x54];
46  __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
47  __be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */
48  __be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
49  u8 res06c[0x70 - 0x6c];
50  __be32 devdisr; /* 0x.0070 - Device Disable Control */
51 #define CCSR_GUTS_DEVDISR_TB1 0x00001000
52 #define CCSR_GUTS_DEVDISR_TB0 0x00004000
53  __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
54  u8 res078[0x7c - 0x78];
55  __be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */
56  __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
57  __be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */
58  __be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */
59  __be32 pmcdr; /* 0x.008c - 4Power management clock disable register */
60  __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
61  __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */
62  __be32 ectrstcr; /* 0x.0098 - Exception reset control register */
63  __be32 autorstsr; /* 0x.009c - Automatic reset status register */
64  __be32 pvr; /* 0x.00a0 - Processor Version Register */
65  __be32 svr; /* 0x.00a4 - System Version Register */
66  u8 res0a8[0xb0 - 0xa8];
67  __be32 rstcr; /* 0x.00b0 - Reset Control Register */
68  u8 res0b4[0xc0 - 0xb4];
69  __be32 iovselsr; /* 0x.00c0 - I/O voltage select status register
70  Called 'elbcvselcr' on 86xx SOCs */
71  u8 res0c4[0x224 - 0xc4];
72  __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
73  __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
74  u8 res22c[0x800 - 0x22c];
75  __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
76  u8 res804[0x900 - 0x804];
77  __be32 ircr; /* 0x.0900 - Infrared Control Register */
78  u8 res904[0x908 - 0x904];
79  __be32 dmacr; /* 0x.0908 - DMA Control Register */
80  u8 res90c[0x914 - 0x90c];
81  __be32 elbccr; /* 0x.0914 - eLBC Control Register */
82  u8 res918[0xb20 - 0x918];
83  __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
84  __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
85  __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
86  u8 resb2c[0xe00 - 0xb2c];
87  __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */
88  u8 rese04[0xe10 - 0xe04];
89  __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
90  u8 rese14[0xe20 - 0xe14];
91  __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
92  __be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */
93  u8 rese28[0xf04 - 0xe28];
94  __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
95  __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
96  u8 resf0c[0xf2c - 0xf0c];
97  __be32 itcr; /* 0x.0f2c - Internal transaction control register */
98  u8 resf30[0xf40 - 0xf30];
99  __be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
100  __be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
101 } __attribute__ ((packed));
102 
103 
104 /* Alternate function signal multiplex control */
105 #define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
106 
107 #ifdef CONFIG_PPC_86xx
108 
109 #define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */
110 #define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */
111 
112 /*
113  * Set the DMACR register in the GUTS
114  *
115  * The DMACR register determines the source of initiated transfers for each
116  * channel on each DMA controller. Rather than have a bunch of repetitive
117  * macros for the bit patterns, we just have a function that calculates
118  * them.
119  *
120  * guts: Pointer to GUTS structure
121  * co: The DMA controller (0 or 1)
122  * ch: The channel on the DMA controller (0, 1, 2, or 3)
123  * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
124  */
125 static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
126  unsigned int co, unsigned int ch, unsigned int device)
127 {
128  unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
129 
130  clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
131 }
132 
133 #define CCSR_GUTS_PMUXCR_LDPSEL 0x00010000
134 #define CCSR_GUTS_PMUXCR_SSI1_MASK 0x0000C000 /* Bitmask for SSI1 */
135 #define CCSR_GUTS_PMUXCR_SSI1_LA 0x00000000 /* Latched address */
136 #define CCSR_GUTS_PMUXCR_SSI1_HI 0x00004000 /* High impedance */
137 #define CCSR_GUTS_PMUXCR_SSI1_SSI 0x00008000 /* Used for SSI1 */
138 #define CCSR_GUTS_PMUXCR_SSI2_MASK 0x00003000 /* Bitmask for SSI2 */
139 #define CCSR_GUTS_PMUXCR_SSI2_LA 0x00000000 /* Latched address */
140 #define CCSR_GUTS_PMUXCR_SSI2_HI 0x00001000 /* High impedance */
141 #define CCSR_GUTS_PMUXCR_SSI2_SSI 0x00002000 /* Used for SSI2 */
142 #define CCSR_GUTS_PMUXCR_LA_22_25_LA 0x00000000 /* Latched Address */
143 #define CCSR_GUTS_PMUXCR_LA_22_25_HI 0x00000400 /* High impedance */
144 #define CCSR_GUTS_PMUXCR_DBGDRV 0x00000200 /* Signals not driven */
145 #define CCSR_GUTS_PMUXCR_DMA2_0 0x00000008
146 #define CCSR_GUTS_PMUXCR_DMA2_3 0x00000004
147 #define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002
148 #define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001
149 
150 /*
151  * Set the DMA external control bits in the GUTS
152  *
153  * The DMA external control bits in the PMUXCR are only meaningful for
154  * channels 0 and 3. Any other channels are ignored.
155  *
156  * guts: Pointer to GUTS structure
157  * co: The DMA controller (0 or 1)
158  * ch: The channel on the DMA controller (0, 1, 2, or 3)
159  * value: the new value for the bit (0 or 1)
160  */
161 static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
162  unsigned int co, unsigned int ch, unsigned int value)
163 {
164  if ((ch == 0) || (ch == 3)) {
165  unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;
166 
167  clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
168  }
169 }
170 
171 #define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000
172 #define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000
173 #define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000
174 #define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25
175 #define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK 0x06000000
176 #define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \
177  (((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT)
178 #define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT 16
179 #define CCSR_GUTS_CLKDVDR_PXCLK_MASK 0x001F0000
180 #define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT)
181 #define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF
182 #define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
183 
184 #endif
185 
186 #endif
187 #endif
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