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34 #define DRV_BUF_FLUSH(desc,flag)
35 #define DDI_DMA_SYNC_FORCPU
36 #define DDI_DMA_SYNC_FORDEV
42 #define RX_ENABLE_PASS_SMT 21
43 #define RX_DISABLE_PASS_SMT 22
44 #define RX_ENABLE_PASS_NSA 23
45 #define RX_DISABLE_PASS_NSA 24
46 #define RX_ENABLE_PASS_DB 25
47 #define RX_DISABLE_PASS_DB 26
48 #define RX_DISABLE_PASS_ALL 27
49 #define RX_DISABLE_LLC_PROMISC 28
50 #define RX_ENABLE_LLC_PROMISC 29
64 #define EN_IRQ_EOF 0x02
66 #define LAST_FRAG 0x08
67 #define FIRST_FRAG 0x10
69 #define RING_DOWN 0x40
70 #define OUT_OF_TXD 0x80
78 #define HWM_REVERSE(x) (x)
80 #define HWM_REVERSE(x) ((((x)<<24L)&0xff000000L) + \
81 (((x)<< 8L)&0x00ff0000L) + \
82 (((x)>> 8L)&0x0000ff00L) + \
83 (((x)>>24L)&0x000000ffL))
86 #define C_INDIC (1L<<25)
87 #define A_INDIC (1L<<26)
88 #define RD_FS_LOCAL 0x80
104 #define DB_HWM_GEN 12
107 #ifndef MB_OUTSIDE_SMC
175 #define DB_P smc->debug
180 #define DB_RX(a,b,c,lev) if (DB_P.d_os.hwm_rx >= (lev)) printf(a,b,c)
181 #define DB_TX(a,b,c,lev) if (DB_P.d_os.hwm_tx >= (lev)) printf(a,b,c)
182 #define DB_GEN(a,b,c,lev) if (DB_P.d_os.hwm_gen >= (lev)) printf(a,b,c)
184 #define DB_RX(a,b,c,lev)
185 #define DB_TX(a,b,c,lev)
186 #define DB_GEN(a,b,c,lev)
210 #define HWM_GET_TX_PHYS(txd) (u_long)AIX_REVERSE((txd)->txd_tbadr)
226 #define HWM_GET_TX_LEN(txd) ((int)AIX_REVERSE((txd)->txd_tbctrl)& RD_LENGTH)
243 #define HWM_GET_TX_USED(smc,queue) (int) (smc)->hw.fp.tx_q[queue].tx_used
261 #define HWM_GET_CURR_TXD(smc,queue) (struct s_smt_fp_txd volatile *)\
262 (smc)->hw.fp.tx_q[queue].tx_curr_put
278 #define HWM_GET_RX_FRAG_LEN(rxd) ((int)AIX_REVERSE((rxd)->rxd_rbctrl)& \
295 #define HWM_GET_RX_PHYS(rxd) (u_long)AIX_REVERSE((rxd)->rxd_rbadr)
312 #define HWM_GET_RX_USED(smc) ((int)(smc)->hw.fp.rx_q[QUEUE_R1].rx_used)
326 #define HWM_GET_RX_FREE(smc) ((int)(smc)->hw.fp.rx_q[QUEUE_R1].rx_free-1)
341 #define HWM_GET_CURR_RXD(smc) (struct s_smt_fp_rxd volatile *)\
342 (smc)->hw.fp.rx_q[QUEUE_R1].rx_curr_put
358 #ifndef HWM_NO_FLOW_CTL
359 #define HWM_RX_CHECK(smc,low_water) {\
360 if ((low_water) >= (smc)->hw.fp.rx_q[QUEUE_R1].rx_used) {\
361 mac_drv_fill_rxd(smc) ;\
365 #define HWM_RX_CHECK(smc,low_water) mac_drv_fill_rxd(smc)
369 #define HWM_EBASE 500
372 #define HWM_E0001 HWM_EBASE + 1
373 #define HWM_E0001_MSG "HWM: Wrong size of s_rxd_os struct"
374 #define HWM_E0002 HWM_EBASE + 2
375 #define HWM_E0002_MSG "HWM: Wrong size of s_txd_os struct"
376 #define HWM_E0003 HWM_EBASE + 3
377 #define HWM_E0003_MSG "HWM: smt_free_mbuf() called with NULL pointer"
378 #define HWM_E0004 HWM_EBASE + 4
379 #define HWM_E0004_MSG "HWM: Parity error rx queue 1"
380 #define HWM_E0005 HWM_EBASE + 5
381 #define HWM_E0005_MSG "HWM: Encoding error rx queue 1"
382 #define HWM_E0006 HWM_EBASE + 6
383 #define HWM_E0006_MSG "HWM: Encoding error async tx queue"
384 #define HWM_E0007 HWM_EBASE + 7
385 #define HWM_E0007_MSG "HWM: Encoding error sync tx queue"
386 #define HWM_E0008 HWM_EBASE + 8
387 #define HWM_E0008_MSG ""
388 #define HWM_E0009 HWM_EBASE + 9
389 #define HWM_E0009_MSG "HWM: Out of RxD condition detected"
390 #define HWM_E0010 HWM_EBASE + 10
391 #define HWM_E0010_MSG "HWM: A protocol layer has tried to send a frame with an invalid frame control"
392 #define HWM_E0011 HWM_EBASE + 11
393 #define HWM_E0011_MSG "HWM: mac_drv_clear_tx_queue was called although the hardware wasn't stopped"
394 #define HWM_E0012 HWM_EBASE + 12
395 #define HWM_E0012_MSG "HWM: mac_drv_clear_rx_queue was called although the hardware wasn't stopped"
396 #define HWM_E0013 HWM_EBASE + 13
397 #define HWM_E0013_MSG "HWM: mac_drv_repair_descr was called although the hardware wasn't stopped"