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i915_reg.h
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1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2  * All Rights Reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the
6  * "Software"), to deal in the Software without restriction, including
7  * without limitation the rights to use, copy, modify, merge, publish,
8  * distribute, sub license, and/or sell copies of the Software, and to
9  * permit persons to whom the Software is furnished to do so, subject to
10  * the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the
13  * next paragraph) shall be included in all copies or substantial portions
14  * of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
25 #ifndef _I915_REG_H_
26 #define _I915_REG_H_
27 
28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29 
30 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
31 
32 #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
33 #define _MASKED_BIT_DISABLE(a) ((a) << 16)
34 
35 /*
36  * The Bridge device's PCI config space has information about the
37  * fb aperture size and the amount of pre-reserved memory.
38  * This is all handled in the intel-gtt.ko module. i915.ko only
39  * cares about the vga bit for the vga rbiter.
40  */
41 #define INTEL_GMCH_CTRL 0x52
42 #define INTEL_GMCH_VGA_DISABLE (1 << 1)
43 
44 /* PCI config space */
45 
46 #define HPLLCC 0xc0 /* 855 only */
47 #define GC_CLOCK_CONTROL_MASK (0xf << 0)
48 #define GC_CLOCK_133_200 (0 << 0)
49 #define GC_CLOCK_100_200 (1 << 0)
50 #define GC_CLOCK_100_133 (2 << 0)
51 #define GC_CLOCK_166_250 (3 << 0)
52 #define GCFGC2 0xda
53 #define GCFGC 0xf0 /* 915+ only */
54 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
55 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
56 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
57 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
58 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
59 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
60 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
61 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
62 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
63 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
64 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
65 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
66 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
67 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
68 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
69 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
70 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
71 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
72 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
73 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
74 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
75 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
76 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
77 #define LBB 0xf4
78 
79 /* Graphics reset regs */
80 #define I965_GDRST 0xc0 /* PCI config register */
81 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */
82 #define GRDOM_FULL (0<<2)
83 #define GRDOM_RENDER (1<<2)
84 #define GRDOM_MEDIA (3<<2)
85 #define GRDOM_RESET_ENABLE (1<<0)
86 
87 #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
88 #define GEN6_MBC_SNPCR_SHIFT 21
89 #define GEN6_MBC_SNPCR_MASK (3<<21)
90 #define GEN6_MBC_SNPCR_MAX (0<<21)
91 #define GEN6_MBC_SNPCR_MED (1<<21)
92 #define GEN6_MBC_SNPCR_LOW (2<<21)
93 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
94 
95 #define GEN6_MBCTL 0x0907c
96 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
97 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
98 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
99 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
100 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
101 
102 #define GEN6_GDRST 0x941c
103 #define GEN6_GRDOM_FULL (1 << 0)
104 #define GEN6_GRDOM_RENDER (1 << 1)
105 #define GEN6_GRDOM_MEDIA (1 << 2)
106 #define GEN6_GRDOM_BLT (1 << 3)
107 
108 /* PPGTT stuff */
109 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
110 
111 #define GEN6_PDE_VALID (1 << 0)
112 #define GEN6_PDE_LARGE_PAGE (2 << 0) /* use 32kb pages */
113 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
114 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
115 
116 #define GEN6_PTE_VALID (1 << 0)
117 #define GEN6_PTE_UNCACHED (1 << 1)
118 #define HSW_PTE_UNCACHED (0)
119 #define GEN6_PTE_CACHE_LLC (2 << 1)
120 #define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
121 #define GEN6_PTE_CACHE_BITS (3 << 1)
122 #define GEN6_PTE_GFDT (1 << 3)
123 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
124 
125 #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
126 #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
127 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
128 #define PP_DIR_DCLV_2G 0xffffffff
129 
130 #define GAM_ECOCHK 0x4090
131 #define ECOCHK_SNB_BIT (1<<10)
132 #define ECOCHK_PPGTT_CACHE64B (0x3<<3)
133 #define ECOCHK_PPGTT_CACHE4B (0x0<<3)
134 
135 #define GAC_ECO_BITS 0x14090
136 #define ECOBITS_PPGTT_CACHE64B (3<<8)
137 #define ECOBITS_PPGTT_CACHE4B (0<<8)
138 
139 #define GAB_CTL 0x24000
140 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
141 
142 /* VGA stuff */
143 
144 #define VGA_ST01_MDA 0x3ba
145 #define VGA_ST01_CGA 0x3da
146 
147 #define VGA_MSR_WRITE 0x3c2
148 #define VGA_MSR_READ 0x3cc
149 #define VGA_MSR_MEM_EN (1<<1)
150 #define VGA_MSR_CGA_MODE (1<<0)
151 
152 #define VGA_SR_INDEX 0x3c4
153 #define VGA_SR_DATA 0x3c5
154 
155 #define VGA_AR_INDEX 0x3c0
156 #define VGA_AR_VID_EN (1<<5)
157 #define VGA_AR_DATA_WRITE 0x3c0
158 #define VGA_AR_DATA_READ 0x3c1
159 
160 #define VGA_GR_INDEX 0x3ce
161 #define VGA_GR_DATA 0x3cf
162 /* GR05 */
163 #define VGA_GR_MEM_READ_MODE_SHIFT 3
164 #define VGA_GR_MEM_READ_MODE_PLANE 1
165 /* GR06 */
166 #define VGA_GR_MEM_MODE_MASK 0xc
167 #define VGA_GR_MEM_MODE_SHIFT 2
168 #define VGA_GR_MEM_A0000_AFFFF 0
169 #define VGA_GR_MEM_A0000_BFFFF 1
170 #define VGA_GR_MEM_B0000_B7FFF 2
171 #define VGA_GR_MEM_B0000_BFFFF 3
172 
173 #define VGA_DACMASK 0x3c6
174 #define VGA_DACRX 0x3c7
175 #define VGA_DACWX 0x3c8
176 #define VGA_DACDATA 0x3c9
177 
178 #define VGA_CR_INDEX_MDA 0x3b4
179 #define VGA_CR_DATA_MDA 0x3b5
180 #define VGA_CR_INDEX_CGA 0x3d4
181 #define VGA_CR_DATA_CGA 0x3d5
182 
183 /*
184  * Memory interface instructions used by the kernel
185  */
186 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
187 
188 #define MI_NOOP MI_INSTR(0, 0)
189 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
190 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
191 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
192 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
193 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
194 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
195 #define MI_FLUSH MI_INSTR(0x04, 0)
196 #define MI_READ_FLUSH (1 << 0)
197 #define MI_EXE_FLUSH (1 << 1)
198 #define MI_NO_WRITE_FLUSH (1 << 2)
199 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
200 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
201 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
202 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
203 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
204 #define MI_SUSPEND_FLUSH_EN (1<<0)
205 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
206 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
207 #define MI_OVERLAY_CONTINUE (0x0<<21)
208 #define MI_OVERLAY_ON (0x1<<21)
209 #define MI_OVERLAY_OFF (0x2<<21)
210 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
211 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
212 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
213 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
214 /* IVB has funny definitions for which plane to flip. */
215 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
216 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
217 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
218 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
219 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
220 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
221 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
222 #define MI_ARB_ENABLE (1<<0)
223 #define MI_ARB_DISABLE (0<<0)
224 
225 #define MI_SET_CONTEXT MI_INSTR(0x18, 0)
226 #define MI_MM_SPACE_GTT (1<<8)
227 #define MI_MM_SPACE_PHYSICAL (0<<8)
228 #define MI_SAVE_EXT_STATE_EN (1<<3)
229 #define MI_RESTORE_EXT_STATE_EN (1<<2)
230 #define MI_FORCE_RESTORE (1<<1)
231 #define MI_RESTORE_INHIBIT (1<<0)
232 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
233 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
234 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
235 #define MI_STORE_DWORD_INDEX_SHIFT 2
236 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
237  * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
238  * simply ignores the register load under certain conditions.
239  * - One can actually load arbitrary many arbitrary registers: Simply issue x
240  * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
241  */
242 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
243 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
244 #define MI_INVALIDATE_TLB (1<<18)
245 #define MI_INVALIDATE_BSD (1<<7)
246 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
247 #define MI_BATCH_NON_SECURE (1)
248 #define MI_BATCH_NON_SECURE_I965 (1<<8)
249 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
250 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
251 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
252 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
253 #define MI_SEMAPHORE_UPDATE (1<<21)
254 #define MI_SEMAPHORE_COMPARE (1<<20)
255 #define MI_SEMAPHORE_REGISTER (1<<18)
256 #define MI_SEMAPHORE_SYNC_RV (2<<16)
257 #define MI_SEMAPHORE_SYNC_RB (0<<16)
258 #define MI_SEMAPHORE_SYNC_VR (0<<16)
259 #define MI_SEMAPHORE_SYNC_VB (2<<16)
260 #define MI_SEMAPHORE_SYNC_BR (2<<16)
261 #define MI_SEMAPHORE_SYNC_BV (0<<16)
262 #define MI_SEMAPHORE_SYNC_INVALID (1<<0)
263 /*
264  * 3D instructions used by the kernel
265  */
266 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
267 
268 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
269 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
270 #define SC_UPDATE_SCISSOR (0x1<<1)
271 #define SC_ENABLE_MASK (0x1<<0)
272 #define SC_ENABLE (0x1<<0)
273 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
274 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
275 #define SCI_YMIN_MASK (0xffff<<16)
276 #define SCI_XMIN_MASK (0xffff<<0)
277 #define SCI_YMAX_MASK (0xffff<<16)
278 #define SCI_XMAX_MASK (0xffff<<0)
279 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
280 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
281 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
282 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
283 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
284 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
285 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
286 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
287 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
288 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
289 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
290 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
291 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
292 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
293 #define BLT_DEPTH_8 (0<<24)
294 #define BLT_DEPTH_16_565 (1<<24)
295 #define BLT_DEPTH_16_1555 (2<<24)
296 #define BLT_DEPTH_32 (3<<24)
297 #define BLT_ROP_GXCOPY (0xcc<<16)
298 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
299 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
300 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
301 #define ASYNC_FLIP (1<<22)
302 #define DISPLAY_PLANE_A (0<<20)
303 #define DISPLAY_PLANE_B (1<<20)
304 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
305 #define PIPE_CONTROL_CS_STALL (1<<20)
306 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
307 #define PIPE_CONTROL_QW_WRITE (1<<14)
308 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
309 #define PIPE_CONTROL_WRITE_FLUSH (1<<12)
310 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
311 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
312 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
313 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
314 #define PIPE_CONTROL_NOTIFY (1<<8)
315 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
316 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
317 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
318 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
319 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
320 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
321 
322 
323 /*
324  * Reset registers
325  */
326 #define DEBUG_RESET_I830 0x6070
327 #define DEBUG_RESET_FULL (1<<7)
328 #define DEBUG_RESET_RENDER (1<<8)
329 #define DEBUG_RESET_DISPLAY (1<<9)
330 
331 /*
332  * DPIO - a special bus for various display related registers to hide behind:
333  * 0x800c: m1, m2, n, p1, p2, k dividers
334  * 0x8014: REF and SFR select
335  * 0x8014: N divider, VCO select
336  * 0x801c/3c: core clock bits
337  * 0x8048/68: low pass filter coefficients
338  * 0x8100: fast clock controls
339  */
340 #define DPIO_PKT 0x2100
341 #define DPIO_RID (0<<24)
342 #define DPIO_OP_WRITE (1<<16)
343 #define DPIO_OP_READ (0<<16)
344 #define DPIO_PORTID (0x12<<8)
345 #define DPIO_BYTE (0xf<<4)
346 #define DPIO_BUSY (1<<0) /* status only */
347 #define DPIO_DATA 0x2104
348 #define DPIO_REG 0x2108
349 #define DPIO_CTL 0x2110
350 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
351 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
352 #define DPIO_SFR_BYPASS (1<<1)
353 #define DPIO_RESET (1<<0)
354 
355 #define _DPIO_DIV_A 0x800c
356 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
357 #define DPIO_K_SHIFT (24) /* 4 bits */
358 #define DPIO_P1_SHIFT (21) /* 3 bits */
359 #define DPIO_P2_SHIFT (16) /* 5 bits */
360 #define DPIO_N_SHIFT (12) /* 4 bits */
361 #define DPIO_ENABLE_CALIBRATION (1<<11)
362 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
363 #define DPIO_M2DIV_MASK 0xff
364 #define _DPIO_DIV_B 0x802c
365 #define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B)
366 
367 #define _DPIO_REFSFR_A 0x8014
368 #define DPIO_REFSEL_OVERRIDE 27
369 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
370 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
371 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
372 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
373 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
374 #define _DPIO_REFSFR_B 0x8034
375 #define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B)
376 
377 #define _DPIO_CORE_CLK_A 0x801c
378 #define _DPIO_CORE_CLK_B 0x803c
379 #define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)
380 
381 #define _DPIO_LFP_COEFF_A 0x8048
382 #define _DPIO_LFP_COEFF_B 0x8068
383 #define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B)
384 
385 #define DPIO_FASTCLK_DISABLE 0x8100
386 
387 /*
388  * Fence registers
389  */
390 #define FENCE_REG_830_0 0x2000
391 #define FENCE_REG_945_8 0x3000
392 #define I830_FENCE_START_MASK 0x07f80000
393 #define I830_FENCE_TILING_Y_SHIFT 12
394 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
395 #define I830_FENCE_PITCH_SHIFT 4
396 #define I830_FENCE_REG_VALID (1<<0)
397 #define I915_FENCE_MAX_PITCH_VAL 4
398 #define I830_FENCE_MAX_PITCH_VAL 6
399 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
400 
401 #define I915_FENCE_START_MASK 0x0ff00000
402 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
403 
404 #define FENCE_REG_965_0 0x03000
405 #define I965_FENCE_PITCH_SHIFT 2
406 #define I965_FENCE_TILING_Y_SHIFT 1
407 #define I965_FENCE_REG_VALID (1<<0)
408 #define I965_FENCE_MAX_PITCH_VAL 0x0400
409 
410 #define FENCE_REG_SANDYBRIDGE_0 0x100000
411 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
412 
413 /* control register for cpu gtt access */
414 #define TILECTL 0x101000
415 #define TILECTL_SWZCTL (1 << 0)
416 #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
417 #define TILECTL_BACKSNOOP_DIS (1 << 3)
418 
419 /*
420  * Instruction and interrupt control regs
421  */
422 #define PGTBL_ER 0x02024
423 #define RENDER_RING_BASE 0x02000
424 #define BSD_RING_BASE 0x04000
425 #define GEN6_BSD_RING_BASE 0x12000
426 #define BLT_RING_BASE 0x22000
427 #define RING_TAIL(base) ((base)+0x30)
428 #define RING_HEAD(base) ((base)+0x34)
429 #define RING_START(base) ((base)+0x38)
430 #define RING_CTL(base) ((base)+0x3c)
431 #define RING_SYNC_0(base) ((base)+0x40)
432 #define RING_SYNC_1(base) ((base)+0x44)
433 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
434 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
435 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
436 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
437 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
438 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
439 #define RING_MAX_IDLE(base) ((base)+0x54)
440 #define RING_HWS_PGA(base) ((base)+0x80)
441 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
442 #define ARB_MODE 0x04030
443 #define ARB_MODE_SWIZZLE_SNB (1<<4)
444 #define ARB_MODE_SWIZZLE_IVB (1<<5)
445 #define RENDER_HWS_PGA_GEN7 (0x04080)
446 #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
447 #define DONE_REG 0x40b0
448 #define BSD_HWS_PGA_GEN7 (0x04180)
449 #define BLT_HWS_PGA_GEN7 (0x04280)
450 #define RING_ACTHD(base) ((base)+0x74)
451 #define RING_NOPID(base) ((base)+0x94)
452 #define RING_IMR(base) ((base)+0xa8)
453 #define RING_TIMESTAMP(base) ((base)+0x358)
454 #define TAIL_ADDR 0x001FFFF8
455 #define HEAD_WRAP_COUNT 0xFFE00000
456 #define HEAD_WRAP_ONE 0x00200000
457 #define HEAD_ADDR 0x001FFFFC
458 #define RING_NR_PAGES 0x001FF000
459 #define RING_REPORT_MASK 0x00000006
460 #define RING_REPORT_64K 0x00000002
461 #define RING_REPORT_128K 0x00000004
462 #define RING_NO_REPORT 0x00000000
463 #define RING_VALID_MASK 0x00000001
464 #define RING_VALID 0x00000001
465 #define RING_INVALID 0x00000000
466 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
467 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
468 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
469 #if 0
470 #define PRB0_TAIL 0x02030
471 #define PRB0_HEAD 0x02034
472 #define PRB0_START 0x02038
473 #define PRB0_CTL 0x0203c
474 #define PRB1_TAIL 0x02040 /* 915+ only */
475 #define PRB1_HEAD 0x02044 /* 915+ only */
476 #define PRB1_START 0x02048 /* 915+ only */
477 #define PRB1_CTL 0x0204c /* 915+ only */
478 #endif
479 #define IPEIR_I965 0x02064
480 #define IPEHR_I965 0x02068
481 #define INSTDONE_I965 0x0206c
482 #define GEN7_INSTDONE_1 0x0206c
483 #define GEN7_SC_INSTDONE 0x07100
484 #define GEN7_SAMPLER_INSTDONE 0x0e160
485 #define GEN7_ROW_INSTDONE 0x0e164
486 #define I915_NUM_INSTDONE_REG 4
487 #define RING_IPEIR(base) ((base)+0x64)
488 #define RING_IPEHR(base) ((base)+0x68)
489 #define RING_INSTDONE(base) ((base)+0x6c)
490 #define RING_INSTPS(base) ((base)+0x70)
491 #define RING_DMA_FADD(base) ((base)+0x78)
492 #define RING_INSTPM(base) ((base)+0xc0)
493 #define INSTPS 0x02070 /* 965+ only */
494 #define INSTDONE1 0x0207c /* 965+ only */
495 #define ACTHD_I965 0x02074
496 #define HWS_PGA 0x02080
497 #define HWS_ADDRESS_MASK 0xfffff000
498 #define HWS_START_ADDRESS_SHIFT 4
499 #define PWRCTXA 0x2088 /* 965GM+ only */
500 #define PWRCTX_EN (1<<0)
501 #define IPEIR 0x02088
502 #define IPEHR 0x0208c
503 #define INSTDONE 0x02090
504 #define NOPID 0x02094
505 #define HWSTAM 0x02098
506 #define DMA_FADD_I8XX 0x020d0
507 
508 #define ERROR_GEN6 0x040a0
509 #define GEN7_ERR_INT 0x44040
510 #define ERR_INT_MMIO_UNCLAIMED (1<<13)
511 
512 /* GM45+ chicken bits -- debug workaround bits that may be required
513  * for various sorts of correct behavior. The top 16 bits of each are
514  * the enables for writing to the corresponding low bit.
515  */
516 #define _3D_CHICKEN 0x02084
517 #define _3D_CHICKEN2 0x0208c
518 /* Disables pipelining of read flushes past the SF-WIZ interface.
519  * Required on all Ironlake steppings according to the B-Spec, but the
520  * particular danger of not doing so is not specified.
521  */
522 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
523 #define _3D_CHICKEN3 0x02090
524 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
525 
526 #define MI_MODE 0x0209c
527 # define VS_TIMER_DISPATCH (1 << 6)
528 # define MI_FLUSH_ENABLE (1 << 12)
529 
530 #define GEN6_GT_MODE 0x20d0
531 #define GEN6_GT_MODE_HI (1 << 9)
532 
533 #define GFX_MODE 0x02520
534 #define GFX_MODE_GEN7 0x0229c
535 #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
536 #define GFX_RUN_LIST_ENABLE (1<<15)
537 #define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
538 #define GFX_SURFACE_FAULT_ENABLE (1<<12)
539 #define GFX_REPLAY_MODE (1<<11)
540 #define GFX_PSMI_GRANULARITY (1<<10)
541 #define GFX_PPGTT_ENABLE (1<<9)
542 
543 #define VLV_DISPLAY_BASE 0x180000
544 
545 #define SCPD0 0x0209c /* 915+ only */
546 #define IER 0x020a0
547 #define IIR 0x020a4
548 #define IMR 0x020a8
549 #define ISR 0x020ac
550 #define VLV_IIR_RW 0x182084
551 #define VLV_IER 0x1820a0
552 #define VLV_IIR 0x1820a4
553 #define VLV_IMR 0x1820a8
554 #define VLV_ISR 0x1820ac
555 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
556 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
557 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
558 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
559 #define I915_HWB_OOM_INTERRUPT (1<<13)
560 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
561 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
562 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
563 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
564 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
565 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
566 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
567 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
568 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
569 #define I915_DEBUG_INTERRUPT (1<<2)
570 #define I915_USER_INTERRUPT (1<<1)
571 #define I915_ASLE_INTERRUPT (1<<0)
572 #define I915_BSD_USER_INTERRUPT (1<<25)
573 #define EIR 0x020b0
574 #define EMR 0x020b4
575 #define ESR 0x020b8
576 #define GM45_ERROR_PAGE_TABLE (1<<5)
577 #define GM45_ERROR_MEM_PRIV (1<<4)
578 #define I915_ERROR_PAGE_TABLE (1<<4)
579 #define GM45_ERROR_CP_PRIV (1<<3)
580 #define I915_ERROR_MEMORY_REFRESH (1<<1)
581 #define I915_ERROR_INSTRUCTION (1<<0)
582 #define INSTPM 0x020c0
583 #define INSTPM_SELF_EN (1<<12) /* 915GM only */
584 #define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
585  will not assert AGPBUSY# and will only
586  be delivered when out of C3. */
587 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
588 #define ACTHD 0x020c8
589 #define FW_BLC 0x020d8
590 #define FW_BLC2 0x020dc
591 #define FW_BLC_SELF 0x020e0 /* 915+ only */
592 #define FW_BLC_SELF_EN_MASK (1<<31)
593 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
594 #define FW_BLC_SELF_EN (1<<15) /* 945 only */
595 #define MM_BURST_LENGTH 0x00700000
596 #define MM_FIFO_WATERMARK 0x0001F000
597 #define LM_BURST_LENGTH 0x00000700
598 #define LM_FIFO_WATERMARK 0x0000001F
599 #define MI_ARB_STATE 0x020e4 /* 915+ only */
600 
601 /* Make render/texture TLB fetches lower priorty than associated data
602  * fetches. This is not turned on by default
603  */
604 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
605 
606 /* Isoch request wait on GTT enable (Display A/B/C streams).
607  * Make isoch requests stall on the TLB update. May cause
608  * display underruns (test mode only)
609  */
610 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
611 
612 /* Block grant count for isoch requests when block count is
613  * set to a finite value.
614  */
615 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
616 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
617 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
618 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
619 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
620 
621 /* Enable render writes to complete in C2/C3/C4 power states.
622  * If this isn't enabled, render writes are prevented in low
623  * power states. That seems bad to me.
624  */
625 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
626 
627 /* This acknowledges an async flip immediately instead
628  * of waiting for 2TLB fetches.
629  */
630 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
631 
632 /* Enables non-sequential data reads through arbiter
633  */
634 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
635 
636 /* Disable FSB snooping of cacheable write cycles from binner/render
637  * command stream
638  */
639 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
641 /* Arbiter time slice for non-isoch streams */
642 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
643 #define MI_ARB_TIME_SLICE_1 (0 << 5)
644 #define MI_ARB_TIME_SLICE_2 (1 << 5)
645 #define MI_ARB_TIME_SLICE_4 (2 << 5)
646 #define MI_ARB_TIME_SLICE_6 (3 << 5)
647 #define MI_ARB_TIME_SLICE_8 (4 << 5)
648 #define MI_ARB_TIME_SLICE_10 (5 << 5)
649 #define MI_ARB_TIME_SLICE_14 (6 << 5)
650 #define MI_ARB_TIME_SLICE_16 (7 << 5)
652 /* Low priority grace period page size */
653 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
654 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
656 /* Disable display A/B trickle feed */
657 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
659 /* Set display plane priority */
660 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
661 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
663 #define CACHE_MODE_0 0x02120 /* 915+ only */
664 #define CM0_IZ_OPT_DISABLE (1<<6)
665 #define CM0_ZR_OPT_DISABLE (1<<5)
666 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
667 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
668 #define CM0_COLOR_EVICT_DISABLE (1<<3)
669 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
670 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
671 #define BB_ADDR 0x02140 /* 8 bytes */
672 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
673 #define ECOSKPD 0x021d0
674 #define ECO_GATING_CX_ONLY (1<<3)
675 #define ECO_FLIP_DONE (1<<0)
677 #define CACHE_MODE_1 0x7004 /* IVB+ */
678 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
679 
680 /* GEN6 interrupt control
681  * Note that the per-ring interrupt bits do alias with the global interrupt bits
682  * in GTIMR. */
683 #define GEN6_RENDER_HWSTAM 0x2098
684 #define GEN6_RENDER_IMR 0x20a8
685 #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
686 #define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7)
687 #define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6)
688 #define GEN6_RENDER_L3_PARITY_ERROR (1 << 5)
689 #define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4)
690 #define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3)
691 #define GEN6_RENDER_SYNC_STATUS (1 << 2)
692 #define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1)
693 #define GEN6_RENDER_USER_INTERRUPT (1 << 0)
695 #define GEN6_BLITTER_HWSTAM 0x22098
696 #define GEN6_BLITTER_IMR 0x220a8
697 #define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26)
698 #define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
699 #define GEN6_BLITTER_SYNC_STATUS (1 << 24)
700 #define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
702 #define GEN6_BLITTER_ECOSKPD 0x221d0
703 #define GEN6_BLITTER_LOCK_SHIFT 16
704 #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
706 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
707 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
708 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
709 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
710 #define GEN6_BSD_GO_INDICATOR (1 << 4)
712 #define GEN6_BSD_HWSTAM 0x12098
713 #define GEN6_BSD_IMR 0x120a8
714 #define GEN6_BSD_USER_INTERRUPT (1 << 12)
715 
716 #define GEN6_BSD_RNCID 0x12198
718 #define GEN7_FF_THREAD_MODE 0x20a0
719 #define GEN7_FF_SCHED_MASK 0x0077070
720 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
721 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
722 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
723 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
724 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
725 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
726 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
727 #define GEN7_FF_VS_SCHED_HW (0x0<<12)
728 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
729 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
730 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
731 #define GEN7_FF_DS_SCHED_HW (0x0<<4)
732 
733 /*
734  * Framebuffer compression (915+ only)
735  */
737 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
738 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
739 #define FBC_CONTROL 0x03208
740 #define FBC_CTL_EN (1<<31)
741 #define FBC_CTL_PERIODIC (1<<30)
742 #define FBC_CTL_INTERVAL_SHIFT (16)
743 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
744 #define FBC_CTL_C3_IDLE (1<<13)
745 #define FBC_CTL_STRIDE_SHIFT (5)
746 #define FBC_CTL_FENCENO (1<<0)
747 #define FBC_COMMAND 0x0320c
748 #define FBC_CMD_COMPRESS (1<<0)
749 #define FBC_STATUS 0x03210
750 #define FBC_STAT_COMPRESSING (1<<31)
751 #define FBC_STAT_COMPRESSED (1<<30)
752 #define FBC_STAT_MODIFIED (1<<29)
753 #define FBC_STAT_CURRENT_LINE (1<<0)
754 #define FBC_CONTROL2 0x03214
755 #define FBC_CTL_FENCE_DBL (0<<4)
756 #define FBC_CTL_IDLE_IMM (0<<2)
757 #define FBC_CTL_IDLE_FULL (1<<2)
758 #define FBC_CTL_IDLE_LINE (2<<2)
759 #define FBC_CTL_IDLE_DEBUG (3<<2)
760 #define FBC_CTL_CPU_FENCE (1<<1)
761 #define FBC_CTL_PLANEA (0<<0)
762 #define FBC_CTL_PLANEB (1<<0)
763 #define FBC_FENCE_OFF 0x0321b
764 #define FBC_TAG 0x03300
765 
766 #define FBC_LL_SIZE (1536)
768 /* Framebuffer compression for GM45+ */
769 #define DPFC_CB_BASE 0x3200
770 #define DPFC_CONTROL 0x3208
771 #define DPFC_CTL_EN (1<<31)
772 #define DPFC_CTL_PLANEA (0<<30)
773 #define DPFC_CTL_PLANEB (1<<30)
774 #define DPFC_CTL_FENCE_EN (1<<29)
775 #define DPFC_CTL_PERSISTENT_MODE (1<<25)
776 #define DPFC_SR_EN (1<<10)
777 #define DPFC_CTL_LIMIT_1X (0<<6)
778 #define DPFC_CTL_LIMIT_2X (1<<6)
779 #define DPFC_CTL_LIMIT_4X (2<<6)
780 #define DPFC_RECOMP_CTL 0x320c
781 #define DPFC_RECOMP_STALL_EN (1<<27)
782 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
783 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
784 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
785 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
786 #define DPFC_STATUS 0x3210
787 #define DPFC_INVAL_SEG_SHIFT (16)
788 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
789 #define DPFC_COMP_SEG_SHIFT (0)
790 #define DPFC_COMP_SEG_MASK (0x000003ff)
791 #define DPFC_STATUS2 0x3214
792 #define DPFC_FENCE_YOFF 0x3218
793 #define DPFC_CHICKEN 0x3224
794 #define DPFC_HT_MODIFY (1<<31)
796 /* Framebuffer compression for Ironlake */
797 #define ILK_DPFC_CB_BASE 0x43200
798 #define ILK_DPFC_CONTROL 0x43208
799 /* The bit 28-8 is reserved */
800 #define DPFC_RESERVED (0x1FFFFF00)
801 #define ILK_DPFC_RECOMP_CTL 0x4320c
802 #define ILK_DPFC_STATUS 0x43210
803 #define ILK_DPFC_FENCE_YOFF 0x43218
804 #define ILK_DPFC_CHICKEN 0x43224
805 #define ILK_FBC_RT_BASE 0x2128
806 #define ILK_FBC_RT_VALID (1<<0)
808 #define ILK_DISPLAY_CHICKEN1 0x42000
809 #define ILK_FBCQ_DIS (1<<22)
810 #define ILK_PABSTRETCH_DIS (1<<21)
811 
812 
813 /*
814  * Framebuffer compression for Sandybridge
815  *
816  * The following two registers are of type GTTMMADR
817  */
818 #define SNB_DPFC_CTL_SA 0x100100
819 #define SNB_CPU_FENCE_ENABLE (1<<29)
820 #define DPFC_CPU_FENCE_OFFSET 0x100104
821 
822 
823 /*
824  * GPIO regs
825  */
826 #define GPIOA 0x5010
827 #define GPIOB 0x5014
828 #define GPIOC 0x5018
829 #define GPIOD 0x501c
830 #define GPIOE 0x5020
831 #define GPIOF 0x5024
832 #define GPIOG 0x5028
833 #define GPIOH 0x502c
834 # define GPIO_CLOCK_DIR_MASK (1 << 0)
835 # define GPIO_CLOCK_DIR_IN (0 << 1)
836 # define GPIO_CLOCK_DIR_OUT (1 << 1)
837 # define GPIO_CLOCK_VAL_MASK (1 << 2)
838 # define GPIO_CLOCK_VAL_OUT (1 << 3)
839 # define GPIO_CLOCK_VAL_IN (1 << 4)
840 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
841 # define GPIO_DATA_DIR_MASK (1 << 8)
842 # define GPIO_DATA_DIR_IN (0 << 9)
843 # define GPIO_DATA_DIR_OUT (1 << 9)
844 # define GPIO_DATA_VAL_MASK (1 << 10)
845 # define GPIO_DATA_VAL_OUT (1 << 11)
846 # define GPIO_DATA_VAL_IN (1 << 12)
847 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
849 #define GMBUS0 0x5100 /* clock/port select */
850 #define GMBUS_RATE_100KHZ (0<<8)
851 #define GMBUS_RATE_50KHZ (1<<8)
852 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
853 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
854 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
855 #define GMBUS_PORT_DISABLED 0
856 #define GMBUS_PORT_SSC 1
857 #define GMBUS_PORT_VGADDC 2
858 #define GMBUS_PORT_PANEL 3
859 #define GMBUS_PORT_DPC 4 /* HDMIC */
860 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
861 #define GMBUS_PORT_DPD 6 /* HDMID */
862 #define GMBUS_PORT_RESERVED 7 /* 7 reserved */
863 #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
864 #define GMBUS1 0x5104 /* command/status */
865 #define GMBUS_SW_CLR_INT (1<<31)
866 #define GMBUS_SW_RDY (1<<30)
867 #define GMBUS_ENT (1<<29) /* enable timeout */
868 #define GMBUS_CYCLE_NONE (0<<25)
869 #define GMBUS_CYCLE_WAIT (1<<25)
870 #define GMBUS_CYCLE_INDEX (2<<25)
871 #define GMBUS_CYCLE_STOP (4<<25)
872 #define GMBUS_BYTE_COUNT_SHIFT 16
873 #define GMBUS_SLAVE_INDEX_SHIFT 8
874 #define GMBUS_SLAVE_ADDR_SHIFT 1
875 #define GMBUS_SLAVE_READ (1<<0)
876 #define GMBUS_SLAVE_WRITE (0<<0)
877 #define GMBUS2 0x5108 /* status */
878 #define GMBUS_INUSE (1<<15)
879 #define GMBUS_HW_WAIT_PHASE (1<<14)
880 #define GMBUS_STALL_TIMEOUT (1<<13)
881 #define GMBUS_INT (1<<12)
882 #define GMBUS_HW_RDY (1<<11)
883 #define GMBUS_SATOER (1<<10)
884 #define GMBUS_ACTIVE (1<<9)
885 #define GMBUS3 0x510c /* data buffer bytes 3-0 */
886 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
887 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
888 #define GMBUS_NAK_EN (1<<3)
889 #define GMBUS_IDLE_EN (1<<2)
890 #define GMBUS_HW_WAIT_EN (1<<1)
891 #define GMBUS_HW_RDY_EN (1<<0)
892 #define GMBUS5 0x5120 /* byte index */
893 #define GMBUS_2BYTE_INDEX_EN (1<<31)
894 
895 /*
896  * Clock control & power management
897  */
899 #define VGA0 0x6000
900 #define VGA1 0x6004
901 #define VGA_PD 0x6010
902 #define VGA0_PD_P2_DIV_4 (1 << 7)
903 #define VGA0_PD_P1_DIV_2 (1 << 5)
904 #define VGA0_PD_P1_SHIFT 0
905 #define VGA0_PD_P1_MASK (0x1f << 0)
906 #define VGA1_PD_P2_DIV_4 (1 << 15)
907 #define VGA1_PD_P1_DIV_2 (1 << 13)
908 #define VGA1_PD_P1_SHIFT 8
909 #define VGA1_PD_P1_MASK (0x1f << 8)
910 #define _DPLL_A 0x06014
911 #define _DPLL_B 0x06018
912 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
913 #define DPLL_VCO_ENABLE (1 << 31)
914 #define DPLL_DVO_HIGH_SPEED (1 << 30)
915 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
916 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
917 #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29)
918 #define DPLL_VGA_MODE_DIS (1 << 28)
919 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
920 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
921 #define DPLL_MODE_MASK (3 << 26)
922 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
923 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
924 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
925 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
926 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
927 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
928 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
929 #define DPLL_LOCK_VLV (1<<15)
930 #define DPLL_INTEGRATED_CLOCK_VLV (1<<13)
932 #define SRX_INDEX 0x3c4
933 #define SRX_DATA 0x3c5
934 #define SR01 1
935 #define SR01_SCREEN_OFF (1<<5)
937 #define PPCR 0x61204
938 #define PPCR_ON (1<<0)
940 #define DVOB 0x61140
941 #define DVOB_ON (1<<31)
942 #define DVOC 0x61160
943 #define DVOC_ON (1<<31)
944 #define LVDS 0x61180
945 #define LVDS_ON (1<<31)
946 
947 /* Scratch pad debug 0 reg:
948  */
949 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
950 /*
951  * The i830 generation, in LVDS mode, defines P1 as the bit number set within
952  * this field (only one bit may be set).
953  */
954 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
955 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
956 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
957 /* i830, required in DVO non-gang */
958 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
959 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
960 #define PLL_REF_INPUT_DREFCLK (0 << 13)
961 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
962 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
963 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
964 #define PLL_REF_INPUT_MASK (3 << 13)
965 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
966 /* Ironlake */
967 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
968 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
969 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
970 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
971 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
972 
973 /*
974  * Parallel to Serial Load Pulse phase selection.
975  * Selects the phase for the 10X DPLL clock for the PCIe
976  * digital display port. The range is 4 to 13; 10 or more
977  * is just a flip delay. The default is 6
978  */
979 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
980 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
981 /*
982  * SDVO multiplier for 945G/GM. Not used on 965.
983  */
984 #define SDVO_MULTIPLIER_MASK 0x000000ff
985 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
986 #define SDVO_MULTIPLIER_SHIFT_VGA 0
987 #define _DPLL_A_MD 0x0601c /* 965+ only */
988 /*
989  * UDI pixel divider, controlling how many pixels are stuffed into a packet.
990  *
991  * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
992  */
993 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
994 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
995 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
996 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
997 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
998 /*
999  * SDVO/UDI pixel multiplier.
1000  *
1001  * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1002  * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1003  * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1004  * dummy bytes in the datastream at an increased clock rate, with both sides of
1005  * the link knowing how many bytes are fill.
1006  *
1007  * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1008  * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1009  * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1010  * through an SDVO command.
1011  *
1012  * This register field has values of multiplication factor minus 1, with
1013  * a maximum multiplier of 5 for SDVO.
1014  */
1015 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1016 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1017 /*
1018  * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1019  * This best be set to the default value (3) or the CRT won't work. No,
1020  * I don't entirely understand what this does...
1021  */
1022 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1023 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
1024 #define _DPLL_B_MD 0x06020 /* 965+ only */
1025 #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
1027 #define _FPA0 0x06040
1028 #define _FPA1 0x06044
1029 #define _FPB0 0x06048
1030 #define _FPB1 0x0604c
1031 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
1032 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
1033 #define FP_N_DIV_MASK 0x003f0000
1034 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
1035 #define FP_N_DIV_SHIFT 16
1036 #define FP_M1_DIV_MASK 0x00003f00
1037 #define FP_M1_DIV_SHIFT 8
1038 #define FP_M2_DIV_MASK 0x0000003f
1039 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
1040 #define FP_M2_DIV_SHIFT 0
1041 #define DPLL_TEST 0x606c
1042 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1043 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1044 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1045 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1046 #define DPLLB_TEST_N_BYPASS (1 << 19)
1047 #define DPLLB_TEST_M_BYPASS (1 << 18)
1048 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1049 #define DPLLA_TEST_N_BYPASS (1 << 3)
1050 #define DPLLA_TEST_M_BYPASS (1 << 2)
1051 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1052 #define D_STATE 0x6104
1053 #define DSTATE_GFX_RESET_I830 (1<<6)
1054 #define DSTATE_PLL_D3_OFF (1<<3)
1055 #define DSTATE_GFX_CLOCK_GATING (1<<1)
1056 #define DSTATE_DOT_CLOCK_GATING (1<<0)
1057 #define DSPCLK_GATE_D 0x6200
1058 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1059 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1060 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
1061 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
1062 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
1063 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
1064 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
1065 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
1066 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
1067 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
1068 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
1069 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
1070 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
1071 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
1072 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
1073 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
1074 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
1075 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
1076 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
1077 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1078 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
1079 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
1080 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
1081 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
1082 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
1083 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1084 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
1085 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
1086 
1090 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
1091 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
1092 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
1093 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
1094 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
1096 #define RENCLK_GATE_D1 0x6204
1097 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
1098 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
1099 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
1100 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
1101 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
1102 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
1103 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
1104 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
1105 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
1107 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
1108 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
1109 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
1110 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
1112 # define SV_CLOCK_GATE_DISABLE (1 << 0)
1113 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
1114 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
1115 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
1116 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
1117 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
1118 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
1119 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
1120 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1121 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1122 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1123 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1124 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1125 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1126 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1127 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1128 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1129 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1130 
1131 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
1133 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1134 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1135 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1136 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1137 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1138 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
1140 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1141 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1142 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1143 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1144 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1145 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1146 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1147 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1148 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
1149 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
1150 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
1151 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
1152 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
1153 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
1154 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
1155 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
1156 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
1157 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
1158 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
1160 #define RENCLK_GATE_D2 0x6208
1161 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
1162 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
1163 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
1164 #define RAMCLK_GATE_D 0x6210 /* CRL only */
1165 #define DEUC 0x6214 /* CRL only */
1167 #define FW_BLC_SELF_VLV 0x6500
1168 #define FW_CSPWRDWNEN (1<<15)
1169 
1170 /*
1171  * Palette regs
1172  */
1174 #define _PALETTE_A 0x0a000
1175 #define _PALETTE_B 0x0a800
1176 #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
1177 
1178 /* MCH MMIO space */
1179 
1180 /*
1181  * MCHBAR mirror.
1182  *
1183  * This mirrors the MCHBAR MMIO space whose location is determined by
1184  * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
1185  * every way. It is not accessible from the CP register read instructions.
1186  *
1187  */
1188 #define MCHBAR_MIRROR_BASE 0x10000
1189 
1190 #define MCHBAR_MIRROR_BASE_SNB 0x140000
1193 #define DCC 0x10200
1194 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
1195 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
1196 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
1197 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
1198 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
1199 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
1202 #define CSHRDDR3CTL 0x101a8
1203 #define CSHRDDR3CTL_DDR3 (1 << 2)
1206 #define C0DRB3 0x10206
1207 #define C1DRB3 0x10606
1210 #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
1211 #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
1212 #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
1213 #define MAD_DIMM_ECC_MASK (0x3 << 24)
1214 #define MAD_DIMM_ECC_OFF (0x0 << 24)
1215 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
1216 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
1217 #define MAD_DIMM_ECC_ON (0x3 << 24)
1218 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
1219 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
1220 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
1221 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
1222 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
1223 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
1224 #define MAD_DIMM_A_SELECT (0x1 << 16)
1225 /* DIMM sizes are in multiples of 256mb. */
1226 #define MAD_DIMM_B_SIZE_SHIFT 8
1227 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
1228 #define MAD_DIMM_A_SIZE_SHIFT 0
1229 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
1230 
1232 /* Clocking configuration register */
1233 #define CLKCFG 0x10c00
1234 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
1235 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
1236 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
1237 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
1238 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
1239 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
1240 /* Note, below two are guess */
1241 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
1242 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
1243 #define CLKCFG_FSB_MASK (7 << 0)
1244 #define CLKCFG_MEM_533 (1 << 4)
1245 #define CLKCFG_MEM_667 (2 << 4)
1246 #define CLKCFG_MEM_800 (3 << 4)
1247 #define CLKCFG_MEM_MASK (7 << 4)
1249 #define TSC1 0x11001
1250 #define TSE (1<<0)
1251 #define TR1 0x11006
1252 #define TSFS 0x11020
1253 #define TSFS_SLOPE_MASK 0x0000ff00
1254 #define TSFS_SLOPE_SHIFT 8
1255 #define TSFS_INTR_MASK 0x000000ff
1257 #define CRSTANDVID 0x11100
1258 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1259 #define PXVFREQ_PX_MASK 0x7f000000
1260 #define PXVFREQ_PX_SHIFT 24
1261 #define VIDFREQ_BASE 0x11110
1262 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1263 #define VIDFREQ2 0x11114
1264 #define VIDFREQ3 0x11118
1265 #define VIDFREQ4 0x1111c
1266 #define VIDFREQ_P0_MASK 0x1f000000
1267 #define VIDFREQ_P0_SHIFT 24
1268 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
1269 #define VIDFREQ_P0_CSCLK_SHIFT 20
1270 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
1271 #define VIDFREQ_P0_CRCLK_SHIFT 16
1272 #define VIDFREQ_P1_MASK 0x00001f00
1273 #define VIDFREQ_P1_SHIFT 8
1274 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
1275 #define VIDFREQ_P1_CSCLK_SHIFT 4
1276 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
1277 #define INTTOEXT_BASE_ILK 0x11300
1278 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
1279 #define INTTOEXT_MAP3_SHIFT 24
1280 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
1281 #define INTTOEXT_MAP2_SHIFT 16
1282 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
1283 #define INTTOEXT_MAP1_SHIFT 8
1284 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
1285 #define INTTOEXT_MAP0_SHIFT 0
1286 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
1287 #define MEMSWCTL 0x11170 /* Ironlake only */
1288 #define MEMCTL_CMD_MASK 0xe000
1289 #define MEMCTL_CMD_SHIFT 13
1290 #define MEMCTL_CMD_RCLK_OFF 0
1291 #define MEMCTL_CMD_RCLK_ON 1
1292 #define MEMCTL_CMD_CHFREQ 2
1293 #define MEMCTL_CMD_CHVID 3
1294 #define MEMCTL_CMD_VMMOFF 4
1295 #define MEMCTL_CMD_VMMON 5
1296 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
1297  when command complete */
1298 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
1299 #define MEMCTL_FREQ_SHIFT 8
1300 #define MEMCTL_SFCAVM (1<<7)
1301 #define MEMCTL_TGT_VID_MASK 0x007f
1302 #define MEMIHYST 0x1117c
1303 #define MEMINTREN 0x11180 /* 16 bits */
1304 #define MEMINT_RSEXIT_EN (1<<8)
1305 #define MEMINT_CX_SUPR_EN (1<<7)
1306 #define MEMINT_CONT_BUSY_EN (1<<6)
1307 #define MEMINT_AVG_BUSY_EN (1<<5)
1308 #define MEMINT_EVAL_CHG_EN (1<<4)
1309 #define MEMINT_MON_IDLE_EN (1<<3)
1310 #define MEMINT_UP_EVAL_EN (1<<2)
1311 #define MEMINT_DOWN_EVAL_EN (1<<1)
1312 #define MEMINT_SW_CMD_EN (1<<0)
1313 #define MEMINTRSTR 0x11182 /* 16 bits */
1314 #define MEM_RSEXIT_MASK 0xc000
1315 #define MEM_RSEXIT_SHIFT 14
1316 #define MEM_CONT_BUSY_MASK 0x3000
1317 #define MEM_CONT_BUSY_SHIFT 12
1318 #define MEM_AVG_BUSY_MASK 0x0c00
1319 #define MEM_AVG_BUSY_SHIFT 10
1320 #define MEM_EVAL_CHG_MASK 0x0300
1321 #define MEM_EVAL_BUSY_SHIFT 8
1322 #define MEM_MON_IDLE_MASK 0x00c0
1323 #define MEM_MON_IDLE_SHIFT 6
1324 #define MEM_UP_EVAL_MASK 0x0030
1325 #define MEM_UP_EVAL_SHIFT 4
1326 #define MEM_DOWN_EVAL_MASK 0x000c
1327 #define MEM_DOWN_EVAL_SHIFT 2
1328 #define MEM_SW_CMD_MASK 0x0003
1329 #define MEM_INT_STEER_GFX 0
1330 #define MEM_INT_STEER_CMR 1
1331 #define MEM_INT_STEER_SMI 2
1332 #define MEM_INT_STEER_SCI 3
1333 #define MEMINTRSTS 0x11184
1334 #define MEMINT_RSEXIT (1<<7)
1335 #define MEMINT_CONT_BUSY (1<<6)
1336 #define MEMINT_AVG_BUSY (1<<5)
1337 #define MEMINT_EVAL_CHG (1<<4)
1338 #define MEMINT_MON_IDLE (1<<3)
1339 #define MEMINT_UP_EVAL (1<<2)
1340 #define MEMINT_DOWN_EVAL (1<<1)
1341 #define MEMINT_SW_CMD (1<<0)
1342 #define MEMMODECTL 0x11190
1343 #define MEMMODE_BOOST_EN (1<<31)
1344 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1345 #define MEMMODE_BOOST_FREQ_SHIFT 24
1346 #define MEMMODE_IDLE_MODE_MASK 0x00030000
1347 #define MEMMODE_IDLE_MODE_SHIFT 16
1348 #define MEMMODE_IDLE_MODE_EVAL 0
1349 #define MEMMODE_IDLE_MODE_CONT 1
1350 #define MEMMODE_HWIDLE_EN (1<<15)
1351 #define MEMMODE_SWMODE_EN (1<<14)
1352 #define MEMMODE_RCLK_GATE (1<<13)
1353 #define MEMMODE_HW_UPDATE (1<<12)
1354 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
1355 #define MEMMODE_FSTART_SHIFT 8
1356 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
1357 #define MEMMODE_FMAX_SHIFT 4
1358 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
1359 #define RCBMAXAVG 0x1119c
1360 #define MEMSWCTL2 0x1119e /* Cantiga only */
1361 #define SWMEMCMD_RENDER_OFF (0 << 13)
1362 #define SWMEMCMD_RENDER_ON (1 << 13)
1363 #define SWMEMCMD_SWFREQ (2 << 13)
1364 #define SWMEMCMD_TARVID (3 << 13)
1365 #define SWMEMCMD_VRM_OFF (4 << 13)
1366 #define SWMEMCMD_VRM_ON (5 << 13)
1367 #define CMDSTS (1<<12)
1368 #define SFCAVM (1<<11)
1369 #define SWFREQ_MASK 0x0380 /* P0-7 */
1370 #define SWFREQ_SHIFT 7
1371 #define TARVID_MASK 0x001f
1372 #define MEMSTAT_CTG 0x111a0
1373 #define RCBMINAVG 0x111a0
1374 #define RCUPEI 0x111b0
1375 #define RCDNEI 0x111b4
1376 #define RSTDBYCTL 0x111b8
1377 #define RS1EN (1<<31)
1378 #define RS2EN (1<<30)
1379 #define RS3EN (1<<29)
1380 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
1381 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
1382 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
1383 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
1384 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
1385 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
1386 #define RSX_STATUS_MASK (7<<20)
1387 #define RSX_STATUS_ON (0<<20)
1388 #define RSX_STATUS_RC1 (1<<20)
1389 #define RSX_STATUS_RC1E (2<<20)
1390 #define RSX_STATUS_RS1 (3<<20)
1391 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
1392 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
1393 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
1394 #define RSX_STATUS_RSVD2 (7<<20)
1395 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
1396 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
1397 #define JRSC (1<<17) /* rsx coupled to cpu c-state */
1398 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
1399 #define RS1CONTSAV_MASK (3<<14)
1400 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
1401 #define RS1CONTSAV_RSVD (1<<14)
1402 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
1403 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
1404 #define NORMSLEXLAT_MASK (3<<12)
1405 #define SLOW_RS123 (0<<12)
1406 #define SLOW_RS23 (1<<12)
1407 #define SLOW_RS3 (2<<12)
1408 #define NORMAL_RS123 (3<<12)
1409 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
1410 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1411 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
1412 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
1413 #define RS_CSTATE_MASK (3<<4)
1414 #define RS_CSTATE_C367_RS1 (0<<4)
1415 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1416 #define RS_CSTATE_RSVD (2<<4)
1417 #define RS_CSTATE_C367_RS2 (3<<4)
1418 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */
1419 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
1420 #define VIDCTL 0x111c0
1421 #define VIDSTS 0x111c8
1422 #define VIDSTART 0x111cc /* 8 bits */
1423 #define MEMSTAT_ILK 0x111f8
1424 #define MEMSTAT_VID_MASK 0x7f00
1425 #define MEMSTAT_VID_SHIFT 8
1426 #define MEMSTAT_PSTATE_MASK 0x00f8
1427 #define MEMSTAT_PSTATE_SHIFT 3
1428 #define MEMSTAT_MON_ACTV (1<<2)
1429 #define MEMSTAT_SRC_CTL_MASK 0x0003
1430 #define MEMSTAT_SRC_CTL_CORE 0
1431 #define MEMSTAT_SRC_CTL_TRB 1
1432 #define MEMSTAT_SRC_CTL_THM 2
1433 #define MEMSTAT_SRC_CTL_STDBY 3
1434 #define RCPREVBSYTUPAVG 0x113b8
1435 #define RCPREVBSYTDNAVG 0x113bc
1436 #define PMMISC 0x11214
1437 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
1438 #define SDEW 0x1124c
1439 #define CSIEW0 0x11250
1440 #define CSIEW1 0x11254
1441 #define CSIEW2 0x11258
1442 #define PEW 0x1125c
1443 #define DEW 0x11270
1444 #define MCHAFE 0x112c0
1445 #define CSIEC 0x112e0
1446 #define DMIEC 0x112e4
1447 #define DDREC 0x112e8
1448 #define PEG0EC 0x112ec
1449 #define PEG1EC 0x112f0
1450 #define GFXEC 0x112f4
1451 #define RPPREVBSYTUPAVG 0x113b8
1452 #define RPPREVBSYTDNAVG 0x113bc
1453 #define ECR 0x11600
1454 #define ECR_GPFE (1<<31)
1455 #define ECR_IMONE (1<<30)
1456 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
1457 #define OGW0 0x11608
1458 #define OGW1 0x1160c
1459 #define EG0 0x11610
1460 #define EG1 0x11614
1461 #define EG2 0x11618
1462 #define EG3 0x1161c
1463 #define EG4 0x11620
1464 #define EG5 0x11624
1465 #define EG6 0x11628
1466 #define EG7 0x1162c
1467 #define PXW 0x11664
1468 #define PXWL 0x11680
1469 #define LCFUSE02 0x116c0
1470 #define LCFUSE_HIV_MASK 0x000000ff
1471 #define CSIPLL0 0x12c10
1472 #define DDRMPLL1 0X12c20
1473 #define PEG_BAND_GAP_DATA 0x14d68
1475 #define GEN6_GT_THREAD_STATUS_REG 0x13805c
1476 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
1477 #define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
1479 #define GEN6_GT_PERF_STATUS 0x145948
1480 #define GEN6_RP_STATE_LIMITS 0x145994
1481 #define GEN6_RP_STATE_CAP 0x145998
1482 
1483 /*
1484  * Logical Context regs
1485  */
1486 #define CCID 0x2180
1487 #define CCID_EN (1<<0)
1488 #define CXT_SIZE 0x21a0
1489 #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
1490 #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
1491 #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
1492 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
1493 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
1494 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_POWER_SIZE(cxt_reg) + \
1495  GEN6_CXT_RING_SIZE(cxt_reg) + \
1496  GEN6_CXT_RENDER_SIZE(cxt_reg) + \
1497  GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
1498  GEN6_CXT_PIPELINE_SIZE(cxt_reg))
1499 #define GEN7_CXT_SIZE 0x21a8
1500 #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f)
1501 #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7)
1502 #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f)
1503 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
1504 #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
1505 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
1506 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_POWER_SIZE(ctx_reg) + \
1507  GEN7_CXT_RING_SIZE(ctx_reg) + \
1508  GEN7_CXT_RENDER_SIZE(ctx_reg) + \
1509  GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
1510  GEN7_CXT_GT1_SIZE(ctx_reg) + \
1511  GEN7_CXT_VFSTATE_SIZE(ctx_reg))
1512 #define HSW_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 26) & 0x3f)
1513 #define HSW_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 23) & 0x7)
1514 #define HSW_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 15) & 0xff)
1515 #define HSW_CXT_TOTAL_SIZE(ctx_reg) (HSW_CXT_POWER_SIZE(ctx_reg) + \
1516  HSW_CXT_RING_SIZE(ctx_reg) + \
1517  HSW_CXT_RENDER_SIZE(ctx_reg) + \
1518  GEN7_CXT_VFSTATE_SIZE(ctx_reg))
1519 
1520 
1521 /*
1522  * Overlay regs
1523  */
1525 #define OVADD 0x30000
1526 #define DOVSTA 0x30008
1527 #define OC_BUF (0x3<<20)
1528 #define OGAMC5 0x30010
1529 #define OGAMC4 0x30014
1530 #define OGAMC3 0x30018
1531 #define OGAMC2 0x3001c
1532 #define OGAMC1 0x30020
1533 #define OGAMC0 0x30024
1534 
1535 /*
1536  * Display engine regs
1537  */
1539 /* Pipe A timing regs */
1540 #define _HTOTAL_A 0x60000
1541 #define _HBLANK_A 0x60004
1542 #define _HSYNC_A 0x60008
1543 #define _VTOTAL_A 0x6000c
1544 #define _VBLANK_A 0x60010
1545 #define _VSYNC_A 0x60014
1546 #define _PIPEASRC 0x6001c
1547 #define _BCLRPAT_A 0x60020
1548 #define _VSYNCSHIFT_A 0x60028
1550 /* Pipe B timing regs */
1551 #define _HTOTAL_B 0x61000
1552 #define _HBLANK_B 0x61004
1553 #define _HSYNC_B 0x61008
1554 #define _VTOTAL_B 0x6100c
1555 #define _VBLANK_B 0x61010
1556 #define _VSYNC_B 0x61014
1557 #define _PIPEBSRC 0x6101c
1558 #define _BCLRPAT_B 0x61020
1559 #define _VSYNCSHIFT_B 0x61028
1562 #define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
1563 #define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
1564 #define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
1565 #define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
1566 #define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
1567 #define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
1568 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
1569 #define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
1571 /* VGA port control */
1572 #define ADPA 0x61100
1573 #define PCH_ADPA 0xe1100
1574 #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
1576 #define ADPA_DAC_ENABLE (1<<31)
1577 #define ADPA_DAC_DISABLE 0
1578 #define ADPA_PIPE_SELECT_MASK (1<<30)
1579 #define ADPA_PIPE_A_SELECT 0
1580 #define ADPA_PIPE_B_SELECT (1<<30)
1581 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
1582 /* CPT uses bits 29:30 for pch transcoder select */
1583 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
1584 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
1585 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
1586 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
1587 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
1588 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
1589 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
1590 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
1591 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
1592 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
1593 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
1594 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
1595 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
1596 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
1597 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
1598 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
1599 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
1600 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
1601 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
1602 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
1603 #define ADPA_SETS_HVPOLARITY 0
1604 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1605 #define ADPA_VSYNC_CNTL_ENABLE 0
1606 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1607 #define ADPA_HSYNC_CNTL_ENABLE 0
1608 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1609 #define ADPA_VSYNC_ACTIVE_LOW 0
1610 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1611 #define ADPA_HSYNC_ACTIVE_LOW 0
1612 #define ADPA_DPMS_MASK (~(3<<10))
1613 #define ADPA_DPMS_ON (0<<10)
1614 #define ADPA_DPMS_SUSPEND (1<<10)
1615 #define ADPA_DPMS_STANDBY (2<<10)
1616 #define ADPA_DPMS_OFF (3<<10)
1619 /* Hotplug control (945+ only) */
1620 #define PORT_HOTPLUG_EN 0x61110
1621 #define HDMIB_HOTPLUG_INT_EN (1 << 29)
1622 #define DPB_HOTPLUG_INT_EN (1 << 29)
1623 #define HDMIC_HOTPLUG_INT_EN (1 << 28)
1624 #define DPC_HOTPLUG_INT_EN (1 << 28)
1625 #define HDMID_HOTPLUG_INT_EN (1 << 27)
1626 #define DPD_HOTPLUG_INT_EN (1 << 27)
1627 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
1628 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
1629 #define TV_HOTPLUG_INT_EN (1 << 18)
1630 #define CRT_HOTPLUG_INT_EN (1 << 9)
1631 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1632 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1633 /* must use period 64 on GM45 according to docs */
1634 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1635 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1636 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1637 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1638 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1639 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1640 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1641 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1642 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1643 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1644 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1645 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
1647 #define PORT_HOTPLUG_STAT 0x61114
1648 /* HDMI/DP bits are gen4+ */
1649 #define DPB_HOTPLUG_LIVE_STATUS (1 << 29)
1650 #define DPC_HOTPLUG_LIVE_STATUS (1 << 28)
1651 #define DPD_HOTPLUG_LIVE_STATUS (1 << 27)
1652 #define DPD_HOTPLUG_INT_STATUS (3 << 21)
1653 #define DPC_HOTPLUG_INT_STATUS (3 << 19)
1654 #define DPB_HOTPLUG_INT_STATUS (3 << 17)
1655 /* HDMI bits are shared with the DP bits */
1656 #define HDMIB_HOTPLUG_LIVE_STATUS (1 << 29)
1657 #define HDMIC_HOTPLUG_LIVE_STATUS (1 << 28)
1658 #define HDMID_HOTPLUG_LIVE_STATUS (1 << 27)
1659 #define HDMID_HOTPLUG_INT_STATUS (3 << 21)
1660 #define HDMIC_HOTPLUG_INT_STATUS (3 << 19)
1661 #define HDMIB_HOTPLUG_INT_STATUS (3 << 17)
1662 /* CRT/TV common between gen3+ */
1663 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
1664 #define TV_HOTPLUG_INT_STATUS (1 << 10)
1665 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1666 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1667 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1668 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1669 /* SDVO is different across gen3/4 */
1670 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
1671 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
1672 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
1673 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
1674 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
1675 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
1677 /* SDVO port control */
1678 #define SDVOB 0x61140
1679 #define SDVOC 0x61160
1680 #define SDVO_ENABLE (1 << 31)
1681 #define SDVO_PIPE_B_SELECT (1 << 30)
1682 #define SDVO_STALL_SELECT (1 << 29)
1683 #define SDVO_INTERRUPT_ENABLE (1 << 26)
1684 
1691 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1692 #define SDVO_PORT_MULTIPLY_SHIFT 23
1693 #define SDVO_PHASE_SELECT_MASK (15 << 19)
1694 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1695 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1696 #define SDVOC_GANG_MODE (1 << 16)
1697 #define SDVO_ENCODING_SDVO (0x0 << 10)
1698 #define SDVO_ENCODING_HDMI (0x2 << 10)
1700 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
1701 #define SDVO_COLOR_RANGE_16_235 (1 << 8)
1702 #define SDVO_BORDER_ENABLE (1 << 7)
1703 #define SDVO_AUDIO_ENABLE (1 << 6)
1705 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1707 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
1708 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
1709 #define SDVO_DETECTED (1 << 2)
1710 /* Bits to be preserved when writing */
1711 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
1712 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
1714 /* DVO port control */
1715 #define DVOA 0x61120
1716 #define DVOB 0x61140
1717 #define DVOC 0x61160
1718 #define DVO_ENABLE (1 << 31)
1719 #define DVO_PIPE_B_SELECT (1 << 30)
1720 #define DVO_PIPE_STALL_UNUSED (0 << 28)
1721 #define DVO_PIPE_STALL (1 << 28)
1722 #define DVO_PIPE_STALL_TV (2 << 28)
1723 #define DVO_PIPE_STALL_MASK (3 << 28)
1724 #define DVO_USE_VGA_SYNC (1 << 15)
1725 #define DVO_DATA_ORDER_I740 (0 << 14)
1726 #define DVO_DATA_ORDER_FP (1 << 14)
1727 #define DVO_VSYNC_DISABLE (1 << 11)
1728 #define DVO_HSYNC_DISABLE (1 << 10)
1729 #define DVO_VSYNC_TRISTATE (1 << 9)
1730 #define DVO_HSYNC_TRISTATE (1 << 8)
1731 #define DVO_BORDER_ENABLE (1 << 7)
1732 #define DVO_DATA_ORDER_GBRG (1 << 6)
1733 #define DVO_DATA_ORDER_RGGB (0 << 6)
1734 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
1735 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
1736 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
1737 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
1738 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
1739 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
1740 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
1741 #define DVO_PRESERVE_MASK (0x7<<24)
1742 #define DVOA_SRCDIM 0x61124
1743 #define DVOB_SRCDIM 0x61144
1744 #define DVOC_SRCDIM 0x61164
1745 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
1746 #define DVO_SRCDIM_VERTICAL_SHIFT 0
1747 
1748 /* LVDS port control */
1749 #define LVDS 0x61180
1750 /*
1751  * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1752  * the DPLL semantics change when the LVDS is assigned to that pipe.
1753  */
1754 #define LVDS_PORT_EN (1 << 31)
1755 /* Selects pipe B for LVDS data. Must be set on pre-965. */
1756 #define LVDS_PIPEB_SELECT (1 << 30)
1757 #define LVDS_PIPE_MASK (1 << 30)
1758 #define LVDS_PIPE(pipe) ((pipe) << 30)
1759 /* LVDS dithering flag on 965/g4x platform */
1760 #define LVDS_ENABLE_DITHER (1 << 25)
1761 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
1762 #define LVDS_VSYNC_POLARITY (1 << 21)
1763 #define LVDS_HSYNC_POLARITY (1 << 20)
1764 
1765 /* Enable border for unscaled (or aspect-scaled) display */
1766 #define LVDS_BORDER_ENABLE (1 << 15)
1767 /*
1768  * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1769  * pixel.
1770  */
1771 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1772 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1773 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1774 /*
1775  * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1776  * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1777  * on.
1778  */
1779 #define LVDS_A3_POWER_MASK (3 << 6)
1780 #define LVDS_A3_POWER_DOWN (0 << 6)
1781 #define LVDS_A3_POWER_UP (3 << 6)
1782 /*
1783  * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1784  * is set.
1785  */
1786 #define LVDS_CLKB_POWER_MASK (3 << 4)
1787 #define LVDS_CLKB_POWER_DOWN (0 << 4)
1788 #define LVDS_CLKB_POWER_UP (3 << 4)
1789 /*
1790  * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1791  * setting for whether we are in dual-channel mode. The B3 pair will
1792  * additionally only be powered up when LVDS_A3_POWER_UP is set.
1793  */
1794 #define LVDS_B0B3_POWER_MASK (3 << 2)
1795 #define LVDS_B0B3_POWER_DOWN (0 << 2)
1796 #define LVDS_B0B3_POWER_UP (3 << 2)
1797 
1798 /* Video Data Island Packet control */
1799 #define VIDEO_DIP_DATA 0x61178
1800 /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
1801  * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
1802  * of the infoframe structure specified by CEA-861. */
1803 #define VIDEO_DIP_DATA_SIZE 32
1804 #define VIDEO_DIP_CTL 0x61170
1805 /* Pre HSW: */
1806 #define VIDEO_DIP_ENABLE (1 << 31)
1807 #define VIDEO_DIP_PORT_B (1 << 29)
1808 #define VIDEO_DIP_PORT_C (2 << 29)
1809 #define VIDEO_DIP_PORT_D (3 << 29)
1810 #define VIDEO_DIP_PORT_MASK (3 << 29)
1811 #define VIDEO_DIP_ENABLE_GCP (1 << 25)
1812 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
1813 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
1814 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
1815 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
1816 #define VIDEO_DIP_SELECT_AVI (0 << 19)
1817 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
1818 #define VIDEO_DIP_SELECT_SPD (3 << 19)
1819 #define VIDEO_DIP_SELECT_MASK (3 << 19)
1820 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
1821 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
1822 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
1823 #define VIDEO_DIP_FREQ_MASK (3 << 16)
1824 /* HSW and later: */
1825 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
1826 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
1827 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
1828 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
1829 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
1830 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
1832 /* Panel power sequencing */
1833 #define PP_STATUS 0x61200
1834 #define PP_ON (1 << 31)
1835 /*
1836  * Indicates that all dependencies of the panel are on:
1837  *
1838  * - PLL enabled
1839  * - pipe enabled
1840  * - LVDS/DVOB/DVOC on
1841  */
1842 #define PP_READY (1 << 30)
1843 #define PP_SEQUENCE_NONE (0 << 28)
1844 #define PP_SEQUENCE_POWER_UP (1 << 28)
1845 #define PP_SEQUENCE_POWER_DOWN (2 << 28)
1846 #define PP_SEQUENCE_MASK (3 << 28)
1847 #define PP_SEQUENCE_SHIFT 28
1848 #define PP_CYCLE_DELAY_ACTIVE (1 << 27)
1849 #define PP_SEQUENCE_STATE_MASK 0x0000000f
1850 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
1851 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
1852 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
1853 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
1854 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
1855 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
1856 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
1857 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
1858 #define PP_SEQUENCE_STATE_RESET (0xf << 0)
1859 #define PP_CONTROL 0x61204
1860 #define POWER_TARGET_ON (1 << 0)
1861 #define PP_ON_DELAYS 0x61208
1862 #define PP_OFF_DELAYS 0x6120c
1863 #define PP_DIVISOR 0x61210
1865 /* Panel fitting */
1866 #define PFIT_CONTROL 0x61230
1867 #define PFIT_ENABLE (1 << 31)
1868 #define PFIT_PIPE_MASK (3 << 29)
1869 #define PFIT_PIPE_SHIFT 29
1870 #define VERT_INTERP_DISABLE (0 << 10)
1871 #define VERT_INTERP_BILINEAR (1 << 10)
1872 #define VERT_INTERP_MASK (3 << 10)
1873 #define VERT_AUTO_SCALE (1 << 9)
1874 #define HORIZ_INTERP_DISABLE (0 << 6)
1875 #define HORIZ_INTERP_BILINEAR (1 << 6)
1876 #define HORIZ_INTERP_MASK (3 << 6)
1877 #define HORIZ_AUTO_SCALE (1 << 5)
1878 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
1879 #define PFIT_FILTER_FUZZY (0 << 24)
1880 #define PFIT_SCALING_AUTO (0 << 26)
1881 #define PFIT_SCALING_PROGRAMMED (1 << 26)
1882 #define PFIT_SCALING_PILLAR (2 << 26)
1883 #define PFIT_SCALING_LETTER (3 << 26)
1884 #define PFIT_PGM_RATIOS 0x61234
1885 #define PFIT_VERT_SCALE_MASK 0xfff00000
1886 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1887 /* Pre-965 */
1888 #define PFIT_VERT_SCALE_SHIFT 20
1889 #define PFIT_VERT_SCALE_MASK 0xfff00000
1890 #define PFIT_HORIZ_SCALE_SHIFT 4
1891 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1892 /* 965+ */
1893 #define PFIT_VERT_SCALE_SHIFT_965 16
1894 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
1895 #define PFIT_HORIZ_SCALE_SHIFT_965 0
1896 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
1897 
1898 #define PFIT_AUTO_RATIOS 0x61238
1900 /* Backlight control */
1901 #define BLC_PWM_CTL2 0x61250 /* 965+ only */
1902 #define BLM_PWM_ENABLE (1 << 31)
1903 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
1904 #define BLM_PIPE_SELECT (1 << 29)
1905 #define BLM_PIPE_SELECT_IVB (3 << 29)
1906 #define BLM_PIPE_A (0 << 29)
1907 #define BLM_PIPE_B (1 << 29)
1908 #define BLM_PIPE_C (2 << 29) /* ivb + */
1909 #define BLM_PIPE(pipe) ((pipe) << 29)
1910 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
1911 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
1912 #define BLM_PHASE_IN_ENABLE (1 << 25)
1913 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
1914 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
1915 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
1916 #define BLM_PHASE_IN_COUNT_SHIFT (8)
1917 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
1918 #define BLM_PHASE_IN_INCR_SHIFT (0)
1919 #define BLM_PHASE_IN_INCR_MASK (0xff << 0)
1920 #define BLC_PWM_CTL 0x61254
1921 /*
1922  * This is the most significant 15 bits of the number of backlight cycles in a
1923  * complete cycle of the modulated backlight control.
1924  *
1925  * The actual value is this field multiplied by two.
1926  */
1927 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
1928 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
1929 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
1930 /*
1931  * This is the number of cycles out of the backlight modulation cycle for which
1932  * the backlight is on.
1933  *
1934  * This field must be no greater than the number of cycles in the complete
1935  * backlight modulation cycle.
1936  */
1937 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1938 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1939 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
1940 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
1941 
1942 #define BLC_HIST_CTL 0x61260
1944 /* New registers for PCH-split platforms. Safe where new bits show up, the
1945  * register layout machtes with gen4 BLC_PWM_CTL[12]. */
1946 #define BLC_PWM_CPU_CTL2 0x48250
1947 #define BLC_PWM_CPU_CTL 0x48254
1949 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
1950  * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
1951 #define BLC_PWM_PCH_CTL1 0xc8250
1952 #define BLM_PCH_PWM_ENABLE (1 << 31)
1953 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
1954 #define BLM_PCH_POLARITY (1 << 29)
1955 #define BLC_PWM_PCH_CTL2 0xc8254
1956 
1957 /* TV port control */
1958 #define TV_CTL 0x68000
1960 # define TV_ENC_ENABLE (1 << 31)
1962 # define TV_ENC_PIPEB_SELECT (1 << 30)
1964 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
1966 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
1968 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
1969 
1970 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
1971 # define TV_TRILEVEL_SYNC (1 << 21)
1973 # define TV_SLOW_SYNC (1 << 20)
1975 # define TV_OVERSAMPLE_4X (0 << 18)
1977 # define TV_OVERSAMPLE_2X (1 << 18)
1979 # define TV_OVERSAMPLE_NONE (2 << 18)
1981 # define TV_OVERSAMPLE_8X (3 << 18)
1983 # define TV_PROGRESSIVE (1 << 17)
1985 # define TV_PAL_BURST (1 << 16)
1987 # define TV_YC_SKEW_MASK (7 << 12)
1988 
1989 # define TV_ENC_SDP_FIX (1 << 11)
1990 
1995 # define TV_ENC_C0_FIX (1 << 10)
1996 
1997 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
1998 # define TV_FUSE_STATE_MASK (3 << 4)
2000 # define TV_FUSE_STATE_ENABLED (0 << 4)
2002 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
2004 # define TV_FUSE_STATE_DISABLED (2 << 4)
2006 # define TV_TEST_MODE_NORMAL (0 << 0)
2008 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
2010 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
2012 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
2014 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
2015 
2016 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
2017 
2022 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
2023 # define TV_TEST_MODE_MASK (7 << 0)
2024 
2025 #define TV_DAC 0x68004
2026 # define TV_DAC_SAVE 0x00ffff00
2027 
2032 # define TVDAC_STATE_CHG (1 << 31)
2033 # define TVDAC_SENSE_MASK (7 << 28)
2035 # define TVDAC_A_SENSE (1 << 30)
2037 # define TVDAC_B_SENSE (1 << 29)
2038 
2039 # define TVDAC_C_SENSE (1 << 28)
2040 
2046 # define TVDAC_STATE_CHG_EN (1 << 27)
2048 # define TVDAC_A_SENSE_CTL (1 << 26)
2050 # define TVDAC_B_SENSE_CTL (1 << 25)
2052 # define TVDAC_C_SENSE_CTL (1 << 24)
2054 # define DAC_CTL_OVERRIDE (1 << 7)
2056 # define ENC_TVDAC_SLEW_FAST (1 << 6)
2057 # define DAC_A_1_3_V (0 << 4)
2058 # define DAC_A_1_1_V (1 << 4)
2059 # define DAC_A_0_7_V (2 << 4)
2060 # define DAC_A_MASK (3 << 4)
2061 # define DAC_B_1_3_V (0 << 2)
2062 # define DAC_B_1_1_V (1 << 2)
2063 # define DAC_B_0_7_V (2 << 2)
2064 # define DAC_B_MASK (3 << 2)
2065 # define DAC_C_1_3_V (0 << 0)
2066 # define DAC_C_1_1_V (1 << 0)
2067 # define DAC_C_0_7_V (2 << 0)
2068 # define DAC_C_MASK (3 << 0)
2069 
2076 #define TV_CSC_Y 0x68010
2077 # define TV_RY_MASK 0x07ff0000
2078 # define TV_RY_SHIFT 16
2079 # define TV_GY_MASK 0x00000fff
2080 # define TV_GY_SHIFT 0
2082 #define TV_CSC_Y2 0x68014
2083 # define TV_BY_MASK 0x07ff0000
2084 # define TV_BY_SHIFT 16
2085 
2090 # define TV_AY_MASK 0x000003ff
2091 # define TV_AY_SHIFT 0
2093 #define TV_CSC_U 0x68018
2094 # define TV_RU_MASK 0x07ff0000
2095 # define TV_RU_SHIFT 16
2096 # define TV_GU_MASK 0x000007ff
2097 # define TV_GU_SHIFT 0
2099 #define TV_CSC_U2 0x6801c
2100 # define TV_BU_MASK 0x07ff0000
2101 # define TV_BU_SHIFT 16
2102 
2107 # define TV_AU_MASK 0x000003ff
2108 # define TV_AU_SHIFT 0
2110 #define TV_CSC_V 0x68020
2111 # define TV_RV_MASK 0x0fff0000
2112 # define TV_RV_SHIFT 16
2113 # define TV_GV_MASK 0x000007ff
2114 # define TV_GV_SHIFT 0
2116 #define TV_CSC_V2 0x68024
2117 # define TV_BV_MASK 0x07ff0000
2118 # define TV_BV_SHIFT 16
2119 
2124 # define TV_AV_MASK 0x000007ff
2125 # define TV_AV_SHIFT 0
2127 #define TV_CLR_KNOBS 0x68028
2128 
2129 # define TV_BRIGHTNESS_MASK 0xff000000
2130 # define TV_BRIGHTNESS_SHIFT 24
2131 
2132 # define TV_CONTRAST_MASK 0x00ff0000
2133 # define TV_CONTRAST_SHIFT 16
2134 
2135 # define TV_SATURATION_MASK 0x0000ff00
2136 # define TV_SATURATION_SHIFT 8
2137 
2138 # define TV_HUE_MASK 0x000000ff
2139 # define TV_HUE_SHIFT 0
2141 #define TV_CLR_LEVEL 0x6802c
2142 
2143 # define TV_BLACK_LEVEL_MASK 0x01ff0000
2144 # define TV_BLACK_LEVEL_SHIFT 16
2145 
2146 # define TV_BLANK_LEVEL_MASK 0x000001ff
2147 # define TV_BLANK_LEVEL_SHIFT 0
2149 #define TV_H_CTL_1 0x68030
2150 
2151 # define TV_HSYNC_END_MASK 0x1fff0000
2152 # define TV_HSYNC_END_SHIFT 16
2153 
2154 # define TV_HTOTAL_MASK 0x00001fff
2155 # define TV_HTOTAL_SHIFT 0
2157 #define TV_H_CTL_2 0x68034
2159 # define TV_BURST_ENA (1 << 31)
2160 
2161 # define TV_HBURST_START_SHIFT 16
2162 # define TV_HBURST_START_MASK 0x1fff0000
2163 
2164 # define TV_HBURST_LEN_SHIFT 0
2165 # define TV_HBURST_LEN_MASK 0x0001fff
2167 #define TV_H_CTL_3 0x68038
2168 
2169 # define TV_HBLANK_END_SHIFT 16
2170 # define TV_HBLANK_END_MASK 0x1fff0000
2171 
2172 # define TV_HBLANK_START_SHIFT 0
2173 # define TV_HBLANK_START_MASK 0x0001fff
2175 #define TV_V_CTL_1 0x6803c
2176 
2177 # define TV_NBR_END_SHIFT 16
2178 # define TV_NBR_END_MASK 0x07ff0000
2179 
2180 # define TV_VI_END_F1_SHIFT 8
2181 # define TV_VI_END_F1_MASK 0x00003f00
2182 
2183 # define TV_VI_END_F2_SHIFT 0
2184 # define TV_VI_END_F2_MASK 0x0000003f
2186 #define TV_V_CTL_2 0x68040
2187 
2188 # define TV_VSYNC_LEN_MASK 0x07ff0000
2189 # define TV_VSYNC_LEN_SHIFT 16
2193 # define TV_VSYNC_START_F1_MASK 0x00007f00
2194 # define TV_VSYNC_START_F1_SHIFT 8
2195 
2199 # define TV_VSYNC_START_F2_MASK 0x0000007f
2200 # define TV_VSYNC_START_F2_SHIFT 0
2202 #define TV_V_CTL_3 0x68044
2204 # define TV_EQUAL_ENA (1 << 31)
2205 
2206 # define TV_VEQ_LEN_MASK 0x007f0000
2207 # define TV_VEQ_LEN_SHIFT 16
2211 # define TV_VEQ_START_F1_MASK 0x0007f00
2212 # define TV_VEQ_START_F1_SHIFT 8
2213 
2217 # define TV_VEQ_START_F2_MASK 0x000007f
2218 # define TV_VEQ_START_F2_SHIFT 0
2219 
2220 #define TV_V_CTL_4 0x68048
2221 
2225 # define TV_VBURST_START_F1_MASK 0x003f0000
2226 # define TV_VBURST_START_F1_SHIFT 16
2227 
2231 # define TV_VBURST_END_F1_MASK 0x000000ff
2232 # define TV_VBURST_END_F1_SHIFT 0
2233 
2234 #define TV_V_CTL_5 0x6804c
2235 
2239 # define TV_VBURST_START_F2_MASK 0x003f0000
2240 # define TV_VBURST_START_F2_SHIFT 16
2241 
2245 # define TV_VBURST_END_F2_MASK 0x000000ff
2246 # define TV_VBURST_END_F2_SHIFT 0
2247 
2248 #define TV_V_CTL_6 0x68050
2249 
2253 # define TV_VBURST_START_F3_MASK 0x003f0000
2254 # define TV_VBURST_START_F3_SHIFT 16
2255 
2259 # define TV_VBURST_END_F3_MASK 0x000000ff
2260 # define TV_VBURST_END_F3_SHIFT 0
2261 
2262 #define TV_V_CTL_7 0x68054
2263 
2267 # define TV_VBURST_START_F4_MASK 0x003f0000
2268 # define TV_VBURST_START_F4_SHIFT 16
2269 
2273 # define TV_VBURST_END_F4_MASK 0x000000ff
2274 # define TV_VBURST_END_F4_SHIFT 0
2276 #define TV_SC_CTL_1 0x68060
2278 # define TV_SC_DDA1_EN (1 << 31)
2280 # define TV_SC_DDA2_EN (1 << 30)
2282 # define TV_SC_DDA3_EN (1 << 29)
2284 # define TV_SC_RESET_EVERY_2 (0 << 24)
2286 # define TV_SC_RESET_EVERY_4 (1 << 24)
2288 # define TV_SC_RESET_EVERY_8 (2 << 24)
2290 # define TV_SC_RESET_NEVER (3 << 24)
2291 
2292 # define TV_BURST_LEVEL_MASK 0x00ff0000
2293 # define TV_BURST_LEVEL_SHIFT 16
2294 
2295 # define TV_SCDDA1_INC_MASK 0x00000fff
2296 # define TV_SCDDA1_INC_SHIFT 0
2298 #define TV_SC_CTL_2 0x68064
2299 
2300 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
2301 # define TV_SCDDA2_SIZE_SHIFT 16
2302 
2303 # define TV_SCDDA2_INC_MASK 0x00007fff
2304 # define TV_SCDDA2_INC_SHIFT 0
2306 #define TV_SC_CTL_3 0x68068
2307 
2308 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
2309 # define TV_SCDDA3_SIZE_SHIFT 16
2310 
2311 # define TV_SCDDA3_INC_MASK 0x00007fff
2312 # define TV_SCDDA3_INC_SHIFT 0
2314 #define TV_WIN_POS 0x68070
2315 
2316 # define TV_XPOS_MASK 0x1fff0000
2317 # define TV_XPOS_SHIFT 16
2318 
2319 # define TV_YPOS_MASK 0x00000fff
2320 # define TV_YPOS_SHIFT 0
2322 #define TV_WIN_SIZE 0x68074
2323 
2324 # define TV_XSIZE_MASK 0x1fff0000
2325 # define TV_XSIZE_SHIFT 16
2326 
2331 # define TV_YSIZE_MASK 0x00000fff
2332 # define TV_YSIZE_SHIFT 0
2333 
2334 #define TV_FILTER_CTL_1 0x68080
2335 
2341 # define TV_AUTO_SCALE (1 << 31)
2342 
2346 # define TV_V_FILTER_BYPASS (1 << 29)
2347 
2348 # define TV_VADAPT (1 << 28)
2349 # define TV_VADAPT_MODE_MASK (3 << 26)
2351 # define TV_VADAPT_MODE_LEAST (0 << 26)
2353 # define TV_VADAPT_MODE_MODERATE (1 << 26)
2354 
2355 # define TV_VADAPT_MODE_MOST (3 << 26)
2356 
2364 # define TV_HSCALE_FRAC_MASK 0x00003fff
2365 # define TV_HSCALE_FRAC_SHIFT 0
2366 
2367 #define TV_FILTER_CTL_2 0x68084
2368 
2373 # define TV_VSCALE_INT_MASK 0x00038000
2374 # define TV_VSCALE_INT_SHIFT 15
2375 
2380 # define TV_VSCALE_FRAC_MASK 0x00007fff
2381 # define TV_VSCALE_FRAC_SHIFT 0
2382 
2383 #define TV_FILTER_CTL_3 0x68088
2384 
2391 # define TV_VSCALE_IP_INT_MASK 0x00038000
2392 # define TV_VSCALE_IP_INT_SHIFT 15
2393 
2400 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
2401 # define TV_VSCALE_IP_FRAC_SHIFT 0
2402 
2403 #define TV_CC_CONTROL 0x68090
2404 # define TV_CC_ENABLE (1 << 31)
2405 
2410 # define TV_CC_FID_MASK (1 << 27)
2411 # define TV_CC_FID_SHIFT 27
2412 
2413 # define TV_CC_HOFF_MASK 0x03ff0000
2414 # define TV_CC_HOFF_SHIFT 16
2415 
2416 # define TV_CC_LINE_MASK 0x0000003f
2417 # define TV_CC_LINE_SHIFT 0
2418 
2419 #define TV_CC_DATA 0x68094
2420 # define TV_CC_RDY (1 << 31)
2421 
2422 # define TV_CC_DATA_2_MASK 0x007f0000
2423 # define TV_CC_DATA_2_SHIFT 16
2424 
2425 # define TV_CC_DATA_1_MASK 0x0000007f
2426 # define TV_CC_DATA_1_SHIFT 0
2428 #define TV_H_LUMA_0 0x68100
2429 #define TV_H_LUMA_59 0x681ec
2430 #define TV_H_CHROMA_0 0x68200
2431 #define TV_H_CHROMA_59 0x682ec
2432 #define TV_V_LUMA_0 0x68300
2433 #define TV_V_LUMA_42 0x683a8
2434 #define TV_V_CHROMA_0 0x68400
2435 #define TV_V_CHROMA_42 0x684a8
2437 /* Display Port */
2438 #define DP_A 0x64000 /* eDP */
2439 #define DP_B 0x64100
2440 #define DP_C 0x64200
2441 #define DP_D 0x64300
2443 #define DP_PORT_EN (1 << 31)
2444 #define DP_PIPEB_SELECT (1 << 30)
2445 #define DP_PIPE_MASK (1 << 30)
2447 /* Link training mode - select a suitable mode for each stage */
2448 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
2449 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
2450 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
2451 #define DP_LINK_TRAIN_OFF (3 << 28)
2452 #define DP_LINK_TRAIN_MASK (3 << 28)
2453 #define DP_LINK_TRAIN_SHIFT 28
2455 /* CPT Link training mode */
2456 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
2457 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
2458 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
2459 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
2460 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
2461 #define DP_LINK_TRAIN_SHIFT_CPT 8
2463 /* Signal voltages. These are mostly controlled by the other end */
2464 #define DP_VOLTAGE_0_4 (0 << 25)
2465 #define DP_VOLTAGE_0_6 (1 << 25)
2466 #define DP_VOLTAGE_0_8 (2 << 25)
2467 #define DP_VOLTAGE_1_2 (3 << 25)
2468 #define DP_VOLTAGE_MASK (7 << 25)
2469 #define DP_VOLTAGE_SHIFT 25
2470 
2471 /* Signal pre-emphasis levels, like voltages, the other end tells us what
2472  * they want
2473  */
2474 #define DP_PRE_EMPHASIS_0 (0 << 22)
2475 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
2476 #define DP_PRE_EMPHASIS_6 (2 << 22)
2477 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
2478 #define DP_PRE_EMPHASIS_MASK (7 << 22)
2479 #define DP_PRE_EMPHASIS_SHIFT 22
2481 /* How many wires to use. I guess 3 was too hard */
2482 #define DP_PORT_WIDTH_1 (0 << 19)
2483 #define DP_PORT_WIDTH_2 (1 << 19)
2484 #define DP_PORT_WIDTH_4 (3 << 19)
2485 #define DP_PORT_WIDTH_MASK (7 << 19)
2486 
2487 /* Mystic DPCD version 1.1 special mode */
2488 #define DP_ENHANCED_FRAMING (1 << 18)
2490 /* eDP */
2491 #define DP_PLL_FREQ_270MHZ (0 << 16)
2492 #define DP_PLL_FREQ_160MHZ (1 << 16)
2493 #define DP_PLL_FREQ_MASK (3 << 16)
2494 
2496 #define DP_PORT_REVERSAL (1 << 15)
2497 
2498 /* eDP */
2499 #define DP_PLL_ENABLE (1 << 14)
2500 
2502 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
2503 
2504 #define DP_SCRAMBLING_DISABLE (1 << 12)
2505 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
2506 
2508 #define DP_COLOR_RANGE_16_235 (1 << 8)
2509 
2511 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
2514 #define DP_SYNC_VS_HIGH (1 << 4)
2515 #define DP_SYNC_HS_HIGH (1 << 3)
2516 
2518 #define DP_DETECTED (1 << 2)
2519 
2525 #define DPA_AUX_CH_CTL 0x64010
2526 #define DPA_AUX_CH_DATA1 0x64014
2527 #define DPA_AUX_CH_DATA2 0x64018
2528 #define DPA_AUX_CH_DATA3 0x6401c
2529 #define DPA_AUX_CH_DATA4 0x64020
2530 #define DPA_AUX_CH_DATA5 0x64024
2532 #define DPB_AUX_CH_CTL 0x64110
2533 #define DPB_AUX_CH_DATA1 0x64114
2534 #define DPB_AUX_CH_DATA2 0x64118
2535 #define DPB_AUX_CH_DATA3 0x6411c
2536 #define DPB_AUX_CH_DATA4 0x64120
2537 #define DPB_AUX_CH_DATA5 0x64124
2539 #define DPC_AUX_CH_CTL 0x64210
2540 #define DPC_AUX_CH_DATA1 0x64214
2541 #define DPC_AUX_CH_DATA2 0x64218
2542 #define DPC_AUX_CH_DATA3 0x6421c
2543 #define DPC_AUX_CH_DATA4 0x64220
2544 #define DPC_AUX_CH_DATA5 0x64224
2546 #define DPD_AUX_CH_CTL 0x64310
2547 #define DPD_AUX_CH_DATA1 0x64314
2548 #define DPD_AUX_CH_DATA2 0x64318
2549 #define DPD_AUX_CH_DATA3 0x6431c
2550 #define DPD_AUX_CH_DATA4 0x64320
2551 #define DPD_AUX_CH_DATA5 0x64324
2553 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
2554 #define DP_AUX_CH_CTL_DONE (1 << 30)
2555 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
2556 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
2557 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
2558 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
2559 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
2560 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
2561 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
2562 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
2563 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
2564 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
2565 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
2566 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
2567 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
2568 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
2569 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
2570 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
2571 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
2572 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
2573 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
2574 
2575 /*
2576  * Computing GMCH M and N values for the Display Port link
2577  *
2578  * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2579  *
2580  * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2581  *
2582  * The GMCH value is used internally
2583  *
2584  * bytes_per_pixel is the number of bytes coming out of the plane,
2585  * which is after the LUTs, so we want the bytes for our color format.
2586  * For our current usage, this is always 3, one byte for R, G and B.
2587  */
2588 #define _PIPEA_GMCH_DATA_M 0x70050
2589 #define _PIPEB_GMCH_DATA_M 0x71050
2591 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2592 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
2593 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
2595 #define PIPE_GMCH_DATA_M_MASK (0xffffff)
2597 #define _PIPEA_GMCH_DATA_N 0x70054
2598 #define _PIPEB_GMCH_DATA_N 0x71054
2599 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
2600 
2601 /*
2602  * Computing Link M and N values for the Display Port link
2603  *
2604  * Link M / N = pixel_clock / ls_clk
2605  *
2606  * (the DP spec calls pixel_clock the 'strm_clk')
2607  *
2608  * The Link value is transmitted in the Main Stream
2609  * Attributes and VB-ID.
2610  */
2612 #define _PIPEA_DP_LINK_M 0x70060
2613 #define _PIPEB_DP_LINK_M 0x71060
2614 #define PIPEA_DP_LINK_M_MASK (0xffffff)
2616 #define _PIPEA_DP_LINK_N 0x70064
2617 #define _PIPEB_DP_LINK_N 0x71064
2618 #define PIPEA_DP_LINK_N_MASK (0xffffff)
2620 #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
2621 #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
2622 #define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
2623 #define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
2624 
2625 /* Display & cursor control */
2627 /* Pipe A */
2628 #define _PIPEADSL 0x70000
2629 #define DSL_LINEMASK_GEN2 0x00000fff
2630 #define DSL_LINEMASK_GEN3 0x00001fff
2631 #define _PIPEACONF 0x70008
2632 #define PIPECONF_ENABLE (1<<31)
2633 #define PIPECONF_DISABLE 0
2634 #define PIPECONF_DOUBLE_WIDE (1<<30)
2635 #define I965_PIPECONF_ACTIVE (1<<30)
2636 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
2637 #define PIPECONF_SINGLE_WIDE 0
2638 #define PIPECONF_PIPE_UNLOCKED 0
2639 #define PIPECONF_PIPE_LOCKED (1<<25)
2640 #define PIPECONF_PALETTE 0
2641 #define PIPECONF_GAMMA (1<<24)
2642 #define PIPECONF_FORCE_BORDER (1<<25)
2643 #define PIPECONF_INTERLACE_MASK (7 << 21)
2644 /* Note that pre-gen3 does not support interlaced display directly. Panel
2645  * fitting must be disabled on pre-ilk for interlaced. */
2646 #define PIPECONF_PROGRESSIVE (0 << 21)
2647 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
2648 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
2649 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2650 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
2651 /* Ironlake and later have a complete new set of values for interlaced. PFIT
2652  * means panel fitter required, PF means progressive fetch, DBL means power
2653  * saving pixel doubling. */
2654 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
2655 #define PIPECONF_INTERLACED_ILK (3 << 21)
2656 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
2657 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
2658 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
2659 #define PIPECONF_BPP_MASK (0x000000e0)
2660 #define PIPECONF_BPP_8 (0<<5)
2661 #define PIPECONF_BPP_10 (1<<5)
2662 #define PIPECONF_BPP_6 (2<<5)
2663 #define PIPECONF_BPP_12 (3<<5)
2664 #define PIPECONF_DITHER_EN (1<<4)
2665 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
2666 #define PIPECONF_DITHER_TYPE_SP (0<<2)
2667 #define PIPECONF_DITHER_TYPE_ST1 (1<<2)
2668 #define PIPECONF_DITHER_TYPE_ST2 (2<<2)
2669 #define PIPECONF_DITHER_TYPE_TEMP (3<<2)
2670 #define _PIPEASTAT 0x70024
2671 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
2672 #define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30)
2673 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
2674 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
2675 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
2676 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
2677 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
2678 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
2679 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
2680 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
2681 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<26)
2682 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
2683 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
2684 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
2685 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
2686 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
2687 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
2688 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
2689 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
2690 #define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15)
2691 #define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<15)
2692 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
2693 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
2694 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
2695 #define PLANE_FLIPDONE_INT_STATUS_VLV (1UL<<10)
2696 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
2697 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
2698 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
2699 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
2700 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
2701 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
2702 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
2703 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
2704 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
2705 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
2706 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
2707 #define PIPE_BPC_MASK (7 << 5) /* Ironlake */
2708 #define PIPE_8BPC (0 << 5)
2709 #define PIPE_10BPC (1 << 5)
2710 #define PIPE_6BPC (2 << 5)
2711 #define PIPE_12BPC (3 << 5)
2713 #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
2714 #define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
2715 #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
2716 #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
2717 #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
2718 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
2720 #define VLV_DPFLIPSTAT 0x70028
2721 #define PIPEB_LINE_COMPARE_INT_EN (1<<29)
2722 #define PIPEB_HLINE_INT_EN (1<<28)
2723 #define PIPEB_VBLANK_INT_EN (1<<27)
2724 #define SPRITED_FLIPDONE_INT_EN (1<<26)
2725 #define SPRITEC_FLIPDONE_INT_EN (1<<25)
2726 #define PLANEB_FLIPDONE_INT_EN (1<<24)
2727 #define PIPEA_LINE_COMPARE_INT_EN (1<<21)
2728 #define PIPEA_HLINE_INT_EN (1<<20)
2729 #define PIPEA_VBLANK_INT_EN (1<<19)
2730 #define SPRITEB_FLIPDONE_INT_EN (1<<18)
2731 #define SPRITEA_FLIPDONE_INT_EN (1<<17)
2732 #define PLANEA_FLIPDONE_INT_EN (1<<16)
2734 #define DPINVGTT 0x7002c /* VLV only */
2735 #define CURSORB_INVALID_GTT_INT_EN (1<<23)
2736 #define CURSORA_INVALID_GTT_INT_EN (1<<22)
2737 #define SPRITED_INVALID_GTT_INT_EN (1<<21)
2738 #define SPRITEC_INVALID_GTT_INT_EN (1<<20)
2739 #define PLANEB_INVALID_GTT_INT_EN (1<<19)
2740 #define SPRITEB_INVALID_GTT_INT_EN (1<<18)
2741 #define SPRITEA_INVALID_GTT_INT_EN (1<<17)
2742 #define PLANEA_INVALID_GTT_INT_EN (1<<16)
2743 #define DPINVGTT_EN_MASK 0xff0000
2744 #define CURSORB_INVALID_GTT_STATUS (1<<7)
2745 #define CURSORA_INVALID_GTT_STATUS (1<<6)
2746 #define SPRITED_INVALID_GTT_STATUS (1<<5)
2747 #define SPRITEC_INVALID_GTT_STATUS (1<<4)
2748 #define PLANEB_INVALID_GTT_STATUS (1<<3)
2749 #define SPRITEB_INVALID_GTT_STATUS (1<<2)
2750 #define SPRITEA_INVALID_GTT_STATUS (1<<1)
2751 #define PLANEA_INVALID_GTT_STATUS (1<<0)
2752 #define DPINVGTT_STATUS_MASK 0xff
2754 #define DSPARB 0x70030
2755 #define DSPARB_CSTART_MASK (0x7f << 7)
2756 #define DSPARB_CSTART_SHIFT 7
2757 #define DSPARB_BSTART_MASK (0x7f)
2758 #define DSPARB_BSTART_SHIFT 0
2759 #define DSPARB_BEND_SHIFT 9 /* on 855 */
2760 #define DSPARB_AEND_SHIFT 0
2762 #define DSPFW1 0x70034
2763 #define DSPFW_SR_SHIFT 23
2764 #define DSPFW_SR_MASK (0x1ff<<23)
2765 #define DSPFW_CURSORB_SHIFT 16
2766 #define DSPFW_CURSORB_MASK (0x3f<<16)
2767 #define DSPFW_PLANEB_SHIFT 8
2768 #define DSPFW_PLANEB_MASK (0x7f<<8)
2769 #define DSPFW_PLANEA_MASK (0x7f)
2770 #define DSPFW2 0x70038
2771 #define DSPFW_CURSORA_MASK 0x00003f00
2772 #define DSPFW_CURSORA_SHIFT 8
2773 #define DSPFW_PLANEC_MASK (0x7f)
2774 #define DSPFW3 0x7003c
2775 #define DSPFW_HPLL_SR_EN (1<<31)
2776 #define DSPFW_CURSOR_SR_SHIFT 24
2777 #define PINEVIEW_SELF_REFRESH_EN (1<<30)
2778 #define DSPFW_CURSOR_SR_MASK (0x3f<<24)
2779 #define DSPFW_HPLL_CURSOR_SHIFT 16
2780 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
2781 #define DSPFW_HPLL_SR_MASK (0x1ff)
2783 /* drain latency register values*/
2784 #define DRAIN_LATENCY_PRECISION_32 32
2785 #define DRAIN_LATENCY_PRECISION_16 16
2786 #define VLV_DDL1 0x70050
2787 #define DDL_CURSORA_PRECISION_32 (1<<31)
2788 #define DDL_CURSORA_PRECISION_16 (0<<31)
2789 #define DDL_CURSORA_SHIFT 24
2790 #define DDL_PLANEA_PRECISION_32 (1<<7)
2791 #define DDL_PLANEA_PRECISION_16 (0<<7)
2792 #define VLV_DDL2 0x70054
2793 #define DDL_CURSORB_PRECISION_32 (1<<31)
2794 #define DDL_CURSORB_PRECISION_16 (0<<31)
2795 #define DDL_CURSORB_SHIFT 24
2796 #define DDL_PLANEB_PRECISION_32 (1<<7)
2797 #define DDL_PLANEB_PRECISION_16 (0<<7)
2799 /* FIFO watermark sizes etc */
2800 #define G4X_FIFO_LINE_SIZE 64
2801 #define I915_FIFO_LINE_SIZE 64
2802 #define I830_FIFO_LINE_SIZE 32
2804 #define VALLEYVIEW_FIFO_SIZE 255
2805 #define G4X_FIFO_SIZE 127
2806 #define I965_FIFO_SIZE 512
2807 #define I945_FIFO_SIZE 127
2808 #define I915_FIFO_SIZE 95
2809 #define I855GM_FIFO_SIZE 127 /* In cachelines */
2810 #define I830_FIFO_SIZE 95
2812 #define VALLEYVIEW_MAX_WM 0xff
2813 #define G4X_MAX_WM 0x3f
2814 #define I915_MAX_WM 0x3f
2816 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
2817 #define PINEVIEW_FIFO_LINE_SIZE 64
2818 #define PINEVIEW_MAX_WM 0x1ff
2819 #define PINEVIEW_DFT_WM 0x3f
2820 #define PINEVIEW_DFT_HPLLOFF_WM 0
2821 #define PINEVIEW_GUARD_WM 10
2822 #define PINEVIEW_CURSOR_FIFO 64
2823 #define PINEVIEW_CURSOR_MAX_WM 0x3f
2824 #define PINEVIEW_CURSOR_DFT_WM 0
2825 #define PINEVIEW_CURSOR_GUARD_WM 5
2827 #define VALLEYVIEW_CURSOR_MAX_WM 64
2828 #define I965_CURSOR_FIFO 64
2829 #define I965_CURSOR_MAX_WM 32
2830 #define I965_CURSOR_DFT_WM 8
2832 /* define the Watermark register on Ironlake */
2833 #define WM0_PIPEA_ILK 0x45100
2834 #define WM0_PIPE_PLANE_MASK (0x7f<<16)
2835 #define WM0_PIPE_PLANE_SHIFT 16
2836 #define WM0_PIPE_SPRITE_MASK (0x3f<<8)
2837 #define WM0_PIPE_SPRITE_SHIFT 8
2838 #define WM0_PIPE_CURSOR_MASK (0x1f)
2840 #define WM0_PIPEB_ILK 0x45104
2841 #define WM0_PIPEC_IVB 0x45200
2842 #define WM1_LP_ILK 0x45108
2843 #define WM1_LP_SR_EN (1<<31)
2844 #define WM1_LP_LATENCY_SHIFT 24
2845 #define WM1_LP_LATENCY_MASK (0x7f<<24)
2846 #define WM1_LP_FBC_MASK (0xf<<20)
2847 #define WM1_LP_FBC_SHIFT 20
2848 #define WM1_LP_SR_MASK (0x1ff<<8)
2849 #define WM1_LP_SR_SHIFT 8
2850 #define WM1_LP_CURSOR_MASK (0x3f)
2851 #define WM2_LP_ILK 0x4510c
2852 #define WM2_LP_EN (1<<31)
2853 #define WM3_LP_ILK 0x45110
2854 #define WM3_LP_EN (1<<31)
2855 #define WM1S_LP_ILK 0x45120
2856 #define WM2S_LP_IVB 0x45124
2857 #define WM3S_LP_IVB 0x45128
2858 #define WM1S_LP_EN (1<<31)
2860 /* Memory latency timer register */
2861 #define MLTR_ILK 0x11222
2862 #define MLTR_WM1_SHIFT 0
2863 #define MLTR_WM2_SHIFT 8
2864 /* the unit of memory self-refresh latency time is 0.5us */
2865 #define ILK_SRLT_MASK 0x3f
2866 #define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
2867 #define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT)
2868 #define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT)
2870 /* define the fifo size on Ironlake */
2871 #define ILK_DISPLAY_FIFO 128
2872 #define ILK_DISPLAY_MAXWM 64
2873 #define ILK_DISPLAY_DFTWM 8
2874 #define ILK_CURSOR_FIFO 32
2875 #define ILK_CURSOR_MAXWM 16
2876 #define ILK_CURSOR_DFTWM 8
2878 #define ILK_DISPLAY_SR_FIFO 512
2879 #define ILK_DISPLAY_MAX_SRWM 0x1ff
2880 #define ILK_DISPLAY_DFT_SRWM 0x3f
2881 #define ILK_CURSOR_SR_FIFO 64
2882 #define ILK_CURSOR_MAX_SRWM 0x3f
2883 #define ILK_CURSOR_DFT_SRWM 8
2884 
2885 #define ILK_FIFO_LINE_SIZE 64
2887 /* define the WM info on Sandybridge */
2888 #define SNB_DISPLAY_FIFO 128
2889 #define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */
2890 #define SNB_DISPLAY_DFTWM 8
2891 #define SNB_CURSOR_FIFO 32
2892 #define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */
2893 #define SNB_CURSOR_DFTWM 8
2895 #define SNB_DISPLAY_SR_FIFO 512
2896 #define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */
2897 #define SNB_DISPLAY_DFT_SRWM 0x3f
2898 #define SNB_CURSOR_SR_FIFO 64
2899 #define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */
2900 #define SNB_CURSOR_DFT_SRWM 8
2902 #define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */
2903 
2904 #define SNB_FIFO_LINE_SIZE 64
2907 /* the address where we get all kinds of latency value */
2908 #define SSKPD 0x5d10
2909 #define SSKPD_WM_MASK 0x3f
2910 #define SSKPD_WM0_SHIFT 0
2911 #define SSKPD_WM1_SHIFT 8
2912 #define SSKPD_WM2_SHIFT 16
2913 #define SSKPD_WM3_SHIFT 24
2915 #define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
2916 #define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT)
2917 #define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT)
2918 #define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT)
2919 #define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT)
2920 
2921 /*
2922  * The two pipe frame counter registers are not synchronized, so
2923  * reading a stable value is somewhat tricky. The following code
2924  * should work:
2925  *
2926  * do {
2927  * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2928  * PIPE_FRAME_HIGH_SHIFT;
2929  * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2930  * PIPE_FRAME_LOW_SHIFT);
2931  * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2932  * PIPE_FRAME_HIGH_SHIFT);
2933  * } while (high1 != high2);
2934  * frame = (high1 << 8) | low1;
2935  */
2936 #define _PIPEAFRAMEHIGH 0x70040
2937 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
2938 #define PIPE_FRAME_HIGH_SHIFT 0
2939 #define _PIPEAFRAMEPIXEL 0x70044
2940 #define PIPE_FRAME_LOW_MASK 0xff000000
2941 #define PIPE_FRAME_LOW_SHIFT 24
2942 #define PIPE_PIXEL_MASK 0x00ffffff
2943 #define PIPE_PIXEL_SHIFT 0
2944 /* GM45+ just has to be different */
2945 #define _PIPEA_FRMCOUNT_GM45 0x70040
2946 #define _PIPEA_FLIPCOUNT_GM45 0x70044
2947 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
2948 
2949 /* Cursor A & B regs */
2950 #define _CURACNTR 0x70080
2951 /* Old style CUR*CNTR flags (desktop 8xx) */
2952 #define CURSOR_ENABLE 0x80000000
2953 #define CURSOR_GAMMA_ENABLE 0x40000000
2954 #define CURSOR_STRIDE_MASK 0x30000000
2955 #define CURSOR_FORMAT_SHIFT 24
2956 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
2957 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
2958 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
2959 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
2960 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
2961 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
2962 /* New style CUR*CNTR flags */
2963 #define CURSOR_MODE 0x27
2964 #define CURSOR_MODE_DISABLE 0x00
2965 #define CURSOR_MODE_64_32B_AX 0x07
2966 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
2967 #define MCURSOR_PIPE_SELECT (1 << 28)
2968 #define MCURSOR_PIPE_A 0x00
2969 #define MCURSOR_PIPE_B (1 << 28)
2970 #define MCURSOR_GAMMA_ENABLE (1 << 26)
2971 #define _CURABASE 0x70084
2972 #define _CURAPOS 0x70088
2973 #define CURSOR_POS_MASK 0x007FF
2974 #define CURSOR_POS_SIGN 0x8000
2975 #define CURSOR_X_SHIFT 0
2976 #define CURSOR_Y_SHIFT 16
2977 #define CURSIZE 0x700a0
2978 #define _CURBCNTR 0x700c0
2979 #define _CURBBASE 0x700c4
2980 #define _CURBPOS 0x700c8
2982 #define _CURBCNTR_IVB 0x71080
2983 #define _CURBBASE_IVB 0x71084
2984 #define _CURBPOS_IVB 0x71088
2986 #define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
2987 #define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
2988 #define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
2990 #define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
2991 #define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
2992 #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
2994 /* Display A control */
2995 #define _DSPACNTR 0x70180
2996 #define DISPLAY_PLANE_ENABLE (1<<31)
2997 #define DISPLAY_PLANE_DISABLE 0
2998 #define DISPPLANE_GAMMA_ENABLE (1<<30)
2999 #define DISPPLANE_GAMMA_DISABLE 0
3000 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
3001 #define DISPPLANE_8BPP (0x2<<26)
3002 #define DISPPLANE_15_16BPP (0x4<<26)
3003 #define DISPPLANE_16BPP (0x5<<26)
3004 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
3005 #define DISPPLANE_32BPP (0x7<<26)
3006 #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
3007 #define DISPPLANE_STEREO_ENABLE (1<<25)
3008 #define DISPPLANE_STEREO_DISABLE 0
3009 #define DISPPLANE_SEL_PIPE_SHIFT 24
3010 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
3011 #define DISPPLANE_SEL_PIPE_A 0
3012 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
3013 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
3014 #define DISPPLANE_SRC_KEY_DISABLE 0
3015 #define DISPPLANE_LINE_DOUBLE (1<<20)
3016 #define DISPPLANE_NO_LINE_DOUBLE 0
3017 #define DISPPLANE_STEREO_POLARITY_FIRST 0
3018 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
3019 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
3020 #define DISPPLANE_TILED (1<<10)
3021 #define _DSPAADDR 0x70184
3022 #define _DSPASTRIDE 0x70188
3023 #define _DSPAPOS 0x7018C /* reserved */
3024 #define _DSPASIZE 0x70190
3025 #define _DSPASURF 0x7019C /* 965+ only */
3026 #define _DSPATILEOFF 0x701A4 /* 965+ only */
3028 #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
3029 #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
3030 #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
3031 #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
3032 #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
3033 #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
3034 #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
3035 #define DSPLINOFF(plane) DSPADDR(plane)
3037 /* Display/Sprite base address macros */
3038 #define DISP_BASEADDR_MASK (0xfffff000)
3039 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
3040 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
3041 #define I915_MODIFY_DISPBASE(reg, gfx_addr) \
3042  (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))
3044 /* VBIOS flags */
3045 #define SWF00 0x71410
3046 #define SWF01 0x71414
3047 #define SWF02 0x71418
3048 #define SWF03 0x7141c
3049 #define SWF04 0x71420
3050 #define SWF05 0x71424
3051 #define SWF06 0x71428
3052 #define SWF10 0x70410
3053 #define SWF11 0x70414
3054 #define SWF14 0x71420
3055 #define SWF30 0x72414
3056 #define SWF31 0x72418
3057 #define SWF32 0x7241c
3059 /* Pipe B */
3060 #define _PIPEBDSL 0x71000
3061 #define _PIPEBCONF 0x71008
3062 #define _PIPEBSTAT 0x71024
3063 #define _PIPEBFRAMEHIGH 0x71040
3064 #define _PIPEBFRAMEPIXEL 0x71044
3065 #define _PIPEB_FRMCOUNT_GM45 0x71040
3066 #define _PIPEB_FLIPCOUNT_GM45 0x71044
3069 /* Display B control */
3070 #define _DSPBCNTR 0x71180
3071 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
3072 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
3073 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
3074 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
3075 #define _DSPBADDR 0x71184
3076 #define _DSPBSTRIDE 0x71188
3077 #define _DSPBPOS 0x7118C
3078 #define _DSPBSIZE 0x71190
3079 #define _DSPBSURF 0x7119C
3080 #define _DSPBTILEOFF 0x711A4
3082 /* Sprite A control */
3083 #define _DVSACNTR 0x72180
3084 #define DVS_ENABLE (1<<31)
3085 #define DVS_GAMMA_ENABLE (1<<30)
3086 #define DVS_PIXFORMAT_MASK (3<<25)
3087 #define DVS_FORMAT_YUV422 (0<<25)
3088 #define DVS_FORMAT_RGBX101010 (1<<25)
3089 #define DVS_FORMAT_RGBX888 (2<<25)
3090 #define DVS_FORMAT_RGBX161616 (3<<25)
3091 #define DVS_SOURCE_KEY (1<<22)
3092 #define DVS_RGB_ORDER_XBGR (1<<20)
3093 #define DVS_YUV_BYTE_ORDER_MASK (3<<16)
3094 #define DVS_YUV_ORDER_YUYV (0<<16)
3095 #define DVS_YUV_ORDER_UYVY (1<<16)
3096 #define DVS_YUV_ORDER_YVYU (2<<16)
3097 #define DVS_YUV_ORDER_VYUY (3<<16)
3098 #define DVS_DEST_KEY (1<<2)
3099 #define DVS_TRICKLE_FEED_DISABLE (1<<14)
3100 #define DVS_TILED (1<<10)
3101 #define _DVSALINOFF 0x72184
3102 #define _DVSASTRIDE 0x72188
3103 #define _DVSAPOS 0x7218c
3104 #define _DVSASIZE 0x72190
3105 #define _DVSAKEYVAL 0x72194
3106 #define _DVSAKEYMSK 0x72198
3107 #define _DVSASURF 0x7219c
3108 #define _DVSAKEYMAXVAL 0x721a0
3109 #define _DVSATILEOFF 0x721a4
3110 #define _DVSASURFLIVE 0x721ac
3111 #define _DVSASCALE 0x72204
3112 #define DVS_SCALE_ENABLE (1<<31)
3113 #define DVS_FILTER_MASK (3<<29)
3114 #define DVS_FILTER_MEDIUM (0<<29)
3115 #define DVS_FILTER_ENHANCING (1<<29)
3116 #define DVS_FILTER_SOFTENING (2<<29)
3117 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
3118 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
3119 #define _DVSAGAMC 0x72300
3121 #define _DVSBCNTR 0x73180
3122 #define _DVSBLINOFF 0x73184
3123 #define _DVSBSTRIDE 0x73188
3124 #define _DVSBPOS 0x7318c
3125 #define _DVSBSIZE 0x73190
3126 #define _DVSBKEYVAL 0x73194
3127 #define _DVSBKEYMSK 0x73198
3128 #define _DVSBSURF 0x7319c
3129 #define _DVSBKEYMAXVAL 0x731a0
3130 #define _DVSBTILEOFF 0x731a4
3131 #define _DVSBSURFLIVE 0x731ac
3132 #define _DVSBSCALE 0x73204
3133 #define _DVSBGAMC 0x73300
3135 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
3136 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
3137 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
3138 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
3139 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
3140 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
3141 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
3142 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
3143 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
3144 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
3145 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
3147 #define _SPRA_CTL 0x70280
3148 #define SPRITE_ENABLE (1<<31)
3149 #define SPRITE_GAMMA_ENABLE (1<<30)
3150 #define SPRITE_PIXFORMAT_MASK (7<<25)
3151 #define SPRITE_FORMAT_YUV422 (0<<25)
3152 #define SPRITE_FORMAT_RGBX101010 (1<<25)
3153 #define SPRITE_FORMAT_RGBX888 (2<<25)
3154 #define SPRITE_FORMAT_RGBX161616 (3<<25)
3155 #define SPRITE_FORMAT_YUV444 (4<<25)
3156 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
3157 #define SPRITE_CSC_ENABLE (1<<24)
3158 #define SPRITE_SOURCE_KEY (1<<22)
3159 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
3160 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
3161 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
3162 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
3163 #define SPRITE_YUV_ORDER_YUYV (0<<16)
3164 #define SPRITE_YUV_ORDER_UYVY (1<<16)
3165 #define SPRITE_YUV_ORDER_YVYU (2<<16)
3166 #define SPRITE_YUV_ORDER_VYUY (3<<16)
3167 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
3168 #define SPRITE_INT_GAMMA_ENABLE (1<<13)
3169 #define SPRITE_TILED (1<<10)
3170 #define SPRITE_DEST_KEY (1<<2)
3171 #define _SPRA_LINOFF 0x70284
3172 #define _SPRA_STRIDE 0x70288
3173 #define _SPRA_POS 0x7028c
3174 #define _SPRA_SIZE 0x70290
3175 #define _SPRA_KEYVAL 0x70294
3176 #define _SPRA_KEYMSK 0x70298
3177 #define _SPRA_SURF 0x7029c
3178 #define _SPRA_KEYMAX 0x702a0
3179 #define _SPRA_TILEOFF 0x702a4
3180 #define _SPRA_SCALE 0x70304
3181 #define SPRITE_SCALE_ENABLE (1<<31)
3182 #define SPRITE_FILTER_MASK (3<<29)
3183 #define SPRITE_FILTER_MEDIUM (0<<29)
3184 #define SPRITE_FILTER_ENHANCING (1<<29)
3185 #define SPRITE_FILTER_SOFTENING (2<<29)
3186 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
3187 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
3188 #define _SPRA_GAMC 0x70400
3190 #define _SPRB_CTL 0x71280
3191 #define _SPRB_LINOFF 0x71284
3192 #define _SPRB_STRIDE 0x71288
3193 #define _SPRB_POS 0x7128c
3194 #define _SPRB_SIZE 0x71290
3195 #define _SPRB_KEYVAL 0x71294
3196 #define _SPRB_KEYMSK 0x71298
3197 #define _SPRB_SURF 0x7129c
3198 #define _SPRB_KEYMAX 0x712a0
3199 #define _SPRB_TILEOFF 0x712a4
3200 #define _SPRB_SCALE 0x71304
3201 #define _SPRB_GAMC 0x71400
3203 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
3204 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
3205 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
3206 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
3207 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
3208 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
3209 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
3210 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
3211 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
3212 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
3213 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
3214 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
3216 /* VBIOS regs */
3217 #define VGACNTRL 0x71400
3218 # define VGA_DISP_DISABLE (1 << 31)
3219 # define VGA_2X_MODE (1 << 30)
3220 # define VGA_PIPE_B_SELECT (1 << 29)
3222 /* Ironlake */
3224 #define CPU_VGACNTRL 0x41000
3226 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
3227 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
3228 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
3229 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
3230 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
3231 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
3232 #define DIGITAL_PORTA_NO_DETECT (0 << 0)
3233 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
3234 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
3236 /* refresh rate hardware control */
3237 #define RR_HW_CTL 0x45300
3238 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
3239 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
3241 #define FDI_PLL_BIOS_0 0x46000
3242 #define FDI_PLL_FB_CLOCK_MASK 0xff
3243 #define FDI_PLL_BIOS_1 0x46004
3244 #define FDI_PLL_BIOS_2 0x46008
3245 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
3246 #define DISPLAY_PORT_PLL_BIOS_1 0x46010
3247 #define DISPLAY_PORT_PLL_BIOS_2 0x46014
3249 #define PCH_DSPCLK_GATE_D 0x42020
3250 # define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
3251 # define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
3252 # define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
3253 # define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
3255 #define PCH_3DCGDIS0 0x46020
3256 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
3257 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
3258 
3259 #define PCH_3DCGDIS1 0x46024
3260 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
3262 #define FDI_PLL_FREQ_CTL 0x46030
3263 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
3264 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
3265 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
3268 #define _PIPEA_DATA_M1 0x60030
3269 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
3270 #define TU_SIZE_MASK 0x7e000000
3271 #define PIPE_DATA_M1_OFFSET 0
3272 #define _PIPEA_DATA_N1 0x60034
3273 #define PIPE_DATA_N1_OFFSET 0
3275 #define _PIPEA_DATA_M2 0x60038
3276 #define PIPE_DATA_M2_OFFSET 0
3277 #define _PIPEA_DATA_N2 0x6003c
3278 #define PIPE_DATA_N2_OFFSET 0
3280 #define _PIPEA_LINK_M1 0x60040
3281 #define PIPE_LINK_M1_OFFSET 0
3282 #define _PIPEA_LINK_N1 0x60044
3283 #define PIPE_LINK_N1_OFFSET 0
3285 #define _PIPEA_LINK_M2 0x60048
3286 #define PIPE_LINK_M2_OFFSET 0
3287 #define _PIPEA_LINK_N2 0x6004c
3288 #define PIPE_LINK_N2_OFFSET 0
3290 /* PIPEB timing regs are same start from 0x61000 */
3291 
3292 #define _PIPEB_DATA_M1 0x61030
3293 #define _PIPEB_DATA_N1 0x61034
3294 
3295 #define _PIPEB_DATA_M2 0x61038
3296 #define _PIPEB_DATA_N2 0x6103c
3297 
3298 #define _PIPEB_LINK_M1 0x61040
3299 #define _PIPEB_LINK_N1 0x61044
3300 
3301 #define _PIPEB_LINK_M2 0x61048
3302 #define _PIPEB_LINK_N2 0x6104c
3304 #define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
3305 #define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
3306 #define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
3307 #define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
3308 #define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
3309 #define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
3310 #define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
3311 #define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
3313 /* CPU panel fitter */
3314 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
3315 #define _PFA_CTL_1 0x68080
3316 #define _PFB_CTL_1 0x68880
3317 #define PF_ENABLE (1<<31)
3318 #define PF_FILTER_MASK (3<<23)
3319 #define PF_FILTER_PROGRAMMED (0<<23)
3320 #define PF_FILTER_MED_3x3 (1<<23)
3321 #define PF_FILTER_EDGE_ENHANCE (2<<23)
3322 #define PF_FILTER_EDGE_SOFTEN (3<<23)
3323 #define _PFA_WIN_SZ 0x68074
3324 #define _PFB_WIN_SZ 0x68874
3325 #define _PFA_WIN_POS 0x68070
3326 #define _PFB_WIN_POS 0x68870
3327 #define _PFA_VSCALE 0x68084
3328 #define _PFB_VSCALE 0x68884
3329 #define _PFA_HSCALE 0x68090
3330 #define _PFB_HSCALE 0x68890
3332 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
3333 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
3334 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
3335 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
3336 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
3338 /* legacy palette */
3339 #define _LGC_PALETTE_A 0x4a000
3340 #define _LGC_PALETTE_B 0x4a800
3341 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
3343 /* interrupts */
3344 #define DE_MASTER_IRQ_CONTROL (1 << 31)
3345 #define DE_SPRITEB_FLIP_DONE (1 << 29)
3346 #define DE_SPRITEA_FLIP_DONE (1 << 28)
3347 #define DE_PLANEB_FLIP_DONE (1 << 27)
3348 #define DE_PLANEA_FLIP_DONE (1 << 26)
3349 #define DE_PCU_EVENT (1 << 25)
3350 #define DE_GTT_FAULT (1 << 24)
3351 #define DE_POISON (1 << 23)
3352 #define DE_PERFORM_COUNTER (1 << 22)
3353 #define DE_PCH_EVENT (1 << 21)
3354 #define DE_AUX_CHANNEL_A (1 << 20)
3355 #define DE_DP_A_HOTPLUG (1 << 19)
3356 #define DE_GSE (1 << 18)
3357 #define DE_PIPEB_VBLANK (1 << 15)
3358 #define DE_PIPEB_EVEN_FIELD (1 << 14)
3359 #define DE_PIPEB_ODD_FIELD (1 << 13)
3360 #define DE_PIPEB_LINE_COMPARE (1 << 12)
3361 #define DE_PIPEB_VSYNC (1 << 11)
3362 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
3363 #define DE_PIPEA_VBLANK (1 << 7)
3364 #define DE_PIPEA_EVEN_FIELD (1 << 6)
3365 #define DE_PIPEA_ODD_FIELD (1 << 5)
3366 #define DE_PIPEA_LINE_COMPARE (1 << 4)
3367 #define DE_PIPEA_VSYNC (1 << 3)
3368 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
3370 /* More Ivybridge lolz */
3371 #define DE_ERR_DEBUG_IVB (1<<30)
3372 #define DE_GSE_IVB (1<<29)
3373 #define DE_PCH_EVENT_IVB (1<<28)
3374 #define DE_DP_A_HOTPLUG_IVB (1<<27)
3375 #define DE_AUX_CHANNEL_A_IVB (1<<26)
3376 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
3377 #define DE_PLANEC_FLIP_DONE_IVB (1<<13)
3378 #define DE_PIPEC_VBLANK_IVB (1<<10)
3379 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
3380 #define DE_PLANEB_FLIP_DONE_IVB (1<<8)
3381 #define DE_PIPEB_VBLANK_IVB (1<<5)
3382 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
3383 #define DE_PLANEA_FLIP_DONE_IVB (1<<3)
3384 #define DE_PIPEA_VBLANK_IVB (1<<0)
3385 
3386 #define VLV_MASTER_IER 0x4400c /* Gunit master IER */
3387 #define MASTER_INTERRUPT_ENABLE (1<<31)
3389 #define DEISR 0x44000
3390 #define DEIMR 0x44004
3391 #define DEIIR 0x44008
3392 #define DEIER 0x4400c
3393 
3394 /* GT interrupt.
3395  * Note that for gen6+ the ring-specific interrupt bits do alias with the
3396  * corresponding bits in the per-ring interrupt control registers. */
3397 #define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
3398 #define GT_GEN6_BLT_CS_ERROR_INTERRUPT (1 << 25)
3399 #define GT_GEN6_BLT_USER_INTERRUPT (1 << 22)
3400 #define GT_GEN6_BSD_CS_ERROR_INTERRUPT (1 << 15)
3401 #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12)
3402 #define GT_BSD_USER_INTERRUPT (1 << 5) /* ilk only */
3403 #define GT_GEN7_L3_PARITY_ERROR_INTERRUPT (1 << 5)
3404 #define GT_PIPE_NOTIFY (1 << 4)
3405 #define GT_RENDER_CS_ERROR_INTERRUPT (1 << 3)
3406 #define GT_SYNC_STATUS (1 << 2)
3407 #define GT_USER_INTERRUPT (1 << 0)
3409 #define GTISR 0x44010
3410 #define GTIMR 0x44014
3411 #define GTIIR 0x44018
3412 #define GTIER 0x4401c
3414 #define ILK_DISPLAY_CHICKEN2 0x42004
3415 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
3416 #define ILK_ELPIN_409_SELECT (1 << 25)
3417 #define ILK_DPARB_GATE (1<<22)
3418 #define ILK_VSDPFD_FULL (1<<21)
3419 #define ILK_DISPLAY_CHICKEN_FUSES 0x42014
3420 #define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31)
3421 #define ILK_INTERNAL_DISPLAY_DISABLE (1<<30)
3422 #define ILK_DISPLAY_DEBUG_DISABLE (1<<29)
3423 #define ILK_HDCP_DISABLE (1<<25)
3424 #define ILK_eDP_A_DISABLE (1<<24)
3425 #define ILK_DESKTOP (1<<23)
3426 #define ILK_DSPCLK_GATE 0x42020
3427 #define IVB_VRHUNIT_CLK_GATE (1<<28)
3428 #define ILK_DPARB_CLK_GATE (1<<5)
3429 #define ILK_DPFD_CLK_GATE (1<<7)
3431 /* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
3432 #define ILK_CLK_FBC (1<<7)
3433 #define ILK_DPFC_DIS1 (1<<8)
3434 #define ILK_DPFC_DIS2 (1<<9)
3436 #define IVB_CHICKEN3 0x4200c
3437 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
3438 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
3440 #define DISP_ARB_CTL 0x45000
3441 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
3442 #define DISP_FBC_WM_DIS (1<<15)
3444 /* GEN7 chicken */
3445 #define GEN7_COMMON_SLICE_CHICKEN1 0x7010
3446 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
3447 
3448 #define GEN7_L3CNTLREG1 0xB01C
3449 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C
3450 
3451 #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
3452 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
3454 /* WaCatErrorRejectionIssue */
3455 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
3456 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
3457 
3458 /* PCH */
3460 /* south display engine interrupt: IBX */
3461 #define SDE_AUDIO_POWER_D (1 << 27)
3462 #define SDE_AUDIO_POWER_C (1 << 26)
3463 #define SDE_AUDIO_POWER_B (1 << 25)
3464 #define SDE_AUDIO_POWER_SHIFT (25)
3465 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
3466 #define SDE_GMBUS (1 << 24)
3467 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
3468 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
3469 #define SDE_AUDIO_HDCP_MASK (3 << 22)
3470 #define SDE_AUDIO_TRANSB (1 << 21)
3471 #define SDE_AUDIO_TRANSA (1 << 20)
3472 #define SDE_AUDIO_TRANS_MASK (3 << 20)
3473 #define SDE_POISON (1 << 19)
3474 /* 18 reserved */
3475 #define SDE_FDI_RXB (1 << 17)
3476 #define SDE_FDI_RXA (1 << 16)
3477 #define SDE_FDI_MASK (3 << 16)
3478 #define SDE_AUXD (1 << 15)
3479 #define SDE_AUXC (1 << 14)
3480 #define SDE_AUXB (1 << 13)
3481 #define SDE_AUX_MASK (7 << 13)
3482 /* 12 reserved */
3483 #define SDE_CRT_HOTPLUG (1 << 11)
3484 #define SDE_PORTD_HOTPLUG (1 << 10)
3485 #define SDE_PORTC_HOTPLUG (1 << 9)
3486 #define SDE_PORTB_HOTPLUG (1 << 8)
3487 #define SDE_SDVOB_HOTPLUG (1 << 6)
3488 #define SDE_HOTPLUG_MASK (0xf << 8)
3489 #define SDE_TRANSB_CRC_DONE (1 << 5)
3490 #define SDE_TRANSB_CRC_ERR (1 << 4)
3491 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
3492 #define SDE_TRANSA_CRC_DONE (1 << 2)
3493 #define SDE_TRANSA_CRC_ERR (1 << 1)
3494 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
3495 #define SDE_TRANS_MASK (0x3f)
3497 /* south display engine interrupt: CPT/PPT */
3498 #define SDE_AUDIO_POWER_D_CPT (1 << 31)
3499 #define SDE_AUDIO_POWER_C_CPT (1 << 30)
3500 #define SDE_AUDIO_POWER_B_CPT (1 << 29)
3501 #define SDE_AUDIO_POWER_SHIFT_CPT 29
3502 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
3503 #define SDE_AUXD_CPT (1 << 27)
3504 #define SDE_AUXC_CPT (1 << 26)
3505 #define SDE_AUXB_CPT (1 << 25)
3506 #define SDE_AUX_MASK_CPT (7 << 25)
3507 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
3508 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
3509 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
3510 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
3511 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
3512  SDE_PORTD_HOTPLUG_CPT | \
3513  SDE_PORTC_HOTPLUG_CPT | \
3514  SDE_PORTB_HOTPLUG_CPT)
3515 #define SDE_GMBUS_CPT (1 << 17)
3516 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
3517 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
3518 #define SDE_FDI_RXC_CPT (1 << 8)
3519 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
3520 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
3521 #define SDE_FDI_RXB_CPT (1 << 4)
3522 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
3523 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
3524 #define SDE_FDI_RXA_CPT (1 << 0)
3525 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
3526  SDE_AUDIO_CP_REQ_B_CPT | \
3527  SDE_AUDIO_CP_REQ_A_CPT)
3528 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
3529  SDE_AUDIO_CP_CHG_B_CPT | \
3530  SDE_AUDIO_CP_CHG_A_CPT)
3531 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
3532  SDE_FDI_RXB_CPT | \
3533  SDE_FDI_RXA_CPT)
3535 #define SDEISR 0xc4000
3536 #define SDEIMR 0xc4004
3537 #define SDEIIR 0xc4008
3538 #define SDEIER 0xc400c
3540 /* digital port hotplug */
3541 #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
3542 #define PORTD_HOTPLUG_ENABLE (1 << 20)
3543 #define PORTD_PULSE_DURATION_2ms (0)
3544 #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
3545 #define PORTD_PULSE_DURATION_6ms (2 << 18)
3546 #define PORTD_PULSE_DURATION_100ms (3 << 18)
3547 #define PORTD_PULSE_DURATION_MASK (3 << 18)
3548 #define PORTD_HOTPLUG_NO_DETECT (0)
3549 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
3550 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
3551 #define PORTC_HOTPLUG_ENABLE (1 << 12)
3552 #define PORTC_PULSE_DURATION_2ms (0)
3553 #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
3554 #define PORTC_PULSE_DURATION_6ms (2 << 10)
3555 #define PORTC_PULSE_DURATION_100ms (3 << 10)
3556 #define PORTC_PULSE_DURATION_MASK (3 << 10)
3557 #define PORTC_HOTPLUG_NO_DETECT (0)
3558 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
3559 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
3560 #define PORTB_HOTPLUG_ENABLE (1 << 4)
3561 #define PORTB_PULSE_DURATION_2ms (0)
3562 #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
3563 #define PORTB_PULSE_DURATION_6ms (2 << 2)
3564 #define PORTB_PULSE_DURATION_100ms (3 << 2)
3565 #define PORTB_PULSE_DURATION_MASK (3 << 2)
3566 #define PORTB_HOTPLUG_NO_DETECT (0)
3567 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
3568 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
3570 #define PCH_GPIOA 0xc5010
3571 #define PCH_GPIOB 0xc5014
3572 #define PCH_GPIOC 0xc5018
3573 #define PCH_GPIOD 0xc501c
3574 #define PCH_GPIOE 0xc5020
3575 #define PCH_GPIOF 0xc5024
3577 #define PCH_GMBUS0 0xc5100
3578 #define PCH_GMBUS1 0xc5104
3579 #define PCH_GMBUS2 0xc5108
3580 #define PCH_GMBUS3 0xc510c
3581 #define PCH_GMBUS4 0xc5110
3582 #define PCH_GMBUS5 0xc5120
3584 #define _PCH_DPLL_A 0xc6014
3585 #define _PCH_DPLL_B 0xc6018
3586 #define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
3588 #define _PCH_FPA0 0xc6040
3589 #define FP_CB_TUNE (0x3<<22)
3590 #define _PCH_FPA1 0xc6044
3591 #define _PCH_FPB0 0xc6048
3592 #define _PCH_FPB1 0xc604c
3593 #define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
3594 #define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
3596 #define PCH_DPLL_TEST 0xc606c
3598 #define PCH_DREF_CONTROL 0xC6200
3599 #define DREF_CONTROL_MASK 0x7fc3
3600 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
3601 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
3602 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
3603 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
3604 #define DREF_SSC_SOURCE_DISABLE (0<<11)
3605 #define DREF_SSC_SOURCE_ENABLE (2<<11)
3606 #define DREF_SSC_SOURCE_MASK (3<<11)
3607 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
3608 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
3609 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
3610 #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
3611 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
3612 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
3613 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
3614 #define DREF_SSC4_DOWNSPREAD (0<<6)
3615 #define DREF_SSC4_CENTERSPREAD (1<<6)
3616 #define DREF_SSC1_DISABLE (0<<1)
3617 #define DREF_SSC1_ENABLE (1<<1)
3618 #define DREF_SSC4_DISABLE (0)
3619 #define DREF_SSC4_ENABLE (1)
3621 #define PCH_RAWCLK_FREQ 0xc6204
3622 #define FDL_TP1_TIMER_SHIFT 12
3623 #define FDL_TP1_TIMER_MASK (3<<12)
3624 #define FDL_TP2_TIMER_SHIFT 10
3625 #define FDL_TP2_TIMER_MASK (3<<10)
3626 #define RAWCLK_FREQ_MASK 0x3ff
3628 #define PCH_DPLL_TMR_CFG 0xc6208
3629 
3630 #define PCH_SSC4_PARMS 0xc6210
3631 #define PCH_SSC4_AUX_PARMS 0xc6214
3633 #define PCH_DPLL_SEL 0xc7000
3634 #define TRANSA_DPLL_ENABLE (1<<3)
3635 #define TRANSA_DPLLB_SEL (1<<0)
3636 #define TRANSA_DPLLA_SEL 0
3637 #define TRANSB_DPLL_ENABLE (1<<7)
3638 #define TRANSB_DPLLB_SEL (1<<4)
3639 #define TRANSB_DPLLA_SEL (0)
3640 #define TRANSC_DPLL_ENABLE (1<<11)
3641 #define TRANSC_DPLLB_SEL (1<<8)
3642 #define TRANSC_DPLLA_SEL (0)
3644 /* transcoder */
3646 #define _TRANS_HTOTAL_A 0xe0000
3647 #define TRANS_HTOTAL_SHIFT 16
3648 #define TRANS_HACTIVE_SHIFT 0
3649 #define _TRANS_HBLANK_A 0xe0004
3650 #define TRANS_HBLANK_END_SHIFT 16
3651 #define TRANS_HBLANK_START_SHIFT 0
3652 #define _TRANS_HSYNC_A 0xe0008
3653 #define TRANS_HSYNC_END_SHIFT 16
3654 #define TRANS_HSYNC_START_SHIFT 0
3655 #define _TRANS_VTOTAL_A 0xe000c
3656 #define TRANS_VTOTAL_SHIFT 16
3657 #define TRANS_VACTIVE_SHIFT 0
3658 #define _TRANS_VBLANK_A 0xe0010
3659 #define TRANS_VBLANK_END_SHIFT 16
3660 #define TRANS_VBLANK_START_SHIFT 0
3661 #define _TRANS_VSYNC_A 0xe0014
3662 #define TRANS_VSYNC_END_SHIFT 16
3663 #define TRANS_VSYNC_START_SHIFT 0
3664 #define _TRANS_VSYNCSHIFT_A 0xe0028
3666 #define _TRANSA_DATA_M1 0xe0030
3667 #define _TRANSA_DATA_N1 0xe0034
3668 #define _TRANSA_DATA_M2 0xe0038
3669 #define _TRANSA_DATA_N2 0xe003c
3670 #define _TRANSA_DP_LINK_M1 0xe0040
3671 #define _TRANSA_DP_LINK_N1 0xe0044
3672 #define _TRANSA_DP_LINK_M2 0xe0048
3673 #define _TRANSA_DP_LINK_N2 0xe004c
3675 /* Per-transcoder DIP controls */
3677 #define _VIDEO_DIP_CTL_A 0xe0200
3678 #define _VIDEO_DIP_DATA_A 0xe0208
3679 #define _VIDEO_DIP_GCP_A 0xe0210
3681 #define _VIDEO_DIP_CTL_B 0xe1200
3682 #define _VIDEO_DIP_DATA_B 0xe1208
3683 #define _VIDEO_DIP_GCP_B 0xe1210
3685 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
3686 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
3687 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
3689 #define VLV_VIDEO_DIP_CTL_A 0x60220
3690 #define VLV_VIDEO_DIP_DATA_A 0x60208
3691 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
3693 #define VLV_VIDEO_DIP_CTL_B 0x61170
3694 #define VLV_VIDEO_DIP_DATA_B 0x61174
3695 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178
3697 #define VLV_TVIDEO_DIP_CTL(pipe) \
3698  _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
3699 #define VLV_TVIDEO_DIP_DATA(pipe) \
3700  _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
3701 #define VLV_TVIDEO_DIP_GCP(pipe) \
3702  _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
3704 /* Haswell DIP controls */
3705 #define HSW_VIDEO_DIP_CTL_A 0x60200
3706 #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220
3707 #define HSW_VIDEO_DIP_VS_DATA_A 0x60260
3708 #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
3709 #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
3710 #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320
3711 #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240
3712 #define HSW_VIDEO_DIP_VS_ECC_A 0x60280
3713 #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
3714 #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300
3715 #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344
3716 #define HSW_VIDEO_DIP_GCP_A 0x60210
3718 #define HSW_VIDEO_DIP_CTL_B 0x61200
3719 #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220
3720 #define HSW_VIDEO_DIP_VS_DATA_B 0x61260
3721 #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
3722 #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
3723 #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320
3724 #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240
3725 #define HSW_VIDEO_DIP_VS_ECC_B 0x61280
3726 #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
3727 #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300
3728 #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344
3729 #define HSW_VIDEO_DIP_GCP_B 0x61210
3731 #define HSW_TVIDEO_DIP_CTL(pipe) \
3732  _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
3733 #define HSW_TVIDEO_DIP_AVI_DATA(pipe) \
3734  _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
3735 #define HSW_TVIDEO_DIP_SPD_DATA(pipe) \
3736  _PIPE(pipe, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B)
3737 #define HSW_TVIDEO_DIP_GCP(pipe) \
3738  _PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
3740 #define _TRANS_HTOTAL_B 0xe1000
3741 #define _TRANS_HBLANK_B 0xe1004
3742 #define _TRANS_HSYNC_B 0xe1008
3743 #define _TRANS_VTOTAL_B 0xe100c
3744 #define _TRANS_VBLANK_B 0xe1010
3745 #define _TRANS_VSYNC_B 0xe1014
3746 #define _TRANS_VSYNCSHIFT_B 0xe1028
3748 #define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
3749 #define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
3750 #define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
3751 #define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
3752 #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
3753 #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
3754 #define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \
3755  _TRANS_VSYNCSHIFT_B)
3757 #define _TRANSB_DATA_M1 0xe1030
3758 #define _TRANSB_DATA_N1 0xe1034
3759 #define _TRANSB_DATA_M2 0xe1038
3760 #define _TRANSB_DATA_N2 0xe103c
3761 #define _TRANSB_DP_LINK_M1 0xe1040
3762 #define _TRANSB_DP_LINK_N1 0xe1044
3763 #define _TRANSB_DP_LINK_M2 0xe1048
3764 #define _TRANSB_DP_LINK_N2 0xe104c
3766 #define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
3767 #define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
3768 #define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
3769 #define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
3770 #define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
3771 #define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
3772 #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
3773 #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
3775 #define _TRANSACONF 0xf0008
3776 #define _TRANSBCONF 0xf1008
3777 #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
3778 #define TRANS_DISABLE (0<<31)
3779 #define TRANS_ENABLE (1<<31)
3780 #define TRANS_STATE_MASK (1<<30)
3781 #define TRANS_STATE_DISABLE (0<<30)
3782 #define TRANS_STATE_ENABLE (1<<30)
3783 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
3784 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
3785 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
3786 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
3787 #define TRANS_DP_AUDIO_ONLY (1<<26)
3788 #define TRANS_DP_VIDEO_AUDIO (0<<26)
3789 #define TRANS_INTERLACE_MASK (7<<21)
3790 #define TRANS_PROGRESSIVE (0<<21)
3791 #define TRANS_INTERLACED (3<<21)
3792 #define TRANS_LEGACY_INTERLACED_ILK (2<<21)
3793 #define TRANS_8BPC (0<<5)
3794 #define TRANS_10BPC (1<<5)
3795 #define TRANS_6BPC (2<<5)
3796 #define TRANS_12BPC (3<<5)
3798 #define _TRANSA_CHICKEN2 0xf0064
3799 #define _TRANSB_CHICKEN2 0xf1064
3800 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
3801 #define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
3803 #define SOUTH_CHICKEN1 0xc2000
3804 #define FDIA_PHASE_SYNC_SHIFT_OVR 19
3805 #define FDIA_PHASE_SYNC_SHIFT_EN 18
3806 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
3807 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
3808 #define SOUTH_CHICKEN2 0xc2004
3809 #define DPLS_EDP_PPS_FIX_DIS (1<<0)
3811 #define _FDI_RXA_CHICKEN 0xc200c
3812 #define _FDI_RXB_CHICKEN 0xc2010
3813 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
3814 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
3815 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
3816 
3817 #define SOUTH_DSPCLK_GATE_D 0xc2020
3818 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
3820 /* CPU: FDI_TX */
3821 #define _FDI_TXA_CTL 0x60100
3822 #define _FDI_TXB_CTL 0x61100
3823 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
3824 #define FDI_TX_DISABLE (0<<31)
3825 #define FDI_TX_ENABLE (1<<31)
3826 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
3827 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
3828 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
3829 #define FDI_LINK_TRAIN_NONE (3<<28)
3830 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
3831 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
3832 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
3833 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
3834 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
3835 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
3836 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
3837 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
3838 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
3839  SNB has different settings. */
3840 /* SNB A-stepping */
3841 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3842 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3843 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3844 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3845 /* SNB B-stepping */
3846 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
3847 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
3848 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
3849 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
3850 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
3851 #define FDI_DP_PORT_WIDTH_X1 (0<<19)
3852 #define FDI_DP_PORT_WIDTH_X2 (1<<19)
3853 #define FDI_DP_PORT_WIDTH_X3 (2<<19)
3854 #define FDI_DP_PORT_WIDTH_X4 (3<<19)
3855 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
3856 /* Ironlake: hardwired to 1 */
3857 #define FDI_TX_PLL_ENABLE (1<<14)
3859 /* Ivybridge has different bits for lolz */
3860 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
3861 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
3862 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
3863 #define FDI_LINK_TRAIN_NONE_IVB (3<<8)
3865 /* both Tx and Rx */
3866 #define FDI_COMPOSITE_SYNC (1<<11)
3867 #define FDI_LINK_TRAIN_AUTO (1<<10)
3868 #define FDI_SCRAMBLING_ENABLE (0<<7)
3869 #define FDI_SCRAMBLING_DISABLE (1<<7)
3871 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
3872 #define _FDI_RXA_CTL 0xf000c
3873 #define _FDI_RXB_CTL 0xf100c
3874 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
3875 #define FDI_RX_ENABLE (1<<31)
3876 /* train, dp width same as FDI_TX */
3877 #define FDI_FS_ERRC_ENABLE (1<<27)
3878 #define FDI_FE_ERRC_ENABLE (1<<26)
3879 #define FDI_DP_PORT_WIDTH_X8 (7<<19)
3880 #define FDI_8BPC (0<<16)
3881 #define FDI_10BPC (1<<16)
3882 #define FDI_6BPC (2<<16)
3883 #define FDI_12BPC (3<<16)
3884 #define FDI_LINK_REVERSE_OVERWRITE (1<<15)
3885 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
3886 #define FDI_RX_PLL_ENABLE (1<<13)
3887 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
3888 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
3889 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
3890 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
3891 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
3892 #define FDI_PCDCLK (1<<4)
3893 /* CPT */
3894 #define FDI_AUTO_TRAINING (1<<10)
3895 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
3896 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
3897 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
3898 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
3899 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
3900 /* LPT */
3901 #define FDI_PORT_WIDTH_2X_LPT (1<<19)
3902 #define FDI_PORT_WIDTH_1X_LPT (0<<19)
3904 #define _FDI_RXA_MISC 0xf0010
3905 #define _FDI_RXB_MISC 0xf1010
3906 #define _FDI_RXA_TUSIZE1 0xf0030
3907 #define _FDI_RXA_TUSIZE2 0xf0038
3908 #define _FDI_RXB_TUSIZE1 0xf1030
3909 #define _FDI_RXB_TUSIZE2 0xf1038
3910 #define FDI_RX_TP1_TO_TP2_48 (2<<20)
3911 #define FDI_RX_TP1_TO_TP2_64 (3<<20)
3912 #define FDI_RX_FDI_DELAY_90 (0x90<<0)
3913 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
3914 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
3915 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
3917 /* FDI_RX interrupt register format */
3918 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
3919 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
3920 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
3921 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
3922 #define FDI_RX_FS_CODE_ERR (1<<6)
3923 #define FDI_RX_FE_CODE_ERR (1<<5)
3924 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
3925 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
3926 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
3927 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
3928 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
3930 #define _FDI_RXA_IIR 0xf0014
3931 #define _FDI_RXA_IMR 0xf0018
3932 #define _FDI_RXB_IIR 0xf1014
3933 #define _FDI_RXB_IMR 0xf1018
3934 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
3935 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
3936 
3937 #define FDI_PLL_CTL_1 0xfe000
3938 #define FDI_PLL_CTL_2 0xfe004
3940 /* or SDVOB */
3941 #define HDMIB 0xe1140
3942 #define PORT_ENABLE (1 << 31)
3943 #define TRANSCODER(pipe) ((pipe) << 30)
3944 #define TRANSCODER_CPT(pipe) ((pipe) << 29)
3945 #define TRANSCODER_MASK (1 << 30)
3946 #define TRANSCODER_MASK_CPT (3 << 29)
3947 #define COLOR_FORMAT_8bpc (0)
3948 #define COLOR_FORMAT_12bpc (3 << 26)
3949 #define SDVOB_HOTPLUG_ENABLE (1 << 23)
3950 #define SDVO_ENCODING (0)
3951 #define TMDS_ENCODING (2 << 10)
3952 #define NULL_PACKET_VSYNC_ENABLE (1 << 9)
3953 /* CPT */
3954 #define HDMI_MODE_SELECT (1 << 9)
3955 #define DVI_MODE_SELECT (0)
3956 #define SDVOB_BORDER_ENABLE (1 << 7)
3957 #define AUDIO_ENABLE (1 << 6)
3958 #define VSYNC_ACTIVE_HIGH (1 << 4)
3959 #define HSYNC_ACTIVE_HIGH (1 << 3)
3960 #define PORT_DETECTED (1 << 2)
3961 
3962 /* PCH SDVOB multiplex with HDMIB */
3963 #define PCH_SDVOB HDMIB
3964 
3965 #define HDMIC 0xe1150
3966 #define HDMID 0xe1160
3967 
3968 #define PCH_LVDS 0xe1180
3969 #define LVDS_DETECTED (1 << 1)
3971 /* vlv has 2 sets of panel control regs. */
3972 #define PIPEA_PP_STATUS 0x61200
3973 #define PIPEA_PP_CONTROL 0x61204
3974 #define PIPEA_PP_ON_DELAYS 0x61208
3975 #define PIPEA_PP_OFF_DELAYS 0x6120c
3976 #define PIPEA_PP_DIVISOR 0x61210
3978 #define PIPEB_PP_STATUS 0x61300
3979 #define PIPEB_PP_CONTROL 0x61304
3980 #define PIPEB_PP_ON_DELAYS 0x61308
3981 #define PIPEB_PP_OFF_DELAYS 0x6130c
3982 #define PIPEB_PP_DIVISOR 0x61310
3984 #define PCH_PP_STATUS 0xc7200
3985 #define PCH_PP_CONTROL 0xc7204
3986 #define PANEL_UNLOCK_REGS (0xabcd << 16)
3987 #define PANEL_UNLOCK_MASK (0xffff << 16)
3988 #define EDP_FORCE_VDD (1 << 3)
3989 #define EDP_BLC_ENABLE (1 << 2)
3990 #define PANEL_POWER_RESET (1 << 1)
3991 #define PANEL_POWER_OFF (0 << 0)
3992 #define PANEL_POWER_ON (1 << 0)
3993 #define PCH_PP_ON_DELAYS 0xc7208
3994 #define PANEL_PORT_SELECT_MASK (3 << 30)
3995 #define PANEL_PORT_SELECT_LVDS (0 << 30)
3996 #define PANEL_PORT_SELECT_DPA (1 << 30)
3997 #define EDP_PANEL (1 << 30)
3998 #define PANEL_PORT_SELECT_DPC (2 << 30)
3999 #define PANEL_PORT_SELECT_DPD (3 << 30)
4000 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
4001 #define PANEL_POWER_UP_DELAY_SHIFT 16
4002 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
4003 #define PANEL_LIGHT_ON_DELAY_SHIFT 0
4005 #define PCH_PP_OFF_DELAYS 0xc720c
4006 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
4007 #define PANEL_POWER_DOWN_DELAY_SHIFT 16
4008 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
4009 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0
4011 #define PCH_PP_DIVISOR 0xc7210
4012 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
4013 #define PP_REFERENCE_DIVIDER_SHIFT 8
4014 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
4015 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
4017 #define PCH_DP_B 0xe4100
4018 #define PCH_DPB_AUX_CH_CTL 0xe4110
4019 #define PCH_DPB_AUX_CH_DATA1 0xe4114
4020 #define PCH_DPB_AUX_CH_DATA2 0xe4118
4021 #define PCH_DPB_AUX_CH_DATA3 0xe411c
4022 #define PCH_DPB_AUX_CH_DATA4 0xe4120
4023 #define PCH_DPB_AUX_CH_DATA5 0xe4124
4025 #define PCH_DP_C 0xe4200
4026 #define PCH_DPC_AUX_CH_CTL 0xe4210
4027 #define PCH_DPC_AUX_CH_DATA1 0xe4214
4028 #define PCH_DPC_AUX_CH_DATA2 0xe4218
4029 #define PCH_DPC_AUX_CH_DATA3 0xe421c
4030 #define PCH_DPC_AUX_CH_DATA4 0xe4220
4031 #define PCH_DPC_AUX_CH_DATA5 0xe4224
4033 #define PCH_DP_D 0xe4300
4034 #define PCH_DPD_AUX_CH_CTL 0xe4310
4035 #define PCH_DPD_AUX_CH_DATA1 0xe4314
4036 #define PCH_DPD_AUX_CH_DATA2 0xe4318
4037 #define PCH_DPD_AUX_CH_DATA3 0xe431c
4038 #define PCH_DPD_AUX_CH_DATA4 0xe4320
4039 #define PCH_DPD_AUX_CH_DATA5 0xe4324
4041 /* CPT */
4042 #define PORT_TRANS_A_SEL_CPT 0
4043 #define PORT_TRANS_B_SEL_CPT (1<<29)
4044 #define PORT_TRANS_C_SEL_CPT (2<<29)
4045 #define PORT_TRANS_SEL_MASK (3<<29)
4046 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
4047 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
4048 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
4050 #define TRANS_DP_CTL_A 0xe0300
4051 #define TRANS_DP_CTL_B 0xe1300
4052 #define TRANS_DP_CTL_C 0xe2300
4053 #define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000)
4054 #define TRANS_DP_OUTPUT_ENABLE (1<<31)
4055 #define TRANS_DP_PORT_SEL_B (0<<29)
4056 #define TRANS_DP_PORT_SEL_C (1<<29)
4057 #define TRANS_DP_PORT_SEL_D (2<<29)
4058 #define TRANS_DP_PORT_SEL_NONE (3<<29)
4059 #define TRANS_DP_PORT_SEL_MASK (3<<29)
4060 #define TRANS_DP_AUDIO_ONLY (1<<26)
4061 #define TRANS_DP_ENH_FRAMING (1<<18)
4062 #define TRANS_DP_8BPC (0<<9)
4063 #define TRANS_DP_10BPC (1<<9)
4064 #define TRANS_DP_6BPC (2<<9)
4065 #define TRANS_DP_12BPC (3<<9)
4066 #define TRANS_DP_BPC_MASK (3<<9)
4067 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
4068 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
4069 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
4070 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
4071 #define TRANS_DP_SYNC_MASK (3<<3)
4073 /* SNB eDP training params */
4074 /* SNB A-stepping */
4075 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
4076 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
4077 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
4078 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
4079 /* SNB B-stepping */
4080 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
4081 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
4082 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
4083 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
4084 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
4085 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
4087 /* IVB */
4088 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
4089 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
4090 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
4091 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
4092 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
4093 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
4094 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x33 <<22)
4096 /* legacy values */
4097 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
4098 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
4099 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
4100 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
4101 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
4103 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
4105 #define FORCEWAKE 0xA18C
4106 #define FORCEWAKE_VLV 0x1300b0
4107 #define FORCEWAKE_ACK_VLV 0x1300b4
4108 #define FORCEWAKE_ACK_HSW 0x130044
4109 #define FORCEWAKE_ACK 0x130090
4110 #define FORCEWAKE_MT 0xa188 /* multi-threaded */
4111 #define FORCEWAKE_MT_ACK 0x130040
4112 #define ECOBUS 0xa180
4113 #define FORCEWAKE_MT_ENABLE (1<<5)
4115 #define GTFIFODBG 0x120000
4116 #define GT_FIFO_CPU_ERROR_MASK 7
4117 #define GT_FIFO_OVFERR (1<<2)
4118 #define GT_FIFO_IAWRERR (1<<1)
4119 #define GT_FIFO_IARDERR (1<<0)
4120 
4121 #define GT_FIFO_FREE_ENTRIES 0x120008
4122 #define GT_FIFO_NUM_RESERVED_ENTRIES 20
4124 #define GEN6_UCGCTL1 0x9400
4125 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
4126 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
4128 #define GEN6_UCGCTL2 0x9404
4129 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
4130 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
4131 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
4132 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
4133 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
4134 
4135 #define GEN7_UCGCTL4 0x940c
4136 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
4138 #define GEN6_RPNSWREQ 0xA008
4139 #define GEN6_TURBO_DISABLE (1<<31)
4140 #define GEN6_FREQUENCY(x) ((x)<<25)
4141 #define GEN6_OFFSET(x) ((x)<<19)
4142 #define GEN6_AGGRESSIVE_TURBO (0<<15)
4143 #define GEN6_RC_VIDEO_FREQ 0xA00C
4144 #define GEN6_RC_CONTROL 0xA090
4145 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
4146 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
4147 #define GEN6_RC_CTL_RC6_ENABLE (1<<18)
4148 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
4149 #define GEN6_RC_CTL_RC7_ENABLE (1<<22)
4150 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
4151 #define GEN6_RC_CTL_HW_ENABLE (1<<31)
4152 #define GEN6_RP_DOWN_TIMEOUT 0xA010
4153 #define GEN6_RP_INTERRUPT_LIMITS 0xA014
4154 #define GEN6_RPSTAT1 0xA01C
4155 #define GEN6_CAGF_SHIFT 8
4156 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
4157 #define GEN6_RP_CONTROL 0xA024
4158 #define GEN6_RP_MEDIA_TURBO (1<<11)
4159 #define GEN6_RP_MEDIA_MODE_MASK (3<<9)
4160 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
4161 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
4162 #define GEN6_RP_MEDIA_HW_MODE (1<<9)
4163 #define GEN6_RP_MEDIA_SW_MODE (0<<9)
4164 #define GEN6_RP_MEDIA_IS_GFX (1<<8)
4165 #define GEN6_RP_ENABLE (1<<7)
4166 #define GEN6_RP_UP_IDLE_MIN (0x1<<3)
4167 #define GEN6_RP_UP_BUSY_AVG (0x2<<3)
4168 #define GEN6_RP_UP_BUSY_CONT (0x4<<3)
4169 #define GEN7_RP_DOWN_IDLE_AVG (0x2<<0)
4170 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
4171 #define GEN6_RP_UP_THRESHOLD 0xA02C
4172 #define GEN6_RP_DOWN_THRESHOLD 0xA030
4173 #define GEN6_RP_CUR_UP_EI 0xA050
4174 #define GEN6_CURICONT_MASK 0xffffff
4175 #define GEN6_RP_CUR_UP 0xA054
4176 #define GEN6_CURBSYTAVG_MASK 0xffffff
4177 #define GEN6_RP_PREV_UP 0xA058
4178 #define GEN6_RP_CUR_DOWN_EI 0xA05C
4179 #define GEN6_CURIAVG_MASK 0xffffff
4180 #define GEN6_RP_CUR_DOWN 0xA060
4181 #define GEN6_RP_PREV_DOWN 0xA064
4182 #define GEN6_RP_UP_EI 0xA068
4183 #define GEN6_RP_DOWN_EI 0xA06C
4184 #define GEN6_RP_IDLE_HYSTERSIS 0xA070
4185 #define GEN6_RC_STATE 0xA094
4186 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
4187 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
4188 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
4189 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
4190 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
4191 #define GEN6_RC_SLEEP 0xA0B0
4192 #define GEN6_RC1e_THRESHOLD 0xA0B4
4193 #define GEN6_RC6_THRESHOLD 0xA0B8
4194 #define GEN6_RC6p_THRESHOLD 0xA0BC
4195 #define GEN6_RC6pp_THRESHOLD 0xA0C0
4196 #define GEN6_PMINTRMSK 0xA168
4198 #define GEN6_PMISR 0x44020
4199 #define GEN6_PMIMR 0x44024 /* rps_lock */
4200 #define GEN6_PMIIR 0x44028
4201 #define GEN6_PMIER 0x4402C
4202 #define GEN6_PM_MBOX_EVENT (1<<25)
4203 #define GEN6_PM_THERMAL_EVENT (1<<24)
4204 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
4205 #define GEN6_PM_RP_UP_THRESHOLD (1<<5)
4206 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
4207 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
4208 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
4209 #define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
4210  GEN6_PM_RP_DOWN_THRESHOLD | \
4211  GEN6_PM_RP_DOWN_TIMEOUT)
4213 #define GEN6_GT_GFX_RC6_LOCKED 0x138104
4214 #define GEN6_GT_GFX_RC6 0x138108
4215 #define GEN6_GT_GFX_RC6p 0x13810C
4216 #define GEN6_GT_GFX_RC6pp 0x138110
4218 #define GEN6_PCODE_MAILBOX 0x138124
4219 #define GEN6_PCODE_READY (1<<31)
4220 #define GEN6_READ_OC_PARAMS 0xc
4221 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
4222 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
4223 #define GEN6_PCODE_DATA 0x138128
4224 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
4226 #define GEN6_GT_CORE_STATUS 0x138060
4227 #define GEN6_CORE_CPD_STATE_MASK (7<<4)
4228 #define GEN6_RCn_MASK 7
4229 #define GEN6_RC0 0
4230 #define GEN6_RC3 2
4231 #define GEN6_RC6 3
4232 #define GEN6_RC7 4
4233 
4234 #define GEN7_MISCCPCTL (0x9424)
4235 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
4237 /* IVYBRIDGE DPF */
4238 #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
4239 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
4240 #define GEN7_PARITY_ERROR_VALID (1<<13)
4241 #define GEN7_L3CDERRST1_BANK_MASK (3<<11)
4242 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
4243 #define GEN7_PARITY_ERROR_ROW(reg) \
4244  ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
4245 #define GEN7_PARITY_ERROR_BANK(reg) \
4246  ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
4247 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
4248  ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
4249 #define GEN7_L3CDERRST1_ENABLE (1<<7)
4250 
4251 #define GEN7_L3LOG_BASE 0xB070
4252 #define GEN7_L3LOG_SIZE 0x80
4254 #define G4X_AUD_VID_DID 0x62020
4255 #define INTEL_AUDIO_DEVCL 0x808629FB
4256 #define INTEL_AUDIO_DEVBLC 0x80862801
4257 #define INTEL_AUDIO_DEVCTG 0x80862802
4259 #define G4X_AUD_CNTL_ST 0x620B4
4260 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
4261 #define G4X_ELDV_DEVCTG (1 << 14)
4262 #define G4X_ELD_ADDR (0xf << 5)
4263 #define G4X_ELD_ACK (1 << 4)
4264 #define G4X_HDMIW_HDMIEDID 0x6210C
4266 #define IBX_HDMIW_HDMIEDID_A 0xE2050
4267 #define IBX_HDMIW_HDMIEDID_B 0xE2150
4268 #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
4269  IBX_HDMIW_HDMIEDID_A, \
4270  IBX_HDMIW_HDMIEDID_B)
4271 #define IBX_AUD_CNTL_ST_A 0xE20B4
4272 #define IBX_AUD_CNTL_ST_B 0xE21B4
4273 #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
4274  IBX_AUD_CNTL_ST_A, \
4275  IBX_AUD_CNTL_ST_B)
4276 #define IBX_ELD_BUFFER_SIZE (0x1f << 10)
4277 #define IBX_ELD_ADDRESS (0x1f << 5)
4278 #define IBX_ELD_ACK (1 << 4)
4279 #define IBX_AUD_CNTL_ST2 0xE20C0
4280 #define IBX_ELD_VALIDB (1 << 0)
4281 #define IBX_CP_READYB (1 << 1)
4283 #define CPT_HDMIW_HDMIEDID_A 0xE5050
4284 #define CPT_HDMIW_HDMIEDID_B 0xE5150
4285 #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
4286  CPT_HDMIW_HDMIEDID_A, \
4287  CPT_HDMIW_HDMIEDID_B)
4288 #define CPT_AUD_CNTL_ST_A 0xE50B4
4289 #define CPT_AUD_CNTL_ST_B 0xE51B4
4290 #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
4291  CPT_AUD_CNTL_ST_A, \
4292  CPT_AUD_CNTL_ST_B)
4293 #define CPT_AUD_CNTRL_ST2 0xE50C0
4294 
4295 /* These are the 4 32-bit write offset registers for each stream
4296  * output buffer. It determines the offset from the
4297  * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
4298  */
4299 #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
4301 #define IBX_AUD_CONFIG_A 0xe2000
4302 #define IBX_AUD_CONFIG_B 0xe2100
4303 #define IBX_AUD_CFG(pipe) _PIPE(pipe, \
4304  IBX_AUD_CONFIG_A, \
4305  IBX_AUD_CONFIG_B)
4306 #define CPT_AUD_CONFIG_A 0xe5000
4307 #define CPT_AUD_CONFIG_B 0xe5100
4308 #define CPT_AUD_CFG(pipe) _PIPE(pipe, \
4309  CPT_AUD_CONFIG_A, \
4310  CPT_AUD_CONFIG_B)
4311 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
4312 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
4313 #define AUD_CONFIG_UPPER_N_SHIFT 20
4314 #define AUD_CONFIG_UPPER_N_VALUE (0xff << 20)
4315 #define AUD_CONFIG_LOWER_N_SHIFT 4
4316 #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
4317 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
4318 #define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16)
4319 #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
4321 /* HSW Audio */
4322 #define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */
4323 #define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */
4324 #define HSW_AUD_CFG(pipe) _PIPE(pipe, \
4325  HSW_AUD_CONFIG_A, \
4326  HSW_AUD_CONFIG_B)
4328 #define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */
4329 #define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */
4330 #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
4331  HSW_AUD_MISC_CTRL_A, \
4332  HSW_AUD_MISC_CTRL_B)
4334 #define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */
4335 #define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */
4336 #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
4337  HSW_AUD_DIP_ELD_CTRL_ST_A, \
4338  HSW_AUD_DIP_ELD_CTRL_ST_B)
4340 /* Audio Digital Converter */
4341 #define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */
4342 #define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */
4343 #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
4344  HSW_AUD_DIG_CNVT_1, \
4345  HSW_AUD_DIG_CNVT_2)
4346 #define DIP_PORT_SEL_MASK 0x3
4348 #define HSW_AUD_EDID_DATA_A 0x65050
4349 #define HSW_AUD_EDID_DATA_B 0x65150
4350 #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
4351  HSW_AUD_EDID_DATA_A, \
4352  HSW_AUD_EDID_DATA_B)
4354 #define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */
4355 #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */
4356 #define AUDIO_INACTIVE_C (1<<11)
4357 #define AUDIO_INACTIVE_B (1<<7)
4358 #define AUDIO_INACTIVE_A (1<<3)
4359 #define AUDIO_OUTPUT_ENABLE_A (1<<2)
4360 #define AUDIO_OUTPUT_ENABLE_B (1<<6)
4361 #define AUDIO_OUTPUT_ENABLE_C (1<<10)
4362 #define AUDIO_ELD_VALID_A (1<<0)
4363 #define AUDIO_ELD_VALID_B (1<<4)
4364 #define AUDIO_ELD_VALID_C (1<<8)
4365 #define AUDIO_CP_READY_A (1<<1)
4366 #define AUDIO_CP_READY_B (1<<5)
4367 #define AUDIO_CP_READY_C (1<<9)
4369 /* HSW Power Wells */
4370 #define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */
4371 #define HSW_PWR_WELL_CTL2 0x45404 /* Driver */
4372 #define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */
4373 #define HSW_PWR_WELL_CTL4 0x4540C /* Debug */
4374 #define HSW_PWR_WELL_ENABLE (1<<31)
4375 #define HSW_PWR_WELL_STATE (1<<30)
4376 #define HSW_PWR_WELL_CTL5 0x45410
4377 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
4378 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
4379 #define HSW_PWR_WELL_FORCE_ON (1<<19)
4380 #define HSW_PWR_WELL_CTL6 0x45414
4382 /* Per-pipe DDI Function Control */
4383 #define PIPE_DDI_FUNC_CTL_A 0x60400
4384 #define PIPE_DDI_FUNC_CTL_B 0x61400
4385 #define PIPE_DDI_FUNC_CTL_C 0x62400
4386 #define PIPE_DDI_FUNC_CTL_EDP 0x6F400
4387 #define DDI_FUNC_CTL(pipe) _PIPE(pipe, PIPE_DDI_FUNC_CTL_A, \
4388  PIPE_DDI_FUNC_CTL_B)
4389 #define PIPE_DDI_FUNC_ENABLE (1<<31)
4390 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
4391 #define PIPE_DDI_PORT_MASK (7<<28)
4392 #define PIPE_DDI_SELECT_PORT(x) ((x)<<28)
4393 #define PIPE_DDI_MODE_SELECT_MASK (7<<24)
4394 #define PIPE_DDI_MODE_SELECT_HDMI (0<<24)
4395 #define PIPE_DDI_MODE_SELECT_DVI (1<<24)
4396 #define PIPE_DDI_MODE_SELECT_DP_SST (2<<24)
4397 #define PIPE_DDI_MODE_SELECT_DP_MST (3<<24)
4398 #define PIPE_DDI_MODE_SELECT_FDI (4<<24)
4399 #define PIPE_DDI_BPC_MASK (7<<20)
4400 #define PIPE_DDI_BPC_8 (0<<20)
4401 #define PIPE_DDI_BPC_10 (1<<20)
4402 #define PIPE_DDI_BPC_6 (2<<20)
4403 #define PIPE_DDI_BPC_12 (3<<20)
4404 #define PIPE_DDI_PVSYNC (1<<17)
4405 #define PIPE_DDI_PHSYNC (1<<16)
4406 #define PIPE_DDI_BFI_ENABLE (1<<4)
4407 #define PIPE_DDI_PORT_WIDTH_X1 (0<<1)
4408 #define PIPE_DDI_PORT_WIDTH_X2 (1<<1)
4409 #define PIPE_DDI_PORT_WIDTH_X4 (3<<1)
4411 /* DisplayPort Transport Control */
4412 #define DP_TP_CTL_A 0x64040
4413 #define DP_TP_CTL_B 0x64140
4414 #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
4415 #define DP_TP_CTL_ENABLE (1<<31)
4416 #define DP_TP_CTL_MODE_SST (0<<27)
4417 #define DP_TP_CTL_MODE_MST (1<<27)
4418 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
4419 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
4420 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
4421 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
4422 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
4423 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
4425 /* DisplayPort Transport Status */
4426 #define DP_TP_STATUS_A 0x64044
4427 #define DP_TP_STATUS_B 0x64144
4428 #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
4429 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
4431 /* DDI Buffer Control */
4432 #define DDI_BUF_CTL_A 0x64000
4433 #define DDI_BUF_CTL_B 0x64100
4434 #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
4435 #define DDI_BUF_CTL_ENABLE (1<<31)
4436 #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */
4437 #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
4438 #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */
4439 #define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */
4440 #define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */
4441 #define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */
4442 #define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */
4443 #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */
4444 #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
4445 #define DDI_BUF_EMP_MASK (0xf<<24)
4446 #define DDI_BUF_IS_IDLE (1<<7)
4447 #define DDI_PORT_WIDTH_X1 (0<<1)
4448 #define DDI_PORT_WIDTH_X2 (1<<1)
4449 #define DDI_PORT_WIDTH_X4 (3<<1)
4450 #define DDI_INIT_DISPLAY_DETECTED (1<<0)
4452 /* DDI Buffer Translations */
4453 #define DDI_BUF_TRANS_A 0x64E00
4454 #define DDI_BUF_TRANS_B 0x64E60
4455 #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
4456 
4457 /* Sideband Interface (SBI) is programmed indirectly, via
4458  * SBI_ADDR, which contains the register offset; and SBI_DATA,
4459  * which contains the payload */
4460 #define SBI_ADDR 0xC6000
4461 #define SBI_DATA 0xC6004
4462 #define SBI_CTL_STAT 0xC6008
4463 #define SBI_CTL_OP_CRRD (0x6<<8)
4464 #define SBI_CTL_OP_CRWR (0x7<<8)
4465 #define SBI_RESPONSE_FAIL (0x1<<1)
4466 #define SBI_RESPONSE_SUCCESS (0x0<<1)
4467 #define SBI_BUSY (0x1<<0)
4468 #define SBI_READY (0x0<<0)
4470 /* SBI offsets */
4471 #define SBI_SSCDIVINTPHASE6 0x0600
4472 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
4473 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
4474 #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
4475 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
4476 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
4477 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
4478 #define SBI_SSCCTL 0x020c
4479 #define SBI_SSCCTL6 0x060C
4480 #define SBI_SSCCTL_DISABLE (1<<0)
4481 #define SBI_SSCAUXDIV6 0x0610
4482 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
4483 #define SBI_DBUFF0 0x2a00
4485 /* LPT PIXCLK_GATE */
4486 #define PIXCLK_GATE 0xC6020
4487 #define PIXCLK_GATE_UNGATE (1<<0)
4488 #define PIXCLK_GATE_GATE (0<<0)
4490 /* SPLL */
4491 #define SPLL_CTL 0x46020
4492 #define SPLL_PLL_ENABLE (1<<31)
4493 #define SPLL_PLL_SCC (1<<28)
4494 #define SPLL_PLL_NON_SCC (2<<28)
4495 #define SPLL_PLL_FREQ_810MHz (0<<26)
4496 #define SPLL_PLL_FREQ_1350MHz (1<<26)
4498 /* WRPLL */
4499 #define WRPLL_CTL1 0x46040
4500 #define WRPLL_CTL2 0x46060
4501 #define WRPLL_PLL_ENABLE (1<<31)
4502 #define WRPLL_PLL_SELECT_SSC (0x01<<28)
4503 #define WRPLL_PLL_SELECT_NON_SCC (0x02<<28)
4504 #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
4505 /* WRPLL divider programming */
4506 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
4507 #define WRPLL_DIVIDER_POST(x) ((x)<<8)
4508 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
4510 /* Port clock selection */
4511 #define PORT_CLK_SEL_A 0x46100
4512 #define PORT_CLK_SEL_B 0x46104
4513 #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
4514 #define PORT_CLK_SEL_LCPLL_2700 (0<<29)
4515 #define PORT_CLK_SEL_LCPLL_1350 (1<<29)
4516 #define PORT_CLK_SEL_LCPLL_810 (2<<29)
4517 #define PORT_CLK_SEL_SPLL (3<<29)
4518 #define PORT_CLK_SEL_WRPLL1 (4<<29)
4519 #define PORT_CLK_SEL_WRPLL2 (5<<29)
4521 /* Pipe clock selection */
4522 #define PIPE_CLK_SEL_A 0x46140
4523 #define PIPE_CLK_SEL_B 0x46144
4524 #define PIPE_CLK_SEL(pipe) _PIPE(pipe, PIPE_CLK_SEL_A, PIPE_CLK_SEL_B)
4525 /* For each pipe, we need to select the corresponding port clock */
4526 #define PIPE_CLK_SEL_DISABLED (0x0<<29)
4527 #define PIPE_CLK_SEL_PORT(x) ((x+1)<<29)
4529 /* LCPLL Control */
4530 #define LCPLL_CTL 0x130040
4531 #define LCPLL_PLL_DISABLE (1<<31)
4532 #define LCPLL_PLL_LOCK (1<<30)
4533 #define LCPLL_CD_CLOCK_DISABLE (1<<25)
4534 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
4536 /* Pipe WM_LINETIME - watermark line time */
4537 #define PIPE_WM_LINETIME_A 0x45270
4538 #define PIPE_WM_LINETIME_B 0x45274
4539 #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
4540  PIPE_WM_LINETIME_B)
4541 #define PIPE_WM_LINETIME_MASK (0x1ff)
4542 #define PIPE_WM_LINETIME_TIME(x) ((x))
4543 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
4544 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
4546 /* SFUSE_STRAP */
4547 #define SFUSE_STRAP 0xc2014
4548 #define SFUSE_STRAP_DDIB_DETECTED (1<<2)
4549 #define SFUSE_STRAP_DDIC_DETECTED (1<<1)
4550 #define SFUSE_STRAP_DDID_DETECTED (1<<0)
4552 #define WM_DBG 0x45280
4553 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
4554 #define WM_DBG_DISALLOW_MAXFIFO (1<<1)
4555 #define WM_DBG_DISALLOW_SPRITE (1<<2)
4556 
4557 #endif /* _I915_REG_H_ */