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13 #ifndef __LINUX_MFD_SEC_IRQ_H
14 #define __LINUX_MFD_SEC_IRQ_H
39 #define S2MPS11_IRQ_PWRONF_MASK (1 << 0)
40 #define S2MPS11_IRQ_PWRONR_MASK (1 << 1)
41 #define S2MPS11_IRQ_JIGONBF_MASK (1 << 2)
42 #define S2MPS11_IRQ_JIGONBR_MASK (1 << 3)
43 #define S2MPS11_IRQ_ACOKBF_MASK (1 << 4)
44 #define S2MPS11_IRQ_ACOKBR_MASK (1 << 5)
45 #define S2MPS11_IRQ_PWRON1S_MASK (1 << 6)
46 #define S2MPS11_IRQ_MRB_MASK (1 << 7)
48 #define S2MPS11_IRQ_RTC60S_MASK (1 << 0)
49 #define S2MPS11_IRQ_RTCA1_MASK (1 << 1)
50 #define S2MPS11_IRQ_RTCA2_MASK (1 << 2)
51 #define S2MPS11_IRQ_SMPL_MASK (1 << 3)
52 #define S2MPS11_IRQ_RTC1S_MASK (1 << 4)
53 #define S2MPS11_IRQ_WTSR_MASK (1 << 5)
55 #define S2MPS11_IRQ_INT120C_MASK (1 << 0)
56 #define S2MPS11_IRQ_INT140C_MASK (1 << 1)
82 #define S5M8767_IRQ_PWRR_MASK (1 << 0)
83 #define S5M8767_IRQ_PWRF_MASK (1 << 1)
84 #define S5M8767_IRQ_PWR1S_MASK (1 << 3)
85 #define S5M8767_IRQ_JIGR_MASK (1 << 4)
86 #define S5M8767_IRQ_JIGF_MASK (1 << 5)
87 #define S5M8767_IRQ_LOWBAT2_MASK (1 << 6)
88 #define S5M8767_IRQ_LOWBAT1_MASK (1 << 7)
90 #define S5M8767_IRQ_MRB_MASK (1 << 2)
91 #define S5M8767_IRQ_DVSOK2_MASK (1 << 3)
92 #define S5M8767_IRQ_DVSOK3_MASK (1 << 4)
93 #define S5M8767_IRQ_DVSOK4_MASK (1 << 5)
95 #define S5M8767_IRQ_RTC60S_MASK (1 << 0)
96 #define S5M8767_IRQ_RTCA1_MASK (1 << 1)
97 #define S5M8767_IRQ_RTCA2_MASK (1 << 2)
98 #define S5M8767_IRQ_SMPL_MASK (1 << 3)
99 #define S5M8767_IRQ_RTC1S_MASK (1 << 4)
100 #define S5M8767_IRQ_WTSR_MASK (1 << 5)
128 #define S5M8763_IRQ_DCINF_MASK (1 << 2)
129 #define S5M8763_IRQ_DCINR_MASK (1 << 3)
130 #define S5M8763_IRQ_JIGF_MASK (1 << 4)
131 #define S5M8763_IRQ_JIGR_MASK (1 << 5)
132 #define S5M8763_IRQ_PWRONF_MASK (1 << 6)
133 #define S5M8763_IRQ_PWRONR_MASK (1 << 7)
135 #define S5M8763_IRQ_WTSREVNT_MASK (1 << 0)
136 #define S5M8763_IRQ_SMPLEVNT_MASK (1 << 1)
137 #define S5M8763_IRQ_ALARM1_MASK (1 << 2)
138 #define S5M8763_IRQ_ALARM0_MASK (1 << 3)
140 #define S5M8763_IRQ_ONKEY1S_MASK (1 << 0)
141 #define S5M8763_IRQ_TOPOFFR_MASK (1 << 2)
142 #define S5M8763_IRQ_DCINOVPR_MASK (1 << 3)
143 #define S5M8763_IRQ_CHGRSTF_MASK (1 << 4)
144 #define S5M8763_IRQ_DONER_MASK (1 << 5)
145 #define S5M8763_IRQ_CHGFAULT_MASK (1 << 7)
147 #define S5M8763_IRQ_LOBAT1_MASK (1 << 0)
148 #define S5M8763_IRQ_LOBAT2_MASK (1 << 1)
150 #define S5M8763_ENRAMP (1 << 4)