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mmc.h
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1 /*
2  * Header for MultiMediaCard (MMC)
3  *
4  * Copyright 2002 Hewlett-Packard Company
5  *
6  * Use consistent with the GNU GPL is permitted,
7  * provided that this copyright notice is
8  * preserved in its entirety in all copies and derived works.
9  *
10  * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
11  * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
12  * FITNESS FOR ANY PARTICULAR PURPOSE.
13  *
14  * Many thanks to Alessandro Rubini and Jonathan Corbet!
15  *
16  * Based strongly on code by:
17  *
18  * Author: Yong-iL Joh <[email protected]>
19  *
20  * Author: Andrew Christian
21  * 15 May 2002
22  */
23 
24 #ifndef LINUX_MMC_MMC_H
25 #define LINUX_MMC_MMC_H
26 
27 /* Standard MMC commands (4.1) type argument response */
28  /* class 1 */
29 #define MMC_GO_IDLE_STATE 0 /* bc */
30 #define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
31 #define MMC_ALL_SEND_CID 2 /* bcr R2 */
32 #define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
33 #define MMC_SET_DSR 4 /* bc [31:16] RCA */
34 #define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */
35 #define MMC_SWITCH 6 /* ac [31:0] See below R1b */
36 #define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
37 #define MMC_SEND_EXT_CSD 8 /* adtc R1 */
38 #define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
39 #define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
40 #define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
41 #define MMC_STOP_TRANSMISSION 12 /* ac R1b */
42 #define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
43 #define MMC_BUS_TEST_R 14 /* adtc R1 */
44 #define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
45 #define MMC_BUS_TEST_W 19 /* adtc R1 */
46 #define MMC_SPI_READ_OCR 58 /* spi spi_R3 */
47 #define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */
48 
49  /* class 2 */
50 #define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
51 #define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
52 #define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
53 #define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */
54 #define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */
55 
56  /* class 3 */
57 #define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
58 
59  /* class 4 */
60 #define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
61 #define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
62 #define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
63 #define MMC_PROGRAM_CID 26 /* adtc R1 */
64 #define MMC_PROGRAM_CSD 27 /* adtc R1 */
65 
66  /* class 6 */
67 #define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
68 #define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
69 #define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
70 
71  /* class 5 */
72 #define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
73 #define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
74 #define MMC_ERASE 38 /* ac R1b */
75 
76  /* class 9 */
77 #define MMC_FAST_IO 39 /* ac <Complex> R4 */
78 #define MMC_GO_IRQ_STATE 40 /* bcr R5 */
79 
80  /* class 7 */
81 #define MMC_LOCK_UNLOCK 42 /* adtc R1b */
82 
83  /* class 8 */
84 #define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
85 #define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */
86 
87 static inline bool mmc_op_multi(u32 opcode)
88 {
89  return opcode == MMC_WRITE_MULTIPLE_BLOCK ||
90  opcode == MMC_READ_MULTIPLE_BLOCK;
91 }
92 
93 /*
94  * MMC_SWITCH argument format:
95  *
96  * [31:26] Always 0
97  * [25:24] Access Mode
98  * [23:16] Location of target Byte in EXT_CSD
99  * [15:08] Value Byte
100  * [07:03] Always 0
101  * [02:00] Command Set
102  */
103 
104 /*
105  MMC status in R1, for native mode (SPI bits are different)
106  Type
107  e : error bit
108  s : status bit
109  r : detected and set for the actual command response
110  x : detected and set during command execution. the host must poll
111  the card by sending status command in order to read these bits.
112  Clear condition
113  a : according to the card state
114  b : always related to the previous command. Reception of
115  a valid command will clear it (with a delay of one command)
116  c : clear by read
117  */
118 
119 #define R1_OUT_OF_RANGE (1 << 31) /* er, c */
120 #define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
121 #define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
122 #define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
123 #define R1_ERASE_PARAM (1 << 27) /* ex, c */
124 #define R1_WP_VIOLATION (1 << 26) /* erx, c */
125 #define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
126 #define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
127 #define R1_COM_CRC_ERROR (1 << 23) /* er, b */
128 #define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
129 #define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
130 #define R1_CC_ERROR (1 << 20) /* erx, c */
131 #define R1_ERROR (1 << 19) /* erx, c */
132 #define R1_UNDERRUN (1 << 18) /* ex, c */
133 #define R1_OVERRUN (1 << 17) /* ex, c */
134 #define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
135 #define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
136 #define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
137 #define R1_ERASE_RESET (1 << 13) /* sr, c */
138 #define R1_STATUS(x) (x & 0xFFFFE000)
139 #define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
140 #define R1_READY_FOR_DATA (1 << 8) /* sx, a */
141 #define R1_SWITCH_ERROR (1 << 7) /* sx, c */
142 #define R1_EXCEPTION_EVENT (1 << 6) /* sx, a */
143 #define R1_APP_CMD (1 << 5) /* sr, c */
144 
145 #define R1_STATE_IDLE 0
146 #define R1_STATE_READY 1
147 #define R1_STATE_IDENT 2
148 #define R1_STATE_STBY 3
149 #define R1_STATE_TRAN 4
150 #define R1_STATE_DATA 5
151 #define R1_STATE_RCV 6
152 #define R1_STATE_PRG 7
153 #define R1_STATE_DIS 8
154 
155 /*
156  * MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS
157  * R1 is the low order byte; R2 is the next highest byte, when present.
158  */
159 #define R1_SPI_IDLE (1 << 0)
160 #define R1_SPI_ERASE_RESET (1 << 1)
161 #define R1_SPI_ILLEGAL_COMMAND (1 << 2)
162 #define R1_SPI_COM_CRC (1 << 3)
163 #define R1_SPI_ERASE_SEQ (1 << 4)
164 #define R1_SPI_ADDRESS (1 << 5)
165 #define R1_SPI_PARAMETER (1 << 6)
166 /* R1 bit 7 is always zero */
167 #define R2_SPI_CARD_LOCKED (1 << 8)
168 #define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */
169 #define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
170 #define R2_SPI_ERROR (1 << 10)
171 #define R2_SPI_CC_ERROR (1 << 11)
172 #define R2_SPI_CARD_ECC_ERROR (1 << 12)
173 #define R2_SPI_WP_VIOLATION (1 << 13)
174 #define R2_SPI_ERASE_PARAM (1 << 14)
175 #define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */
176 #define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
177 
178 /* These are unpacked versions of the actual responses */
179 
180 struct _mmc_csd {
181  u8 csd_structure;
182  u8 spec_vers;
183  u8 taac;
184  u8 nsac;
185  u8 tran_speed;
186  u16 ccc;
187  u8 read_bl_len;
188  u8 read_bl_partial;
189  u8 write_blk_misalign;
190  u8 read_blk_misalign;
191  u8 dsr_imp;
192  u16 c_size;
193  u8 vdd_r_curr_min;
194  u8 vdd_r_curr_max;
195  u8 vdd_w_curr_min;
196  u8 vdd_w_curr_max;
197  u8 c_size_mult;
198  union {
199  struct { /* MMC system specification version 3.1 */
200  u8 erase_grp_size;
201  u8 erase_grp_mult;
202  } v31;
203  struct { /* MMC system specification version 2.2 */
204  u8 sector_size;
205  u8 erase_grp_size;
206  } v22;
207  } erase;
208  u8 wp_grp_size;
209  u8 wp_grp_enable;
210  u8 default_ecc;
211  u8 r2w_factor;
212  u8 write_bl_len;
213  u8 write_bl_partial;
214  u8 file_format_grp;
215  u8 copy;
216  u8 perm_write_protect;
217  u8 tmp_write_protect;
218  u8 file_format;
219  u8 ecc;
220 };
221 
222 /*
223  * OCR bits are mostly in host.h
224  */
225 #define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */
226 
227 /*
228  * Card Command Classes (CCC)
229  */
230 #define CCC_BASIC (1<<0) /* (0) Basic protocol functions */
231  /* (CMD0,1,2,3,4,7,9,10,12,13,15) */
232  /* (and for SPI, CMD58,59) */
233 #define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */
234  /* (CMD11) */
235 #define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */
236  /* (CMD16,17,18) */
237 #define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */
238  /* (CMD20) */
239 #define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */
240  /* (CMD16,24,25,26,27) */
241 #define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */
242  /* (CMD32,33,34,35,36,37,38,39) */
243 #define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */
244  /* (CMD28,29,30) */
245 #define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */
246  /* (CMD16,CMD42) */
247 #define CCC_APP_SPEC (1<<8) /* (8) Application specific */
248  /* (CMD55,56,57,ACMD*) */
249 #define CCC_IO_MODE (1<<9) /* (9) I/O mode */
250  /* (CMD5,39,40,52,53) */
251 #define CCC_SWITCH (1<<10) /* (10) High speed switch */
252  /* (CMD6,34,35,36,37,50) */
253  /* (11) Reserved */
254  /* (CMD?) */
255 
256 /*
257  * CSD field definitions
258  */
259 
260 #define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
261 #define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
262 #define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */
263 #define CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */
264 
265 #define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */
266 #define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
267 #define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */
268 #define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */
269 #define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */
270 
271 /*
272  * EXT_CSD fields
273  */
274 
275 #define EXT_CSD_FLUSH_CACHE 32 /* W */
276 #define EXT_CSD_CACHE_CTRL 33 /* R/W */
277 #define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
278 #define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO */
279 #define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */
280 #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
281 #define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
282 #define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
283 #define EXT_CSD_HPI_MGMT 161 /* R/W */
284 #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
285 #define EXT_CSD_BKOPS_EN 163 /* R/W */
286 #define EXT_CSD_BKOPS_START 164 /* W */
287 #define EXT_CSD_SANITIZE_START 165 /* W */
288 #define EXT_CSD_WR_REL_PARAM 166 /* RO */
289 #define EXT_CSD_BOOT_WP 173 /* R/W */
290 #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
291 #define EXT_CSD_PART_CONFIG 179 /* R/W */
292 #define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
293 #define EXT_CSD_BUS_WIDTH 183 /* R/W */
294 #define EXT_CSD_HS_TIMING 185 /* R/W */
295 #define EXT_CSD_POWER_CLASS 187 /* R/W */
296 #define EXT_CSD_REV 192 /* RO */
297 #define EXT_CSD_STRUCTURE 194 /* RO */
298 #define EXT_CSD_CARD_TYPE 196 /* RO */
299 #define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */
300 #define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
301 #define EXT_CSD_PWR_CL_52_195 200 /* RO */
302 #define EXT_CSD_PWR_CL_26_195 201 /* RO */
303 #define EXT_CSD_PWR_CL_52_360 202 /* RO */
304 #define EXT_CSD_PWR_CL_26_360 203 /* RO */
305 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
306 #define EXT_CSD_S_A_TIMEOUT 217 /* RO */
307 #define EXT_CSD_REL_WR_SEC_C 222 /* RO */
308 #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
309 #define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
310 #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
311 #define EXT_CSD_BOOT_MULT 226 /* RO */
312 #define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
313 #define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
314 #define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
315 #define EXT_CSD_TRIM_MULT 232 /* RO */
316 #define EXT_CSD_PWR_CL_200_195 236 /* RO */
317 #define EXT_CSD_PWR_CL_200_360 237 /* RO */
318 #define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */
319 #define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */
320 #define EXT_CSD_BKOPS_STATUS 246 /* RO */
321 #define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */
322 #define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
323 #define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
324 #define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */
325 #define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */
326 #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
327 #define EXT_CSD_HPI_FEATURES 503 /* RO */
328 
329 /*
330  * EXT_CSD field definitions
331  */
332 
333 #define EXT_CSD_WR_REL_PARAM_EN (1<<2)
334 
335 #define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40)
336 #define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10)
337 #define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04)
338 #define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01)
339 
340 #define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
341 #define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
342 #define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4)
343 
344 #define EXT_CSD_PART_SUPPORT_PART_EN (0x1)
345 
346 #define EXT_CSD_CMD_SET_NORMAL (1<<0)
347 #define EXT_CSD_CMD_SET_SECURE (1<<1)
348 #define EXT_CSD_CMD_SET_CPSECURE (1<<2)
349 
350 #define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */
351 #define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */
352 #define EXT_CSD_CARD_TYPE_MASK 0x3F /* Mask out reserved bits */
353 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */
354  /* DDR mode @1.8V or 3V I/O */
355 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */
356  /* DDR mode @1.2V I/O */
357 #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
358  | EXT_CSD_CARD_TYPE_DDR_1_2V)
359 #define EXT_CSD_CARD_TYPE_SDR_1_8V (1<<4) /* Card can run at 200MHz */
360 #define EXT_CSD_CARD_TYPE_SDR_1_2V (1<<5) /* Card can run at 200MHz */
361  /* SDR mode @1.2V I/O */
362 
363 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
364 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
365 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
366 #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
367 #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
368 
369 #define EXT_CSD_SEC_ER_EN BIT(0)
370 #define EXT_CSD_SEC_BD_BLK_EN BIT(2)
371 #define EXT_CSD_SEC_GB_CL_EN BIT(4)
372 #define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */
373 
374 #define EXT_CSD_RST_N_EN_MASK 0x3
375 #define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */
376 
377 #define EXT_CSD_NO_POWER_NOTIFICATION 0
378 #define EXT_CSD_POWER_ON 1
379 #define EXT_CSD_POWER_OFF_SHORT 2
380 #define EXT_CSD_POWER_OFF_LONG 3
381 
382 #define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */
383 #define EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */
384 #define EXT_CSD_PWR_CL_8BIT_SHIFT 4
385 #define EXT_CSD_PWR_CL_4BIT_SHIFT 0
386 /*
387  * EXCEPTION_EVENT_STATUS field
388  */
389 #define EXT_CSD_URGENT_BKOPS BIT(0)
390 #define EXT_CSD_DYNCAP_NEEDED BIT(1)
391 #define EXT_CSD_SYSPOOL_EXHAUSTED BIT(2)
392 #define EXT_CSD_PACKED_FAILURE BIT(3)
393 
394 /*
395  * BKOPS status level
396  */
397 #define EXT_CSD_BKOPS_LEVEL_2 0x2
398 
399 /*
400  * MMC_SWITCH access modes
401  */
402 
403 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
404 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */
405 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */
406 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
407 
408 #endif /* LINUX_MMC_MMC_H */
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