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iomux-imx31.c
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1 /*
2  * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3  * Copyright (C) 2008 by Sascha Hauer <[email protected]>
4  * Copyright (C) 2009 by Valentin Longchamp <[email protected]>
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * as published by the Free Software Foundation; either version 2
9  * of the License, or (at your option) any later version.
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18  * MA 02110-1301, USA.
19  */
20 #include <linux/gpio.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/io.h>
24 #include <linux/kernel.h>
25 #include <mach/hardware.h>
26 #include <mach/iomux-mx3.h>
27 
28 /*
29  * IOMUX register (base) addresses
30  */
31 #define IOMUX_BASE MX31_IO_ADDRESS(MX31_IOMUXC_BASE_ADDR)
32 #define IOMUXINT_OBS1 (IOMUX_BASE + 0x000)
33 #define IOMUXINT_OBS2 (IOMUX_BASE + 0x004)
34 #define IOMUXGPR (IOMUX_BASE + 0x008)
35 #define IOMUXSW_MUX_CTL (IOMUX_BASE + 0x00C)
36 #define IOMUXSW_PAD_CTL (IOMUX_BASE + 0x154)
37 
38 static DEFINE_SPINLOCK(gpio_mux_lock);
39 
40 #define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
41 
43 /*
44  * set the mode for a IOMUX pin.
45  */
46 int mxc_iomux_mode(unsigned int pin_mode)
47 {
48  u32 field, l, mode, ret = 0;
49  void __iomem *reg;
50 
51  reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
52  field = pin_mode & 0x3;
53  mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
54 
55  spin_lock(&gpio_mux_lock);
56 
57  l = __raw_readl(reg);
58  l &= ~(0xff << (field * 8));
59  l |= mode << (field * 8);
60  __raw_writel(l, reg);
61 
62  spin_unlock(&gpio_mux_lock);
63 
64  return ret;
65 }
67 
68 /*
69  * This function configures the pad value for a IOMUX pin.
70  */
72 {
73  u32 field, l;
74  void __iomem *reg;
75 
76  pin &= IOMUX_PADNUM_MASK;
77  reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
78  field = (pin + 2) % 3;
79 
80  pr_debug("%s: reg offset = 0x%x, field = %d\n",
81  __func__, (pin + 2) / 3, field);
82 
83  spin_lock(&gpio_mux_lock);
84 
85  l = __raw_readl(reg);
86  l &= ~(0x1ff << (field * 10));
87  l |= config << (field * 10);
88  __raw_writel(l, reg);
89 
90  spin_unlock(&gpio_mux_lock);
91 }
93 
94 /*
95  * allocs a single pin:
96  * - reserves the pin so that it is not claimed by another driver
97  * - setups the iomux according to the configuration
98  */
99 int mxc_iomux_alloc_pin(unsigned int pin, const char *label)
100 {
101  unsigned pad = pin & IOMUX_PADNUM_MASK;
102 
103  if (pad >= (PIN_MAX + 1)) {
104  printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
105  pad, label ? label : "?");
106  return -EINVAL;
107  }
108 
110  printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
111  pad, label ? label : "?");
112  return -EBUSY;
113  }
114  mxc_iomux_mode(pin);
115 
116  return 0;
117 }
119 
120 int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
121  const char *label)
122 {
123  const unsigned int *p = pin_list;
124  int i;
125  int ret = -EINVAL;
126 
127  for (i = 0; i < count; i++) {
128  ret = mxc_iomux_alloc_pin(*p, label);
129  if (ret)
130  goto setup_error;
131  p++;
132  }
133  return 0;
134 
135 setup_error:
136  mxc_iomux_release_multiple_pins(pin_list, i);
137  return ret;
138 }
140 
141 void mxc_iomux_release_pin(unsigned int pin)
142 {
143  unsigned pad = pin & IOMUX_PADNUM_MASK;
144 
145  if (pad < (PIN_MAX + 1))
147 }
149 
150 void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
151 {
152  const unsigned int *p = pin_list;
153  int i;
154 
155  for (i = 0; i < count; i++) {
157  p++;
158  }
159 }
161 
162 /*
163  * This function enables/disables the general purpose function for a particular
164  * signal.
165  */
166 void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
167 {
168  u32 l;
169 
170  spin_lock(&gpio_mux_lock);
171  l = __raw_readl(IOMUXGPR);
172  if (en)
173  l |= gp;
174  else
175  l &= ~gp;
176 
178  spin_unlock(&gpio_mux_lock);
179 }