Go to the documentation of this file. 1 #ifndef __iop_fifo_in_defs_h
2 #define __iop_fifo_in_defs_h
18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
53 #ifndef REG_RD_INT_VECT
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
66 #define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
71 #define reg_page_size 8192
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
89 unsigned int avail_lim : 3;
90 unsigned int byte_order : 2;
91 unsigned int trig : 2;
92 unsigned int last_dis_dif_in : 1;
94 unsigned int dummy1 : 22;
96 #define REG_RD_ADDR_iop_fifo_in_rw_cfg 0
97 #define REG_WR_ADDR_iop_fifo_in_rw_cfg 0
101 unsigned int dif_in_en : 1;
102 unsigned int dif_out_en : 1;
103 unsigned int dummy1 : 30;
105 #define REG_RD_ADDR_iop_fifo_in_rw_ctrl 4
106 #define REG_WR_ADDR_iop_fifo_in_rw_ctrl 4
110 unsigned int avail_bytes : 4;
112 unsigned int dif_in_en : 1;
113 unsigned int dif_out_en : 1;
114 unsigned int dummy1 : 18;
116 #define REG_RD_ADDR_iop_fifo_in_r_stat 8
121 unsigned int dummy1 : 24;
123 #define REG_RD_ADDR_iop_fifo_in_rs_rd1byte 12
128 unsigned int dummy1 : 24;
130 #define REG_RD_ADDR_iop_fifo_in_r_rd1byte 16
135 unsigned int dummy1 : 16;
137 #define REG_RD_ADDR_iop_fifo_in_rs_rd2byte 20
142 unsigned int dummy1 : 16;
144 #define REG_RD_ADDR_iop_fifo_in_r_rd2byte 24
149 unsigned int dummy1 : 8;
151 #define REG_RD_ADDR_iop_fifo_in_rs_rd3byte 28
156 unsigned int dummy1 : 8;
158 #define REG_RD_ADDR_iop_fifo_in_r_rd3byte 32
164 #define REG_RD_ADDR_iop_fifo_in_rs_rd4byte 36
170 #define REG_RD_ADDR_iop_fifo_in_r_rd4byte 40
174 #define REG_RD_ADDR_iop_fifo_in_rw_set_last 44
175 #define REG_WR_ADDR_iop_fifo_in_rw_set_last 44
180 unsigned int dummy1 : 30;
182 #define REG_RD_ADDR_iop_fifo_in_rw_strb_dif_in 48
183 #define REG_WR_ADDR_iop_fifo_in_rw_strb_dif_in 48
187 unsigned int urun : 1;
188 unsigned int last_data : 1;
189 unsigned int dav : 1;
191 unsigned int orun : 1;
192 unsigned int dummy1 : 27;
194 #define REG_RD_ADDR_iop_fifo_in_rw_intr_mask 52
195 #define REG_WR_ADDR_iop_fifo_in_rw_intr_mask 52
199 unsigned int urun : 1;
200 unsigned int last_data : 1;
201 unsigned int dav : 1;
203 unsigned int orun : 1;
204 unsigned int dummy1 : 27;
206 #define REG_RD_ADDR_iop_fifo_in_rw_ack_intr 56
207 #define REG_WR_ADDR_iop_fifo_in_rw_ack_intr 56
211 unsigned int urun : 1;
212 unsigned int last_data : 1;
213 unsigned int dav : 1;
215 unsigned int orun : 1;
216 unsigned int dummy1 : 27;
218 #define REG_RD_ADDR_iop_fifo_in_r_intr 60
222 unsigned int urun : 1;
223 unsigned int last_data : 1;
224 unsigned int dav : 1;
226 unsigned int orun : 1;
227 unsigned int dummy1 : 27;
229 #define REG_RD_ADDR_iop_fifo_in_r_masked_intr 64