Go to the documentation of this file. 1 #ifndef __iop_fifo_in_extra_defs_h
2 #define __iop_fifo_in_extra_defs_h
18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
53 #ifndef REG_RD_INT_VECT
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
66 #define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
71 #define reg_page_size 8192
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
89 #define REG_RD_ADDR_iop_fifo_in_extra_rw_wr_data 0
90 #define REG_WR_ADDR_iop_fifo_in_extra_rw_wr_data 0
94 unsigned int avail_bytes : 4;
96 unsigned int dif_in_en : 1;
97 unsigned int dif_out_en : 1;
98 unsigned int dummy1 : 18;
100 #define REG_RD_ADDR_iop_fifo_in_extra_r_stat 4
105 unsigned int dummy1 : 30;
107 #define REG_RD_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8
108 #define REG_WR_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8
112 unsigned int urun : 1;
113 unsigned int last_data : 1;
114 unsigned int dav : 1;
116 unsigned int orun : 1;
117 unsigned int dummy1 : 27;
119 #define REG_RD_ADDR_iop_fifo_in_extra_rw_intr_mask 12
120 #define REG_WR_ADDR_iop_fifo_in_extra_rw_intr_mask 12
124 unsigned int urun : 1;
125 unsigned int last_data : 1;
126 unsigned int dav : 1;
128 unsigned int orun : 1;
129 unsigned int dummy1 : 27;
131 #define REG_RD_ADDR_iop_fifo_in_extra_rw_ack_intr 16
132 #define REG_WR_ADDR_iop_fifo_in_extra_rw_ack_intr 16
136 unsigned int urun : 1;
137 unsigned int last_data : 1;
138 unsigned int dav : 1;
140 unsigned int orun : 1;
141 unsigned int dummy1 : 27;
143 #define REG_RD_ADDR_iop_fifo_in_extra_r_intr 20
147 unsigned int urun : 1;
148 unsigned int last_data : 1;
149 unsigned int dav : 1;
151 unsigned int orun : 1;
152 unsigned int dummy1 : 27;
154 #define REG_RD_ADDR_iop_fifo_in_extra_r_masked_intr 24