Go to the documentation of this file. 1 #ifndef __iop_fifo_out_extra_defs_h
2 #define __iop_fifo_out_extra_defs_h
18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
53 #ifndef REG_RD_INT_VECT
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
66 #define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
71 #define reg_page_size 8192
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
89 #define REG_RD_ADDR_iop_fifo_out_extra_rs_rd_data 0
93 #define REG_RD_ADDR_iop_fifo_out_extra_r_rd_data 4
97 unsigned int avail_bytes : 4;
99 unsigned int dif_in_en : 1;
100 unsigned int dif_out_en : 1;
101 unsigned int zero_data_last : 1;
102 unsigned int dummy1 : 17;
104 #define REG_RD_ADDR_iop_fifo_out_extra_r_stat 8
108 #define REG_RD_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12
109 #define REG_WR_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12
113 unsigned int urun : 1;
114 unsigned int last_data : 1;
115 unsigned int dav : 1;
117 unsigned int orun : 1;
118 unsigned int dummy1 : 27;
120 #define REG_RD_ADDR_iop_fifo_out_extra_rw_intr_mask 16
121 #define REG_WR_ADDR_iop_fifo_out_extra_rw_intr_mask 16
125 unsigned int urun : 1;
126 unsigned int last_data : 1;
127 unsigned int dav : 1;
129 unsigned int orun : 1;
130 unsigned int dummy1 : 27;
132 #define REG_RD_ADDR_iop_fifo_out_extra_rw_ack_intr 20
133 #define REG_WR_ADDR_iop_fifo_out_extra_rw_ack_intr 20
137 unsigned int urun : 1;
138 unsigned int last_data : 1;
139 unsigned int dav : 1;
141 unsigned int orun : 1;
142 unsigned int dummy1 : 27;
144 #define REG_RD_ADDR_iop_fifo_out_extra_r_intr 24
148 unsigned int urun : 1;
149 unsigned int last_data : 1;
150 unsigned int dav : 1;
152 unsigned int orun : 1;
153 unsigned int dummy1 : 27;
155 #define REG_RD_ADDR_iop_fifo_out_extra_r_masked_intr 28