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iop_trigger_grp_defs.h
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1 #ifndef __iop_trigger_grp_defs_h
2 #define __iop_trigger_grp_defs_h
3 
4 /*
5  * This file is autogenerated from
6  * file: ../../inst/io_proc/rtl/iop_trigger_grp.r
7  * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp
8  * last modfied: Mon Apr 11 16:08:46 2005
9  *
10  * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_trigger_grp_defs.h ../../inst/io_proc/rtl/iop_trigger_grp.r
11  * id: $Id: iop_trigger_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
12  * Any changes here will be lost.
13  *
14  * -*- buffer-read-only: t -*-
15  */
16 /* Main access macros */
17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \
19  REG_READ( reg_##scope##_##reg, \
20  (inst) + REG_RD_ADDR_##scope##_##reg )
21 #endif
22 
23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \
25  REG_WRITE( reg_##scope##_##reg, \
26  (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #endif
28 
29 #ifndef REG_RD_VECT
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31  REG_READ( reg_##scope##_##reg, \
32  (inst) + REG_RD_ADDR_##scope##_##reg + \
33  (index) * STRIDE_##scope##_##reg )
34 #endif
35 
36 #ifndef REG_WR_VECT
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38  REG_WRITE( reg_##scope##_##reg, \
39  (inst) + REG_WR_ADDR_##scope##_##reg + \
40  (index) * STRIDE_##scope##_##reg, (val) )
41 #endif
42 
43 #ifndef REG_RD_INT
44 #define REG_RD_INT( scope, inst, reg ) \
45  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #endif
47 
48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \
50  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #endif
52 
53 #ifndef REG_RD_INT_VECT
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56  (index) * STRIDE_##scope##_##reg )
57 #endif
58 
59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62  (index) * STRIDE_##scope##_##reg, (val) )
63 #endif
64 
65 #ifndef REG_TYPE_CONV
66 #define REG_TYPE_CONV( type, orgtype, val ) \
67  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68 #endif
69 
70 #ifndef reg_page_size
71 #define reg_page_size 8192
72 #endif
73 
74 #ifndef REG_ADDR
75 #define REG_ADDR( scope, inst, reg ) \
76  ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #endif
78 
79 #ifndef REG_ADDR_VECT
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82  (index) * STRIDE_##scope##_##reg )
83 #endif
84 
85 /* C-code for register scope iop_trigger_grp */
86 
87 #define STRIDE_iop_trigger_grp_rw_cfg 4
88 /* Register rw_cfg, scope iop_trigger_grp, type rw */
89 typedef struct {
90  unsigned int action : 2;
91  unsigned int once : 1;
92  unsigned int trig : 3;
93  unsigned int en_only_by_reg : 1;
94  unsigned int dis_only_by_reg : 1;
95  unsigned int dummy1 : 24;
96 } reg_iop_trigger_grp_rw_cfg;
97 #define REG_RD_ADDR_iop_trigger_grp_rw_cfg 0
98 #define REG_WR_ADDR_iop_trigger_grp_rw_cfg 0
99 
100 /* Register rw_cmd, scope iop_trigger_grp, type rw */
101 typedef struct {
102  unsigned int dis : 4;
103  unsigned int en : 4;
104  unsigned int dummy1 : 24;
105 } reg_iop_trigger_grp_rw_cmd;
106 #define REG_RD_ADDR_iop_trigger_grp_rw_cmd 16
107 #define REG_WR_ADDR_iop_trigger_grp_rw_cmd 16
108 
109 /* Register rw_intr_mask, scope iop_trigger_grp, type rw */
110 typedef struct {
111  unsigned int trig0 : 1;
112  unsigned int trig1 : 1;
113  unsigned int trig2 : 1;
114  unsigned int trig3 : 1;
115  unsigned int dummy1 : 28;
116 } reg_iop_trigger_grp_rw_intr_mask;
117 #define REG_RD_ADDR_iop_trigger_grp_rw_intr_mask 20
118 #define REG_WR_ADDR_iop_trigger_grp_rw_intr_mask 20
119 
120 /* Register rw_ack_intr, scope iop_trigger_grp, type rw */
121 typedef struct {
122  unsigned int trig0 : 1;
123  unsigned int trig1 : 1;
124  unsigned int trig2 : 1;
125  unsigned int trig3 : 1;
126  unsigned int dummy1 : 28;
127 } reg_iop_trigger_grp_rw_ack_intr;
128 #define REG_RD_ADDR_iop_trigger_grp_rw_ack_intr 24
129 #define REG_WR_ADDR_iop_trigger_grp_rw_ack_intr 24
130 
131 /* Register r_intr, scope iop_trigger_grp, type r */
132 typedef struct {
133  unsigned int trig0 : 1;
134  unsigned int trig1 : 1;
135  unsigned int trig2 : 1;
136  unsigned int trig3 : 1;
137  unsigned int dummy1 : 28;
138 } reg_iop_trigger_grp_r_intr;
139 #define REG_RD_ADDR_iop_trigger_grp_r_intr 28
140 
141 /* Register r_masked_intr, scope iop_trigger_grp, type r */
142 typedef struct {
143  unsigned int trig0 : 1;
144  unsigned int trig1 : 1;
145  unsigned int trig2 : 1;
146  unsigned int trig3 : 1;
147  unsigned int dummy1 : 28;
148 } reg_iop_trigger_grp_r_masked_intr;
149 #define REG_RD_ADDR_iop_trigger_grp_r_masked_intr 32
150 
151 
152 /* Constants */
153 enum {
154  regk_iop_trigger_grp_fall = 0x00000002,
155  regk_iop_trigger_grp_fall_lo = 0x00000006,
156  regk_iop_trigger_grp_no = 0x00000000,
157  regk_iop_trigger_grp_off = 0x00000000,
158  regk_iop_trigger_grp_pulse = 0x00000000,
159  regk_iop_trigger_grp_rise = 0x00000001,
160  regk_iop_trigger_grp_rise_fall = 0x00000003,
161  regk_iop_trigger_grp_rise_fall_hi = 0x00000007,
162  regk_iop_trigger_grp_rise_fall_lo = 0x00000004,
163  regk_iop_trigger_grp_rise_hi = 0x00000005,
164  regk_iop_trigger_grp_rw_cfg_default = 0x000000c0,
165  regk_iop_trigger_grp_rw_cfg_size = 0x00000004,
166  regk_iop_trigger_grp_rw_intr_mask_default = 0x00000000,
167  regk_iop_trigger_grp_toggle = 0x00000003,
168  regk_iop_trigger_grp_yes = 0x00000001
169 };
170 #endif /* __iop_trigger_grp_defs_h */
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