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31 #define DEFSAMPLERATE 44100
32 #define DEFSAMPLESIZE SNDRV_PCM_FORMAT_S16
35 #define SRAM_BANK_SIZE 0x8000
36 #define SRAM_CNTL_START 0x7F00
37 #define SMA_STRUCT_START 0x7F40
39 #define DSP_BASE_ADDR 0x4000
40 #define DSP_BANK_BASE 0x4000
45 #define EXT_DSP_BIT_DCAL 0x0001
46 #define EXT_DSP_BIT_MIDI_CON 0x0002
48 #define BUFFSIZE 0x8000
49 #define HOSTQ_SIZE 0x40
51 #define DAP_BUFF_SIZE 0x2400
53 #define DAPQ_STRUCT_SIZE 0x10
54 #define DARQ_STRUCT_SIZE 0x10
55 #define DAPQ_BUFF_SIZE (3 * 0x10)
56 #define DARQ_BUFF_SIZE (3 * 0x10)
57 #define MODQ_BUFF_SIZE 0x400
59 #define DAPQ_DATA_BUFF 0x6C00
60 #define DARQ_DATA_BUFF 0x6C30
61 #define MODQ_DATA_BUFF 0x6C60
62 #define MIDQ_DATA_BUFF 0x7060
64 #define DAPQ_OFFSET SRAM_CNTL_START
65 #define DARQ_OFFSET (SRAM_CNTL_START + 0x08)
66 #define MODQ_OFFSET (SRAM_CNTL_START + 0x10)
67 #define MIDQ_OFFSET (SRAM_CNTL_START + 0x18)
68 #define DSPQ_OFFSET (SRAM_CNTL_START + 0x20)
83 #define HP_ICR_DEF 0x00
84 #define HP_CVR_DEF 0x12
85 #define HP_ISR_DEF 0x06
86 #define HP_IVR_DEF 0x0f
87 #define HP_NU_DEF 0x00
100 #define HPICR_INIT 0x80
101 #define HPICR_HM1 0x40
102 #define HPICR_HM0 0x20
103 #define HPICR_HF1 0x10
104 #define HPICR_HF0 0x08
105 #define HPICR_TREQ 0x02
106 #define HPICR_RREQ 0x01
108 #define HPCVR_HC 0x80
110 #define HPISR_HREQ 0x80
111 #define HPISR_DMA 0x40
112 #define HPISR_HF3 0x10
113 #define HPISR_HF2 0x08
114 #define HPISR_TRDY 0x04
115 #define HPISR_TXDE 0x02
116 #define HPISR_RXDF 0x01
145 #define HIMT_PLAY_DONE 0x00
146 #define HIMT_RECORD_DONE 0x01
147 #define HIMT_MIDI_EOS 0x02
148 #define HIMT_MIDI_OUT 0x03
150 #define HIMT_MIDI_IN_UCHAR 0x0E
151 #define HIMT_DSP 0x0F
153 #define HDEX_BASE 0x92
154 #define HDEX_PLAY_START (0 + HDEX_BASE)
155 #define HDEX_PLAY_STOP (1 + HDEX_BASE)
156 #define HDEX_PLAY_PAUSE (2 + HDEX_BASE)
157 #define HDEX_PLAY_RESUME (3 + HDEX_BASE)
158 #define HDEX_RECORD_START (4 + HDEX_BASE)
159 #define HDEX_RECORD_STOP (5 + HDEX_BASE)
160 #define HDEX_MIDI_IN_START (6 + HDEX_BASE)
161 #define HDEX_MIDI_IN_STOP (7 + HDEX_BASE)
162 #define HDEX_MIDI_OUT_START (8 + HDEX_BASE)
163 #define HDEX_MIDI_OUT_STOP (9 + HDEX_BASE)
164 #define HDEX_AUX_REQ (10 + HDEX_BASE)
166 #define HDEXAR_CLEAR_PEAKS 1
167 #define HDEXAR_IN_SET_POTS 2
168 #define HDEXAR_AUX_SET_POTS 3
169 #define HDEXAR_CAL_A_TO_D 4
170 #define HDEXAR_RD_EXT_DSP_BITS 5
173 #define HDEXAR_SET_ANA_IN 0
174 #define HDEXAR_SET_SYNTH_IN 4
175 #define HDEXAR_READ_DAT_IN 5
176 #define HDEXAR_MIC_SET_POTS 6
177 #define HDEXAR_SET_DAT_IN 7
179 #define HDEXAR_SET_SYNTH_48 8
180 #define HDEXAR_SET_SYNTH_44 9
182 #define HIWORD(l) ((u16)((((u32)(l)) >> 16) & 0xFFFF))
183 #define LOWORD(l) ((u16)(u32)(l))
184 #define HIBYTE(w) ((u8)(((u16)(w) >> 8) & 0xFF))
185 #define LOBYTE(w) ((u8)(w))
186 #define MAKELONG(low, hi) ((long)(((u16)(low))|(((u32)((u16)(hi)))<<16)))
187 #define MAKEWORD(low, hi) ((u16)(((u8)(low))|(((u16)((u8)(hi)))<<8)))
189 #define PCTODSP_OFFSET(w) (u16)((w)/2)
190 #define PCTODSP_BASED(w) (u16)(((w)/2) + DSP_BASE_ADDR)
191 #define DSPTOPC_BASED(w) (((w) - DSP_BASE_ADDR) * 2)
201 #define JQS_wStart 0x00
202 #define JQS_wSize 0x02
203 #define JQS_wHead 0x04
204 #define JQS_wTail 0x06
205 #define JQS__size 0x08
208 #define DAQDS_wStart 0x00
209 #define DAQDS_wSize 0x02
210 #define DAQDS_wFormat 0x04
211 #define DAQDS_wSampleSize 0x06
212 #define DAQDS_wChannels 0x08
213 #define DAQDS_wSampleRate 0x0A
214 #define DAQDS_wIntMsg 0x0C
215 #define DAQDS_wFlags 0x0E
216 #define DAQDS__size 0x10
254 #define F_RESETTING 0
255 #define F_HAVEDIGITAL 1
256 #define F_AUDIO_WRITE_INUSE 2
258 #define F_WRITEBLOCK 4
259 #define F_WRITEFLUSH 5
260 #define F_AUDIO_READ_INUSE 6
262 #define F_READBLOCK 8
263 #define F_EXT_MIDI_INUSE 9
264 #define F_HDR_MIDI_INUSE 10
265 #define F_DISABLE_WRITE_NDELAY 11
270 #define LEVEL_ENTRIES 32
294 const u8 *bin,
int len);