Go to the documentation of this file. 1 #ifndef __l2cache_defs_h
2 #define __l2cache_defs_h
15 #define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
50 #ifndef REG_RD_INT_VECT
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
63 #define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68 #define reg_page_size 8192
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
87 unsigned int dummy1 : 31;
89 #define REG_RD_ADDR_l2cache_rw_cfg 0
90 #define REG_WR_ADDR_l2cache_rw_cfg 0
94 unsigned int dummy1 : 7;
95 unsigned int cbase : 9;
96 unsigned int dummy2 : 4;
97 unsigned int csize : 10;
98 unsigned int dummy3 : 2;
100 #define REG_RD_ADDR_l2cache_rw_ctrl 4
101 #define REG_WR_ADDR_l2cache_rw_ctrl 4
106 unsigned int dummy1 : 14;
107 unsigned int way : 3;
108 unsigned int dummy2 : 2;
111 #define REG_RD_ADDR_l2cache_rw_idxop 8
112 #define REG_WR_ADDR_l2cache_rw_idxop 8
118 #define REG_RD_ADDR_l2cache_rw_addrop_addr 12
119 #define REG_WR_ADDR_l2cache_rw_addrop_addr 12
124 unsigned int dummy1 : 13;
127 #define REG_RD_ADDR_l2cache_rw_addrop_ctrl 16
128 #define REG_WR_ADDR_l2cache_rw_addrop_ctrl 16