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lpfc_debugfs.h
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1 /*******************************************************************
2  * This file is part of the Emulex Linux Device Driver for *
3  * Fibre Channel Host Bus Adapters. *
4  * Copyright (C) 2007-2011 Emulex. All rights reserved. *
5  * EMULEX and SLI are trademarks of Emulex. *
6  * www.emulex.com *
7  * *
8  * This program is free software; you can redistribute it and/or *
9  * modify it under the terms of version 2 of the GNU General *
10  * Public License as published by the Free Software Foundation. *
11  * This program is distributed in the hope that it will be useful. *
12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16  * TO BE LEGALLY INVALID. See the GNU General Public License for *
17  * more details, a copy of which can be found in the file COPYING *
18  * included with this package. *
19  *******************************************************************/
20 
21 #ifndef _H_LPFC_DEBUG_FS
22 #define _H_LPFC_DEBUG_FS
23 
24 #ifdef CONFIG_SCSI_LPFC_DEBUG_FS
25 
26 /* size of output line, for discovery_trace and slow_ring_trace */
27 #define LPFC_DEBUG_TRC_ENTRY_SIZE 100
28 
29 /* nodelist output buffer size */
30 #define LPFC_NODELIST_SIZE 8192
31 #define LPFC_NODELIST_ENTRY_SIZE 120
32 
33 /* dumpHBASlim output buffer size */
34 #define LPFC_DUMPHBASLIM_SIZE 4096
35 
36 /* dumpHostSlim output buffer size */
37 #define LPFC_DUMPHOSTSLIM_SIZE 4096
38 
39 /* dumpSLIqinfo output buffer size */
40 #define LPFC_DUMPSLIQINFO_SIZE 4096
41 
42 /* hbqinfo output buffer size */
43 #define LPFC_HBQINFO_SIZE 8192
44 
45 /*
46  * For SLI4 iDiag debugfs diagnostics tool
47  */
48 
49 /* pciConf */
50 #define LPFC_PCI_CFG_BROWSE 0xffff
51 #define LPFC_PCI_CFG_RD_CMD_ARG 2
52 #define LPFC_PCI_CFG_WR_CMD_ARG 3
53 #define LPFC_PCI_CFG_SIZE 4096
54 #define LPFC_PCI_CFG_RD_SIZE (LPFC_PCI_CFG_SIZE/4)
55 
56 #define IDIAG_PCICFG_WHERE_INDX 0
57 #define IDIAG_PCICFG_COUNT_INDX 1
58 #define IDIAG_PCICFG_VALUE_INDX 2
59 
60 /* barAcc */
61 #define LPFC_PCI_BAR_BROWSE 0xffff
62 #define LPFC_PCI_BAR_RD_CMD_ARG 3
63 #define LPFC_PCI_BAR_WR_CMD_ARG 3
64 
65 #define LPFC_PCI_IF0_BAR0_SIZE (1024 * 16)
66 #define LPFC_PCI_IF0_BAR1_SIZE (1024 * 128)
67 #define LPFC_PCI_IF0_BAR2_SIZE (1024 * 128)
68 #define LPFC_PCI_IF2_BAR0_SIZE (1024 * 32)
69 
70 #define LPFC_PCI_BAR_RD_BUF_SIZE 4096
71 #define LPFC_PCI_BAR_RD_SIZE (LPFC_PCI_BAR_RD_BUF_SIZE/4)
72 
73 #define LPFC_PCI_IF0_BAR0_RD_SIZE (LPFC_PCI_IF0_BAR0_SIZE/4)
74 #define LPFC_PCI_IF0_BAR1_RD_SIZE (LPFC_PCI_IF0_BAR1_SIZE/4)
75 #define LPFC_PCI_IF0_BAR2_RD_SIZE (LPFC_PCI_IF0_BAR2_SIZE/4)
76 #define LPFC_PCI_IF2_BAR0_RD_SIZE (LPFC_PCI_IF2_BAR0_SIZE/4)
77 
78 #define IDIAG_BARACC_BAR_NUM_INDX 0
79 #define IDIAG_BARACC_OFF_SET_INDX 1
80 #define IDIAG_BARACC_ACC_MOD_INDX 2
81 #define IDIAG_BARACC_REG_VAL_INDX 2
82 #define IDIAG_BARACC_BAR_SZE_INDX 3
83 
84 #define IDIAG_BARACC_BAR_0 0
85 #define IDIAG_BARACC_BAR_1 1
86 #define IDIAG_BARACC_BAR_2 2
87 
88 #define SINGLE_WORD 1
89 
90 /* queue info */
91 #define LPFC_QUE_INFO_GET_BUF_SIZE 4096
92 
93 /* queue acc */
94 #define LPFC_QUE_ACC_BROWSE 0xffff
95 #define LPFC_QUE_ACC_RD_CMD_ARG 4
96 #define LPFC_QUE_ACC_WR_CMD_ARG 6
97 #define LPFC_QUE_ACC_BUF_SIZE 4096
98 #define LPFC_QUE_ACC_SIZE (LPFC_QUE_ACC_BUF_SIZE/2)
99 
100 #define LPFC_IDIAG_EQ 1
101 #define LPFC_IDIAG_CQ 2
102 #define LPFC_IDIAG_MQ 3
103 #define LPFC_IDIAG_WQ 4
104 #define LPFC_IDIAG_RQ 5
105 
106 #define IDIAG_QUEACC_QUETP_INDX 0
107 #define IDIAG_QUEACC_QUEID_INDX 1
108 #define IDIAG_QUEACC_INDEX_INDX 2
109 #define IDIAG_QUEACC_COUNT_INDX 3
110 #define IDIAG_QUEACC_OFFST_INDX 4
111 #define IDIAG_QUEACC_VALUE_INDX 5
112 
113 /* doorbell register acc */
114 #define LPFC_DRB_ACC_ALL 0xffff
115 #define LPFC_DRB_ACC_RD_CMD_ARG 1
116 #define LPFC_DRB_ACC_WR_CMD_ARG 2
117 #define LPFC_DRB_ACC_BUF_SIZE 256
118 
119 #define LPFC_DRB_EQCQ 1
120 #define LPFC_DRB_MQ 2
121 #define LPFC_DRB_WQ 3
122 #define LPFC_DRB_RQ 4
123 
124 #define LPFC_DRB_MAX 4
125 
126 #define IDIAG_DRBACC_REGID_INDX 0
127 #define IDIAG_DRBACC_VALUE_INDX 1
128 
129 /* control register acc */
130 #define LPFC_CTL_ACC_ALL 0xffff
131 #define LPFC_CTL_ACC_RD_CMD_ARG 1
132 #define LPFC_CTL_ACC_WR_CMD_ARG 2
133 #define LPFC_CTL_ACC_BUF_SIZE 256
134 
135 #define LPFC_CTL_PORT_SEM 1
136 #define LPFC_CTL_PORT_STA 2
137 #define LPFC_CTL_PORT_CTL 3
138 #define LPFC_CTL_PORT_ER1 4
139 #define LPFC_CTL_PORT_ER2 5
140 #define LPFC_CTL_PDEV_CTL 6
141 
142 #define LPFC_CTL_MAX 6
143 
144 #define IDIAG_CTLACC_REGID_INDX 0
145 #define IDIAG_CTLACC_VALUE_INDX 1
146 
147 /* mailbox access */
148 #define LPFC_MBX_DMP_ARG 4
149 
150 #define LPFC_MBX_ACC_BUF_SIZE 512
151 #define LPFC_MBX_ACC_LBUF_SZ 128
152 
153 #define LPFC_MBX_DMP_MBX_WORD 0x00000001
154 #define LPFC_MBX_DMP_MBX_BYTE 0x00000002
155 #define LPFC_MBX_DMP_MBX_ALL (LPFC_MBX_DMP_MBX_WORD | LPFC_MBX_DMP_MBX_BYTE)
156 
157 #define LPFC_BSG_DMP_MBX_RD_MBX 0x00000001
158 #define LPFC_BSG_DMP_MBX_RD_BUF 0x00000002
159 #define LPFC_BSG_DMP_MBX_WR_MBX 0x00000004
160 #define LPFC_BSG_DMP_MBX_WR_BUF 0x00000008
161 #define LPFC_BSG_DMP_MBX_ALL (LPFC_BSG_DMP_MBX_RD_MBX | \
162  LPFC_BSG_DMP_MBX_RD_BUF | \
163  LPFC_BSG_DMP_MBX_WR_MBX | \
164  LPFC_BSG_DMP_MBX_WR_BUF)
165 
166 #define LPFC_MBX_DMP_ALL 0xffff
167 #define LPFC_MBX_ALL_CMD 0xff
168 
169 #define IDIAG_MBXACC_MBCMD_INDX 0
170 #define IDIAG_MBXACC_DPMAP_INDX 1
171 #define IDIAG_MBXACC_DPCNT_INDX 2
172 #define IDIAG_MBXACC_WDCNT_INDX 3
173 
174 /* extents access */
175 #define LPFC_EXT_ACC_CMD_ARG 1
176 #define LPFC_EXT_ACC_BUF_SIZE 4096
177 
178 #define LPFC_EXT_ACC_AVAIL 0x1
179 #define LPFC_EXT_ACC_ALLOC 0x2
180 #define LPFC_EXT_ACC_DRIVR 0x4
181 #define LPFC_EXT_ACC_ALL (LPFC_EXT_ACC_DRIVR | \
182  LPFC_EXT_ACC_AVAIL | \
183  LPFC_EXT_ACC_ALLOC)
184 
185 #define IDIAG_EXTACC_EXMAP_INDX 0
186 
187 #define SIZE_U8 sizeof(uint8_t)
188 #define SIZE_U16 sizeof(uint16_t)
189 #define SIZE_U32 sizeof(uint32_t)
190 
191 struct lpfc_debug {
192  char *i_private;
193  char op;
194 #define LPFC_IDIAG_OP_RD 1
195 #define LPFC_IDIAG_OP_WR 2
196  char *buffer;
197  int len;
198 };
199 
200 struct lpfc_debugfs_trc {
201  char *fmt;
202  uint32_t data1;
203  uint32_t data2;
204  uint32_t data3;
205  uint32_t seq_cnt;
206  unsigned long jif;
207 };
208 
209 struct lpfc_idiag_offset {
210  uint32_t last_rd;
211 };
212 
213 #define LPFC_IDIAG_CMD_DATA_SIZE 8
214 struct lpfc_idiag_cmd {
215  uint32_t opcode;
216 #define LPFC_IDIAG_CMD_PCICFG_RD 0x00000001
217 #define LPFC_IDIAG_CMD_PCICFG_WR 0x00000002
218 #define LPFC_IDIAG_CMD_PCICFG_ST 0x00000003
219 #define LPFC_IDIAG_CMD_PCICFG_CL 0x00000004
220 
221 #define LPFC_IDIAG_CMD_BARACC_RD 0x00000008
222 #define LPFC_IDIAG_CMD_BARACC_WR 0x00000009
223 #define LPFC_IDIAG_CMD_BARACC_ST 0x0000000a
224 #define LPFC_IDIAG_CMD_BARACC_CL 0x0000000b
225 
226 #define LPFC_IDIAG_CMD_QUEACC_RD 0x00000011
227 #define LPFC_IDIAG_CMD_QUEACC_WR 0x00000012
228 #define LPFC_IDIAG_CMD_QUEACC_ST 0x00000013
229 #define LPFC_IDIAG_CMD_QUEACC_CL 0x00000014
230 
231 #define LPFC_IDIAG_CMD_DRBACC_RD 0x00000021
232 #define LPFC_IDIAG_CMD_DRBACC_WR 0x00000022
233 #define LPFC_IDIAG_CMD_DRBACC_ST 0x00000023
234 #define LPFC_IDIAG_CMD_DRBACC_CL 0x00000024
235 
236 #define LPFC_IDIAG_CMD_CTLACC_RD 0x00000031
237 #define LPFC_IDIAG_CMD_CTLACC_WR 0x00000032
238 #define LPFC_IDIAG_CMD_CTLACC_ST 0x00000033
239 #define LPFC_IDIAG_CMD_CTLACC_CL 0x00000034
240 
241 #define LPFC_IDIAG_CMD_MBXACC_DP 0x00000041
242 #define LPFC_IDIAG_BSG_MBXACC_DP 0x00000042
243 
244 #define LPFC_IDIAG_CMD_EXTACC_RD 0x00000051
245 
246  uint32_t data[LPFC_IDIAG_CMD_DATA_SIZE];
247 };
248 
249 struct lpfc_idiag {
250  uint32_t active;
251  struct lpfc_idiag_cmd cmd;
252  struct lpfc_idiag_offset offset;
253  void *ptr_private;
254 };
255 #endif
256 
257 /* Mask for discovery_trace */
258 #define LPFC_DISC_TRC_ELS_CMD 0x1 /* Trace ELS commands */
259 #define LPFC_DISC_TRC_ELS_RSP 0x2 /* Trace ELS response */
260 #define LPFC_DISC_TRC_ELS_UNSOL 0x4 /* Trace ELS rcv'ed */
261 #define LPFC_DISC_TRC_ELS_ALL 0x7 /* Trace ELS */
262 #define LPFC_DISC_TRC_MBOX_VPORT 0x8 /* Trace vport MBOXs */
263 #define LPFC_DISC_TRC_MBOX 0x10 /* Trace other MBOXs */
264 #define LPFC_DISC_TRC_MBOX_ALL 0x18 /* Trace all MBOXs */
265 #define LPFC_DISC_TRC_CT 0x20 /* Trace disc CT requests */
266 #define LPFC_DISC_TRC_DSM 0x40 /* Trace DSM events */
267 #define LPFC_DISC_TRC_RPORT 0x80 /* Trace rport events */
268 #define LPFC_DISC_TRC_NODE 0x100 /* Trace ndlp state changes */
269 
270 #define LPFC_DISC_TRC_DISCOVERY 0xef /* common mask for general
271  * discovery */
272 #endif /* H_LPFC_DEBUG_FS */
273 
274 
275 /*
276  * Driver debug utility routines outside of debugfs. The debug utility
277  * routines implemented here is intended to be used in the instrumented
278  * debug driver for debugging host or port issues.
279  */
280 
289 static inline void
290 lpfc_debug_dump_qe(struct lpfc_queue *q, uint32_t idx)
291 {
292  char line_buf[LPFC_LBUF_SZ];
293  int i, esize, qe_word_cnt, len;
294  uint32_t *pword;
295 
296  /* sanity checks */
297  if (!q)
298  return;
299  if (idx >= q->entry_count)
300  return;
301 
302  esize = q->entry_size;
303  qe_word_cnt = esize / sizeof(uint32_t);
304  pword = q->qe[idx].address;
305 
306  len = 0;
307  len += snprintf(line_buf+len, LPFC_LBUF_SZ-len, "QE[%04d]: ", idx);
308  if (qe_word_cnt > 8)
309  printk(KERN_ERR "%s\n", line_buf);
310 
311  for (i = 0; i < qe_word_cnt; i++) {
312  if (!(i % 8)) {
313  if (i != 0)
314  printk(KERN_ERR "%s\n", line_buf);
315  if (qe_word_cnt > 8) {
316  len = 0;
317  memset(line_buf, 0, LPFC_LBUF_SZ);
318  len += snprintf(line_buf+len, LPFC_LBUF_SZ-len,
319  "%03d: ", i);
320  }
321  }
322  len += snprintf(line_buf+len, LPFC_LBUF_SZ-len, "%08x ",
323  ((uint32_t)*pword) & 0xffffffff);
324  pword++;
325  }
326  if (qe_word_cnt <= 8 || (i - 1) % 8)
327  printk(KERN_ERR "%s\n", line_buf);
328 }
329 
337 static inline void
338 lpfc_debug_dump_q(struct lpfc_queue *q)
339 {
340  int idx, entry_count;
341 
342  /* sanity check */
343  if (!q)
344  return;
345 
346  dev_printk(KERN_ERR, &(((q->phba))->pcidev)->dev,
347  "%d: [qid:%d, type:%d, subtype:%d, "
348  "qe_size:%d, qe_count:%d, "
349  "host_index:%d, port_index:%d]\n",
350  (q->phba)->brd_no,
351  q->queue_id, q->type, q->subtype,
352  q->entry_size, q->entry_count,
353  q->host_index, q->hba_index);
354  entry_count = q->entry_count;
355  for (idx = 0; idx < entry_count; idx++)
356  lpfc_debug_dump_qe(q, idx);
357  printk(KERN_ERR "\n");
358 }
359 
368 static inline void
369 lpfc_debug_dump_fcp_wq(struct lpfc_hba *phba, int fcp_wqidx)
370 {
371  /* sanity check */
372  if (fcp_wqidx >= phba->cfg_fcp_io_channel)
373  return;
374 
375  printk(KERN_ERR "FCP WQ: WQ[Idx:%d|Qid:%d]\n",
376  fcp_wqidx, phba->sli4_hba.fcp_wq[fcp_wqidx]->queue_id);
377  lpfc_debug_dump_q(phba->sli4_hba.fcp_wq[fcp_wqidx]);
378 }
379 
388 static inline void
389 lpfc_debug_dump_fcp_cq(struct lpfc_hba *phba, int fcp_wqidx)
390 {
391  int fcp_cqidx, fcp_cqid;
392 
393  /* sanity check */
394  if (fcp_wqidx >= phba->cfg_fcp_io_channel)
395  return;
396 
397  fcp_cqid = phba->sli4_hba.fcp_wq[fcp_wqidx]->assoc_qid;
398  for (fcp_cqidx = 0; fcp_cqidx < phba->cfg_fcp_io_channel; fcp_cqidx++)
399  if (phba->sli4_hba.fcp_cq[fcp_cqidx]->queue_id == fcp_cqid)
400  break;
401  if (phba->intr_type == MSIX) {
402  if (fcp_cqidx >= phba->cfg_fcp_io_channel)
403  return;
404  } else {
405  if (fcp_cqidx > 0)
406  return;
407  }
408 
409  printk(KERN_ERR "FCP CQ: WQ[Idx:%d|Qid%d]->CQ[Idx%d|Qid%d]:\n",
410  fcp_wqidx, phba->sli4_hba.fcp_wq[fcp_wqidx]->queue_id,
411  fcp_cqidx, fcp_cqid);
412  lpfc_debug_dump_q(phba->sli4_hba.fcp_cq[fcp_cqidx]);
413 }
414 
423 static inline void
424 lpfc_debug_dump_hba_eq(struct lpfc_hba *phba, int fcp_wqidx)
425 {
426  struct lpfc_queue *qdesc;
427  int fcp_eqidx, fcp_eqid;
428  int fcp_cqidx, fcp_cqid;
429 
430  /* sanity check */
431  if (fcp_wqidx >= phba->cfg_fcp_io_channel)
432  return;
433  fcp_cqid = phba->sli4_hba.fcp_wq[fcp_wqidx]->assoc_qid;
434  for (fcp_cqidx = 0; fcp_cqidx < phba->cfg_fcp_io_channel; fcp_cqidx++)
435  if (phba->sli4_hba.fcp_cq[fcp_cqidx]->queue_id == fcp_cqid)
436  break;
437  if (phba->intr_type == MSIX) {
438  if (fcp_cqidx >= phba->cfg_fcp_io_channel)
439  return;
440  } else {
441  if (fcp_cqidx > 0)
442  return;
443  }
444 
445  fcp_eqidx = fcp_cqidx;
446  fcp_eqid = phba->sli4_hba.hba_eq[fcp_eqidx]->queue_id;
447  qdesc = phba->sli4_hba.hba_eq[fcp_eqidx];
448 
449  printk(KERN_ERR "FCP EQ: WQ[Idx:%d|Qid:%d]->CQ[Idx:%d|Qid:%d]->"
450  "EQ[Idx:%d|Qid:%d]\n",
451  fcp_wqidx, phba->sli4_hba.fcp_wq[fcp_wqidx]->queue_id,
452  fcp_cqidx, fcp_cqid, fcp_eqidx, fcp_eqid);
453  lpfc_debug_dump_q(qdesc);
454 }
455 
462 static inline void
463 lpfc_debug_dump_els_wq(struct lpfc_hba *phba)
464 {
465  printk(KERN_ERR "ELS WQ: WQ[Qid:%d]:\n",
466  phba->sli4_hba.els_wq->queue_id);
467  lpfc_debug_dump_q(phba->sli4_hba.els_wq);
468 }
469 
476 static inline void
477 lpfc_debug_dump_mbx_wq(struct lpfc_hba *phba)
478 {
479  printk(KERN_ERR "MBX WQ: WQ[Qid:%d]\n",
480  phba->sli4_hba.mbx_wq->queue_id);
481  lpfc_debug_dump_q(phba->sli4_hba.mbx_wq);
482 }
483 
490 static inline void
491 lpfc_debug_dump_dat_rq(struct lpfc_hba *phba)
492 {
493  printk(KERN_ERR "DAT RQ: RQ[Qid:%d]\n",
494  phba->sli4_hba.dat_rq->queue_id);
495  lpfc_debug_dump_q(phba->sli4_hba.dat_rq);
496 }
497 
504 static inline void
505 lpfc_debug_dump_hdr_rq(struct lpfc_hba *phba)
506 {
507  printk(KERN_ERR "HDR RQ: RQ[Qid:%d]\n",
508  phba->sli4_hba.hdr_rq->queue_id);
509  lpfc_debug_dump_q(phba->sli4_hba.hdr_rq);
510 }
511 
518 static inline void
519 lpfc_debug_dump_els_cq(struct lpfc_hba *phba)
520 {
521  printk(KERN_ERR "ELS CQ: WQ[Qid:%d]->CQ[Qid:%d]\n",
522  phba->sli4_hba.els_wq->queue_id,
523  phba->sli4_hba.els_cq->queue_id);
524  lpfc_debug_dump_q(phba->sli4_hba.els_cq);
525 }
526 
533 static inline void
534 lpfc_debug_dump_mbx_cq(struct lpfc_hba *phba)
535 {
536  printk(KERN_ERR "MBX CQ: WQ[Qid:%d]->CQ[Qid:%d]\n",
537  phba->sli4_hba.mbx_wq->queue_id,
538  phba->sli4_hba.mbx_cq->queue_id);
539  lpfc_debug_dump_q(phba->sli4_hba.mbx_cq);
540 }
541 
550 static inline void
551 lpfc_debug_dump_wq_by_id(struct lpfc_hba *phba, int qid)
552 {
553  int wq_idx;
554 
555  for (wq_idx = 0; wq_idx < phba->cfg_fcp_io_channel; wq_idx++)
556  if (phba->sli4_hba.fcp_wq[wq_idx]->queue_id == qid)
557  break;
558  if (wq_idx < phba->cfg_fcp_io_channel) {
559  printk(KERN_ERR "FCP WQ[Idx:%d|Qid:%d]\n", wq_idx, qid);
560  lpfc_debug_dump_q(phba->sli4_hba.fcp_wq[wq_idx]);
561  return;
562  }
563 
564  if (phba->sli4_hba.els_wq->queue_id == qid) {
565  printk(KERN_ERR "ELS WQ[Qid:%d]\n", qid);
566  lpfc_debug_dump_q(phba->sli4_hba.els_wq);
567  }
568 }
569 
578 static inline void
579 lpfc_debug_dump_mq_by_id(struct lpfc_hba *phba, int qid)
580 {
581  if (phba->sli4_hba.mbx_wq->queue_id == qid) {
582  printk(KERN_ERR "MBX WQ[Qid:%d]\n", qid);
583  lpfc_debug_dump_q(phba->sli4_hba.mbx_wq);
584  }
585 }
586 
595 static inline void
596 lpfc_debug_dump_rq_by_id(struct lpfc_hba *phba, int qid)
597 {
598  if (phba->sli4_hba.hdr_rq->queue_id == qid) {
599  printk(KERN_ERR "HDR RQ[Qid:%d]\n", qid);
600  lpfc_debug_dump_q(phba->sli4_hba.hdr_rq);
601  return;
602  }
603  if (phba->sli4_hba.dat_rq->queue_id == qid) {
604  printk(KERN_ERR "DAT RQ[Qid:%d]\n", qid);
605  lpfc_debug_dump_q(phba->sli4_hba.dat_rq);
606  }
607 }
608 
617 static inline void
618 lpfc_debug_dump_cq_by_id(struct lpfc_hba *phba, int qid)
619 {
620  int cq_idx = 0;
621 
622  do {
623  if (phba->sli4_hba.fcp_cq[cq_idx]->queue_id == qid)
624  break;
625  } while (++cq_idx < phba->cfg_fcp_io_channel);
626 
627  if (cq_idx < phba->cfg_fcp_io_channel) {
628  printk(KERN_ERR "FCP CQ[Idx:%d|Qid:%d]\n", cq_idx, qid);
629  lpfc_debug_dump_q(phba->sli4_hba.fcp_cq[cq_idx]);
630  return;
631  }
632 
633  if (phba->sli4_hba.els_cq->queue_id == qid) {
634  printk(KERN_ERR "ELS CQ[Qid:%d]\n", qid);
635  lpfc_debug_dump_q(phba->sli4_hba.els_cq);
636  return;
637  }
638 
639  if (phba->sli4_hba.mbx_cq->queue_id == qid) {
640  printk(KERN_ERR "MBX CQ[Qid:%d]\n", qid);
641  lpfc_debug_dump_q(phba->sli4_hba.mbx_cq);
642  }
643 }
644 
653 static inline void
654 lpfc_debug_dump_eq_by_id(struct lpfc_hba *phba, int qid)
655 {
656  int eq_idx;
657 
658  for (eq_idx = 0; eq_idx < phba->cfg_fcp_io_channel; eq_idx++) {
659  if (phba->sli4_hba.hba_eq[eq_idx]->queue_id == qid)
660  break;
661  }
662 
663  if (eq_idx < phba->cfg_fcp_io_channel) {
664  printk(KERN_ERR "FCP EQ[Idx:%d|Qid:%d]\n", eq_idx, qid);
665  lpfc_debug_dump_q(phba->sli4_hba.hba_eq[eq_idx]);
666  return;
667  }
668 
669 }
670 
671 void lpfc_debug_dump_all_queues(struct lpfc_hba *);
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