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31 #define DEBUG_HW 0x00000001
32 #define DEBUG_HW_OPEN 0x00000002
33 #define DEBUG_HW_DCHANNEL 0x00000100
34 #define DEBUG_HW_DFIFO 0x00000200
35 #define DEBUG_HW_BCHANNEL 0x00001000
36 #define DEBUG_HW_BFIFO 0x00002000
38 #define MAX_DFRAME_LEN_L1 300
39 #define MAX_MON_FRAME 32
40 #define MAX_LOG_SPACE 2048
41 #define MISDN_COPY_SIZE 32
47 #define FLG_L2_ACTIVATED 3
50 #define FLG_BUSY_TIMER 7
52 #define FLG_DCHANNEL 8
53 #define FLG_BCHANNEL 9
54 #define FLG_ECHANNEL 10
55 #define FLG_TRANSPARENT 12
60 #define FLG_FILLEMPTY 16
62 #define FLG_ARCOFI_TIMER 17
63 #define FLG_ARCOFI_ERROR 18
65 #define FLG_INITIALIZED 17
67 #define FLG_LASTDLE 19
69 #define FLG_LASTDATA 21
70 #define FLG_NMD_DATA 22
71 #define FLG_FTI_RUN 23
73 #define FLG_LL_CONN 25
74 #define FLG_DTMFSEND 26
75 #define FLG_TX_EMPTY 27
79 #define FLG_RECVQUEUE 30
80 #define FLG_PHCHANGE 31
82 #define schedule_event(s, ev) do { \
83 test_and_set_bit(ev, &((s)->Flags)); \
84 schedule_work(&((s)->workq)); \
88 struct mISDNdevice
dev;
119 #define INFO3_P8 0x8302
120 #define INFO3_P10 0x8402
121 #define INFO4_P8 0x8502
122 #define INFO4_P10 0x8602
123 #define LOSTFRAMING 0x8702
124 #define ANYSIGNAL 0x8802
125 #define HW_POWERDOWN 0x8902
126 #define HW_RESET_REQ 0x8a02
127 #define HW_POWERUP_REQ 0x8b02
128 #define HW_DEACT_REQ 0x8c02
129 #define HW_ACTIVATE_REQ 0x8e02
130 #define HW_D_NOBLOCKED 0x8f02
131 #define HW_RESET_IND 0x9002
132 #define HW_POWERUP_IND 0x9102
133 #define HW_DEACT_IND 0x9202
134 #define HW_ACTIVATE_IND 0x9302
135 #define HW_DEACT_CNF 0x9402
136 #define HW_TESTLOOP 0x9502
137 #define HW_TESTRX_RAW 0x9602
138 #define HW_TESTRX_HDLC 0x9702
139 #define HW_TESTRX_OFF 0x9802
140 #define HW_TIMER3_IND 0x9902
141 #define HW_TIMER3_VALUE 0x9a00
142 #define HW_TIMER3_VMASK 0x00FF
147 #define MISDN_BCH_FILL_SIZE 4
150 struct mISDNchannel
ch;