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gio_defs_asm.h
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1 #ifndef __gio_defs_asm_h
2 #define __gio_defs_asm_h
3 
4 /*
5  * This file is autogenerated from
6  * file: ../../inst/gio/rtl/gio_regs.r
7  * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
8  * last modfied: Mon Apr 11 16:07:47 2005
9  *
10  * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r
11  * id: $Id: gio_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
12  * Any changes here will be lost.
13  *
14  * -*- buffer-read-only: t -*-
15  */
16 
17 #ifndef REG_FIELD
18 #define REG_FIELD( scope, reg, field, value ) \
19  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20 #define REG_FIELD_X_( value, shift ) ((value) << shift)
21 #endif
22 
23 #ifndef REG_STATE
24 #define REG_STATE( scope, reg, field, symbolic_value ) \
25  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26 #define REG_STATE_X_( k, shift ) (k << shift)
27 #endif
28 
29 #ifndef REG_MASK
30 #define REG_MASK( scope, reg, field ) \
31  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33 #endif
34 
35 #ifndef REG_LSB
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37 #endif
38 
39 #ifndef REG_BIT
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41 #endif
42 
43 #ifndef REG_ADDR
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46 #endif
47 
48 #ifndef REG_ADDR_VECT
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50  REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51  STRIDE_##scope##_##reg )
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53  ((inst) + offs + (index) * stride)
54 #endif
55 
56 /* Register rw_pa_dout, scope gio, type rw */
57 #define reg_gio_rw_pa_dout___data___lsb 0
58 #define reg_gio_rw_pa_dout___data___width 8
59 #define reg_gio_rw_pa_dout_offset 0
60 
61 /* Register r_pa_din, scope gio, type r */
62 #define reg_gio_r_pa_din___data___lsb 0
63 #define reg_gio_r_pa_din___data___width 8
64 #define reg_gio_r_pa_din_offset 4
65 
66 /* Register rw_pa_oe, scope gio, type rw */
67 #define reg_gio_rw_pa_oe___oe___lsb 0
68 #define reg_gio_rw_pa_oe___oe___width 8
69 #define reg_gio_rw_pa_oe_offset 8
70 
71 /* Register rw_intr_cfg, scope gio, type rw */
72 #define reg_gio_rw_intr_cfg___pa0___lsb 0
73 #define reg_gio_rw_intr_cfg___pa0___width 3
74 #define reg_gio_rw_intr_cfg___pa1___lsb 3
75 #define reg_gio_rw_intr_cfg___pa1___width 3
76 #define reg_gio_rw_intr_cfg___pa2___lsb 6
77 #define reg_gio_rw_intr_cfg___pa2___width 3
78 #define reg_gio_rw_intr_cfg___pa3___lsb 9
79 #define reg_gio_rw_intr_cfg___pa3___width 3
80 #define reg_gio_rw_intr_cfg___pa4___lsb 12
81 #define reg_gio_rw_intr_cfg___pa4___width 3
82 #define reg_gio_rw_intr_cfg___pa5___lsb 15
83 #define reg_gio_rw_intr_cfg___pa5___width 3
84 #define reg_gio_rw_intr_cfg___pa6___lsb 18
85 #define reg_gio_rw_intr_cfg___pa6___width 3
86 #define reg_gio_rw_intr_cfg___pa7___lsb 21
87 #define reg_gio_rw_intr_cfg___pa7___width 3
88 #define reg_gio_rw_intr_cfg_offset 12
89 
90 /* Register rw_intr_mask, scope gio, type rw */
91 #define reg_gio_rw_intr_mask___pa0___lsb 0
92 #define reg_gio_rw_intr_mask___pa0___width 1
93 #define reg_gio_rw_intr_mask___pa0___bit 0
94 #define reg_gio_rw_intr_mask___pa1___lsb 1
95 #define reg_gio_rw_intr_mask___pa1___width 1
96 #define reg_gio_rw_intr_mask___pa1___bit 1
97 #define reg_gio_rw_intr_mask___pa2___lsb 2
98 #define reg_gio_rw_intr_mask___pa2___width 1
99 #define reg_gio_rw_intr_mask___pa2___bit 2
100 #define reg_gio_rw_intr_mask___pa3___lsb 3
101 #define reg_gio_rw_intr_mask___pa3___width 1
102 #define reg_gio_rw_intr_mask___pa3___bit 3
103 #define reg_gio_rw_intr_mask___pa4___lsb 4
104 #define reg_gio_rw_intr_mask___pa4___width 1
105 #define reg_gio_rw_intr_mask___pa4___bit 4
106 #define reg_gio_rw_intr_mask___pa5___lsb 5
107 #define reg_gio_rw_intr_mask___pa5___width 1
108 #define reg_gio_rw_intr_mask___pa5___bit 5
109 #define reg_gio_rw_intr_mask___pa6___lsb 6
110 #define reg_gio_rw_intr_mask___pa6___width 1
111 #define reg_gio_rw_intr_mask___pa6___bit 6
112 #define reg_gio_rw_intr_mask___pa7___lsb 7
113 #define reg_gio_rw_intr_mask___pa7___width 1
114 #define reg_gio_rw_intr_mask___pa7___bit 7
115 #define reg_gio_rw_intr_mask_offset 16
116 
117 /* Register rw_ack_intr, scope gio, type rw */
118 #define reg_gio_rw_ack_intr___pa0___lsb 0
119 #define reg_gio_rw_ack_intr___pa0___width 1
120 #define reg_gio_rw_ack_intr___pa0___bit 0
121 #define reg_gio_rw_ack_intr___pa1___lsb 1
122 #define reg_gio_rw_ack_intr___pa1___width 1
123 #define reg_gio_rw_ack_intr___pa1___bit 1
124 #define reg_gio_rw_ack_intr___pa2___lsb 2
125 #define reg_gio_rw_ack_intr___pa2___width 1
126 #define reg_gio_rw_ack_intr___pa2___bit 2
127 #define reg_gio_rw_ack_intr___pa3___lsb 3
128 #define reg_gio_rw_ack_intr___pa3___width 1
129 #define reg_gio_rw_ack_intr___pa3___bit 3
130 #define reg_gio_rw_ack_intr___pa4___lsb 4
131 #define reg_gio_rw_ack_intr___pa4___width 1
132 #define reg_gio_rw_ack_intr___pa4___bit 4
133 #define reg_gio_rw_ack_intr___pa5___lsb 5
134 #define reg_gio_rw_ack_intr___pa5___width 1
135 #define reg_gio_rw_ack_intr___pa5___bit 5
136 #define reg_gio_rw_ack_intr___pa6___lsb 6
137 #define reg_gio_rw_ack_intr___pa6___width 1
138 #define reg_gio_rw_ack_intr___pa6___bit 6
139 #define reg_gio_rw_ack_intr___pa7___lsb 7
140 #define reg_gio_rw_ack_intr___pa7___width 1
141 #define reg_gio_rw_ack_intr___pa7___bit 7
142 #define reg_gio_rw_ack_intr_offset 20
143 
144 /* Register r_intr, scope gio, type r */
145 #define reg_gio_r_intr___pa0___lsb 0
146 #define reg_gio_r_intr___pa0___width 1
147 #define reg_gio_r_intr___pa0___bit 0
148 #define reg_gio_r_intr___pa1___lsb 1
149 #define reg_gio_r_intr___pa1___width 1
150 #define reg_gio_r_intr___pa1___bit 1
151 #define reg_gio_r_intr___pa2___lsb 2
152 #define reg_gio_r_intr___pa2___width 1
153 #define reg_gio_r_intr___pa2___bit 2
154 #define reg_gio_r_intr___pa3___lsb 3
155 #define reg_gio_r_intr___pa3___width 1
156 #define reg_gio_r_intr___pa3___bit 3
157 #define reg_gio_r_intr___pa4___lsb 4
158 #define reg_gio_r_intr___pa4___width 1
159 #define reg_gio_r_intr___pa4___bit 4
160 #define reg_gio_r_intr___pa5___lsb 5
161 #define reg_gio_r_intr___pa5___width 1
162 #define reg_gio_r_intr___pa5___bit 5
163 #define reg_gio_r_intr___pa6___lsb 6
164 #define reg_gio_r_intr___pa6___width 1
165 #define reg_gio_r_intr___pa6___bit 6
166 #define reg_gio_r_intr___pa7___lsb 7
167 #define reg_gio_r_intr___pa7___width 1
168 #define reg_gio_r_intr___pa7___bit 7
169 #define reg_gio_r_intr_offset 24
170 
171 /* Register r_masked_intr, scope gio, type r */
172 #define reg_gio_r_masked_intr___pa0___lsb 0
173 #define reg_gio_r_masked_intr___pa0___width 1
174 #define reg_gio_r_masked_intr___pa0___bit 0
175 #define reg_gio_r_masked_intr___pa1___lsb 1
176 #define reg_gio_r_masked_intr___pa1___width 1
177 #define reg_gio_r_masked_intr___pa1___bit 1
178 #define reg_gio_r_masked_intr___pa2___lsb 2
179 #define reg_gio_r_masked_intr___pa2___width 1
180 #define reg_gio_r_masked_intr___pa2___bit 2
181 #define reg_gio_r_masked_intr___pa3___lsb 3
182 #define reg_gio_r_masked_intr___pa3___width 1
183 #define reg_gio_r_masked_intr___pa3___bit 3
184 #define reg_gio_r_masked_intr___pa4___lsb 4
185 #define reg_gio_r_masked_intr___pa4___width 1
186 #define reg_gio_r_masked_intr___pa4___bit 4
187 #define reg_gio_r_masked_intr___pa5___lsb 5
188 #define reg_gio_r_masked_intr___pa5___width 1
189 #define reg_gio_r_masked_intr___pa5___bit 5
190 #define reg_gio_r_masked_intr___pa6___lsb 6
191 #define reg_gio_r_masked_intr___pa6___width 1
192 #define reg_gio_r_masked_intr___pa6___bit 6
193 #define reg_gio_r_masked_intr___pa7___lsb 7
194 #define reg_gio_r_masked_intr___pa7___width 1
195 #define reg_gio_r_masked_intr___pa7___bit 7
196 #define reg_gio_r_masked_intr_offset 28
197 
198 /* Register rw_pb_dout, scope gio, type rw */
199 #define reg_gio_rw_pb_dout___data___lsb 0
200 #define reg_gio_rw_pb_dout___data___width 18
201 #define reg_gio_rw_pb_dout_offset 32
202 
203 /* Register r_pb_din, scope gio, type r */
204 #define reg_gio_r_pb_din___data___lsb 0
205 #define reg_gio_r_pb_din___data___width 18
206 #define reg_gio_r_pb_din_offset 36
207 
208 /* Register rw_pb_oe, scope gio, type rw */
209 #define reg_gio_rw_pb_oe___oe___lsb 0
210 #define reg_gio_rw_pb_oe___oe___width 18
211 #define reg_gio_rw_pb_oe_offset 40
212 
213 /* Register rw_pc_dout, scope gio, type rw */
214 #define reg_gio_rw_pc_dout___data___lsb 0
215 #define reg_gio_rw_pc_dout___data___width 18
216 #define reg_gio_rw_pc_dout_offset 48
217 
218 /* Register r_pc_din, scope gio, type r */
219 #define reg_gio_r_pc_din___data___lsb 0
220 #define reg_gio_r_pc_din___data___width 18
221 #define reg_gio_r_pc_din_offset 52
222 
223 /* Register rw_pc_oe, scope gio, type rw */
224 #define reg_gio_rw_pc_oe___oe___lsb 0
225 #define reg_gio_rw_pc_oe___oe___width 18
226 #define reg_gio_rw_pc_oe_offset 56
227 
228 /* Register rw_pd_dout, scope gio, type rw */
229 #define reg_gio_rw_pd_dout___data___lsb 0
230 #define reg_gio_rw_pd_dout___data___width 18
231 #define reg_gio_rw_pd_dout_offset 64
232 
233 /* Register r_pd_din, scope gio, type r */
234 #define reg_gio_r_pd_din___data___lsb 0
235 #define reg_gio_r_pd_din___data___width 18
236 #define reg_gio_r_pd_din_offset 68
237 
238 /* Register rw_pd_oe, scope gio, type rw */
239 #define reg_gio_rw_pd_oe___oe___lsb 0
240 #define reg_gio_rw_pd_oe___oe___width 18
241 #define reg_gio_rw_pd_oe_offset 72
242 
243 /* Register rw_pe_dout, scope gio, type rw */
244 #define reg_gio_rw_pe_dout___data___lsb 0
245 #define reg_gio_rw_pe_dout___data___width 18
246 #define reg_gio_rw_pe_dout_offset 80
247 
248 /* Register r_pe_din, scope gio, type r */
249 #define reg_gio_r_pe_din___data___lsb 0
250 #define reg_gio_r_pe_din___data___width 18
251 #define reg_gio_r_pe_din_offset 84
252 
253 /* Register rw_pe_oe, scope gio, type rw */
254 #define reg_gio_rw_pe_oe___oe___lsb 0
255 #define reg_gio_rw_pe_oe___oe___width 18
256 #define reg_gio_rw_pe_oe_offset 88
257 
258 
259 /* Constants */
260 #define regk_gio_anyedge 0x00000007
261 #define regk_gio_hi 0x00000001
262 #define regk_gio_lo 0x00000002
263 #define regk_gio_negedge 0x00000006
264 #define regk_gio_no 0x00000000
265 #define regk_gio_off 0x00000000
266 #define regk_gio_posedge 0x00000005
267 #define regk_gio_rw_intr_cfg_default 0x00000000
268 #define regk_gio_rw_intr_mask_default 0x00000000
269 #define regk_gio_rw_pa_oe_default 0x00000000
270 #define regk_gio_rw_pb_oe_default 0x00000000
271 #define regk_gio_rw_pc_oe_default 0x00000000
272 #define regk_gio_rw_pd_oe_default 0x00000000
273 #define regk_gio_rw_pe_oe_default 0x00000000
274 #define regk_gio_set 0x00000003
275 #define regk_gio_yes 0x00000001
276 #endif /* __gio_defs_asm_h */