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intr_vect_defs.h
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1 #ifndef __intr_vect_defs_h
2 #define __intr_vect_defs_h
3 
4 /*
5  * This file is autogenerated from
6  * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r
7  * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp
8  * last modfied: Mon Apr 11 16:08:03 2005
9  *
10  * by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
11  * id: $Id: intr_vect_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
12  * Any changes here will be lost.
13  *
14  * -*- buffer-read-only: t -*-
15  */
16 /* Main access macros */
17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \
19  REG_READ( reg_##scope##_##reg, \
20  (inst) + REG_RD_ADDR_##scope##_##reg )
21 #endif
22 
23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \
25  REG_WRITE( reg_##scope##_##reg, \
26  (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #endif
28 
29 #ifndef REG_RD_VECT
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31  REG_READ( reg_##scope##_##reg, \
32  (inst) + REG_RD_ADDR_##scope##_##reg + \
33  (index) * STRIDE_##scope##_##reg )
34 #endif
35 
36 #ifndef REG_WR_VECT
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38  REG_WRITE( reg_##scope##_##reg, \
39  (inst) + REG_WR_ADDR_##scope##_##reg + \
40  (index) * STRIDE_##scope##_##reg, (val) )
41 #endif
42 
43 #ifndef REG_RD_INT
44 #define REG_RD_INT( scope, inst, reg ) \
45  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #endif
47 
48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \
50  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #endif
52 
53 #ifndef REG_RD_INT_VECT
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56  (index) * STRIDE_##scope##_##reg )
57 #endif
58 
59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62  (index) * STRIDE_##scope##_##reg, (val) )
63 #endif
64 
65 #ifndef REG_TYPE_CONV
66 #define REG_TYPE_CONV( type, orgtype, val ) \
67  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68 #endif
69 
70 #ifndef reg_page_size
71 #define reg_page_size 8192
72 #endif
73 
74 #ifndef REG_ADDR
75 #define REG_ADDR( scope, inst, reg ) \
76  ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #endif
78 
79 #ifndef REG_ADDR_VECT
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82  (index) * STRIDE_##scope##_##reg )
83 #endif
84 
85 /* C-code for register scope intr_vect */
86 
87 #define STRIDE_intr_vect_rw_mask 0
88 /* Register rw_mask, scope intr_vect, type rw */
89 typedef struct {
90  unsigned int memarb : 1;
91  unsigned int gen_io : 1;
92  unsigned int iop0 : 1;
93  unsigned int iop1 : 1;
94  unsigned int iop2 : 1;
95  unsigned int iop3 : 1;
96  unsigned int dma0 : 1;
97  unsigned int dma1 : 1;
98  unsigned int dma2 : 1;
99  unsigned int dma3 : 1;
100  unsigned int dma4 : 1;
101  unsigned int dma5 : 1;
102  unsigned int dma6 : 1;
103  unsigned int dma7 : 1;
104  unsigned int dma8 : 1;
105  unsigned int dma9 : 1;
106  unsigned int ata : 1;
107  unsigned int sser0 : 1;
108  unsigned int sser1 : 1;
109  unsigned int ser0 : 1;
110  unsigned int ser1 : 1;
111  unsigned int ser2 : 1;
112  unsigned int ser3 : 1;
113  unsigned int p21 : 1;
114  unsigned int eth0 : 1;
115  unsigned int eth1 : 1;
116  unsigned int timer0 : 1;
117  unsigned int bif_arb : 1;
118  unsigned int bif_dma : 1;
119  unsigned int ext : 1;
120  unsigned int dummy1 : 2;
121 } reg_intr_vect_rw_mask;
122 #define REG_RD_ADDR_intr_vect_rw_mask 0
123 #define REG_WR_ADDR_intr_vect_rw_mask 0
124 
125 #define STRIDE_intr_vect_r_vect 0
126 /* Register r_vect, scope intr_vect, type r */
127 typedef struct {
128  unsigned int memarb : 1;
129  unsigned int gen_io : 1;
130  unsigned int iop0 : 1;
131  unsigned int iop1 : 1;
132  unsigned int iop2 : 1;
133  unsigned int iop3 : 1;
134  unsigned int dma0 : 1;
135  unsigned int dma1 : 1;
136  unsigned int dma2 : 1;
137  unsigned int dma3 : 1;
138  unsigned int dma4 : 1;
139  unsigned int dma5 : 1;
140  unsigned int dma6 : 1;
141  unsigned int dma7 : 1;
142  unsigned int dma8 : 1;
143  unsigned int dma9 : 1;
144  unsigned int ata : 1;
145  unsigned int sser0 : 1;
146  unsigned int sser1 : 1;
147  unsigned int ser0 : 1;
148  unsigned int ser1 : 1;
149  unsigned int ser2 : 1;
150  unsigned int ser3 : 1;
151  unsigned int p21 : 1;
152  unsigned int eth0 : 1;
153  unsigned int eth1 : 1;
154  unsigned int timer : 1;
155  unsigned int bif_arb : 1;
156  unsigned int bif_dma : 1;
157  unsigned int ext : 1;
158  unsigned int dummy1 : 2;
159 } reg_intr_vect_r_vect;
160 #define REG_RD_ADDR_intr_vect_r_vect 4
161 
162 #define STRIDE_intr_vect_r_masked_vect 0
163 /* Register r_masked_vect, scope intr_vect, type r */
164 typedef struct {
165  unsigned int memarb : 1;
166  unsigned int gen_io : 1;
167  unsigned int iop0 : 1;
168  unsigned int iop1 : 1;
169  unsigned int iop2 : 1;
170  unsigned int iop3 : 1;
171  unsigned int dma0 : 1;
172  unsigned int dma1 : 1;
173  unsigned int dma2 : 1;
174  unsigned int dma3 : 1;
175  unsigned int dma4 : 1;
176  unsigned int dma5 : 1;
177  unsigned int dma6 : 1;
178  unsigned int dma7 : 1;
179  unsigned int dma8 : 1;
180  unsigned int dma9 : 1;
181  unsigned int ata : 1;
182  unsigned int sser0 : 1;
183  unsigned int sser1 : 1;
184  unsigned int ser0 : 1;
185  unsigned int ser1 : 1;
186  unsigned int ser2 : 1;
187  unsigned int ser3 : 1;
188  unsigned int p21 : 1;
189  unsigned int eth0 : 1;
190  unsigned int eth1 : 1;
191  unsigned int timer : 1;
192  unsigned int bif_arb : 1;
193  unsigned int bif_dma : 1;
194  unsigned int ext : 1;
195  unsigned int dummy1 : 2;
196 } reg_intr_vect_r_masked_vect;
197 #define REG_RD_ADDR_intr_vect_r_masked_vect 8
198 
199 /* Register r_nmi, scope intr_vect, type r */
200 typedef struct {
201  unsigned int ext : 1;
202  unsigned int watchdog : 1;
203  unsigned int dummy1 : 30;
204 } reg_intr_vect_r_nmi;
205 #define REG_RD_ADDR_intr_vect_r_nmi 12
206 
207 /* Register r_guru, scope intr_vect, type r */
208 typedef struct {
209  unsigned int jtag : 1;
210  unsigned int dummy1 : 31;
211 } reg_intr_vect_r_guru;
212 #define REG_RD_ADDR_intr_vect_r_guru 16
213 
214 /* Register rw_ipi, scope intr_vect, type rw */
215 typedef struct
216 {
217  unsigned int vector;
218 } reg_intr_vect_rw_ipi;
219 #define REG_RD_ADDR_intr_vect_rw_ipi 20
220 #define REG_WR_ADDR_intr_vect_rw_ipi 20
221 
222 /* Constants */
223 enum {
224  regk_intr_vect_off = 0x00000000,
225  regk_intr_vect_on = 0x00000001,
226  regk_intr_vect_rw_mask_default = 0x00000000
227 };
228 #endif /* __intr_vect_defs_h */
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