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irqs.h
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1 /*
2  * arch/arm/mach-h720x/include/mach/irqs.h
3  *
4  * Copyright (C) 2000 Jungjun Kim
5  * (C) 2003 Robert Schwebel <[email protected]>
6  * (C) 2003 Thomas Gleixner <[email protected]>
7  *
8  */
9 
10 #ifndef __ASM_ARCH_IRQS_H
11 #define __ASM_ARCH_IRQS_H
12 
13 #if defined (CONFIG_CPU_H7201)
14 
15 #define IRQ_PMU 0 /* 0x000001 */
16 #define IRQ_DMA 1 /* 0x000002 */
17 #define IRQ_LCD 2 /* 0x000004 */
18 #define IRQ_VGA 3 /* 0x000008 */
19 #define IRQ_PCMCIA1 4 /* 0x000010 */
20 #define IRQ_PCMCIA2 5 /* 0x000020 */
21 #define IRQ_AFE 6 /* 0x000040 */
22 #define IRQ_AIC 7 /* 0x000080 */
23 #define IRQ_KEYBOARD 8 /* 0x000100 */
24 #define IRQ_TIMER0 9 /* 0x000200 */
25 #define IRQ_RTC 10 /* 0x000400 */
26 #define IRQ_SOUND 11 /* 0x000800 */
27 #define IRQ_USB 12 /* 0x001000 */
28 #define IRQ_IrDA 13 /* 0x002000 */
29 #define IRQ_UART0 14 /* 0x004000 */
30 #define IRQ_UART1 15 /* 0x008000 */
31 #define IRQ_SPI 16 /* 0x010000 */
32 #define IRQ_GPIOA 17 /* 0x020000 */
33 #define IRQ_GPIOB 18 /* 0x040000 */
34 #define IRQ_GPIOC 19 /* 0x080000 */
35 #define IRQ_GPIOD 20 /* 0x100000 */
36 #define IRQ_CommRX 21 /* 0x200000 */
37 #define IRQ_CommTX 22 /* 0x400000 */
38 #define IRQ_Soft 23 /* 0x800000 */
39 
40 #define NR_GLBL_IRQS 24
41 
42 #define IRQ_CHAINED_GPIOA(x) (NR_GLBL_IRQS + x)
43 #define IRQ_CHAINED_GPIOB(x) (IRQ_CHAINED_GPIOA(32) + x)
44 #define IRQ_CHAINED_GPIOC(x) (IRQ_CHAINED_GPIOB(32) + x)
45 #define IRQ_CHAINED_GPIOD(x) (IRQ_CHAINED_GPIOC(32) + x)
46 #define NR_IRQS IRQ_CHAINED_GPIOD(32)
47 
48 /* Enable mask for multiplexed interrupts */
49 #define IRQ_ENA_MUX (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) \
50  | (1<<IRQ_GPIOC) | (1<<IRQ_GPIOD)
51 
52 
53 #elif defined (CONFIG_CPU_H7202)
54 
55 #define IRQ_PMU 0 /* 0x00000001 */
56 #define IRQ_DMA 1 /* 0x00000002 */
57 #define IRQ_LCD 2 /* 0x00000004 */
58 #define IRQ_SOUND 3 /* 0x00000008 */
59 #define IRQ_I2S 4 /* 0x00000010 */
60 #define IRQ_USB 5 /* 0x00000020 */
61 #define IRQ_MMC 6 /* 0x00000040 */
62 #define IRQ_RTC 7 /* 0x00000080 */
63 #define IRQ_UART0 8 /* 0x00000100 */
64 #define IRQ_UART1 9 /* 0x00000200 */
65 #define IRQ_UART2 10 /* 0x00000400 */
66 #define IRQ_UART3 11 /* 0x00000800 */
67 #define IRQ_KBD 12 /* 0x00001000 */
68 #define IRQ_PS2 13 /* 0x00002000 */
69 #define IRQ_AIC 14 /* 0x00004000 */
70 #define IRQ_TIMER0 15 /* 0x00008000 */
71 #define IRQ_TIMERX 16 /* 0x00010000 */
72 #define IRQ_WDT 17 /* 0x00020000 */
73 #define IRQ_CAN0 18 /* 0x00040000 */
74 #define IRQ_CAN1 19 /* 0x00080000 */
75 #define IRQ_EXT0 20 /* 0x00100000 */
76 #define IRQ_EXT1 21 /* 0x00200000 */
77 #define IRQ_GPIOA 22 /* 0x00400000 */
78 #define IRQ_GPIOB 23 /* 0x00800000 */
79 #define IRQ_GPIOC 24 /* 0x01000000 */
80 #define IRQ_GPIOD 25 /* 0x02000000 */
81 #define IRQ_GPIOE 26 /* 0x04000000 */
82 #define IRQ_COMMRX 27 /* 0x08000000 */
83 #define IRQ_COMMTX 28 /* 0x10000000 */
84 #define IRQ_SMC 29 /* 0x20000000 */
85 #define IRQ_Soft 30 /* 0x40000000 */
86 #define IRQ_RESERVED1 31 /* 0x80000000 */
87 #define NR_GLBL_IRQS 32
88 
89 #define NR_TIMERX_IRQS 3
90 
91 #define IRQ_CHAINED_GPIOA(x) (NR_GLBL_IRQS + x)
92 #define IRQ_CHAINED_GPIOB(x) (IRQ_CHAINED_GPIOA(32) + x)
93 #define IRQ_CHAINED_GPIOC(x) (IRQ_CHAINED_GPIOB(32) + x)
94 #define IRQ_CHAINED_GPIOD(x) (IRQ_CHAINED_GPIOC(32) + x)
95 #define IRQ_CHAINED_GPIOE(x) (IRQ_CHAINED_GPIOD(32) + x)
96 #define IRQ_CHAINED_TIMERX(x) (IRQ_CHAINED_GPIOE(32) + x)
97 #define IRQ_TIMER1 (IRQ_CHAINED_TIMERX(0))
98 #define IRQ_TIMER2 (IRQ_CHAINED_TIMERX(1))
99 #define IRQ_TIMER64B (IRQ_CHAINED_TIMERX(2))
100 
101 #define NR_IRQS (IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS))
102 
103 /* Enable mask for multiplexed interrupts */
104 #define IRQ_ENA_MUX (1<<IRQ_TIMERX) | (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) | \
105  (1<<IRQ_GPIOC) | (1<<IRQ_GPIOD) | (1<<IRQ_GPIOE) | \
106  (1<<IRQ_TIMERX)
107 
108 #else
109 #error cpu definition mismatch
110 #endif
111 
112 /* decode irq number to register number */
113 #define IRQ_TO_REGNO(irq) ((irq - NR_GLBL_IRQS) >> 5)
114 #define IRQ_TO_BIT(irq) (1 << ((irq - NR_GLBL_IRQS) % 32))
115 
116 #endif