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11 #ifndef __ASM_ARCH_BRIDGE_REGS_H
12 #define __ASM_ARCH_BRIDGE_REGS_H
16 #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
18 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
20 #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
21 #define WDT_RESET_OUT_EN 0x0002
23 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
25 #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
27 #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
29 #define WDT_INT_REQ 0x0008
31 #define BRIDGE_INT_TIMER1_CLR (~0x0004)
33 #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
35 #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
37 #define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300)
38 #define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300)