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13 #ifndef __ASM_SH_MAGICPANELR2_H
14 #define __ASM_SH_MAGICPANELR2_H
18 #define __IO_PREFIX mpr2
22 #define SETBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) | mask, reg)
23 #define SETBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) | mask, reg)
24 #define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg)
25 #define CLRBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) & ~mask, reg)
26 #define CLRBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) & ~mask, reg)
27 #define CLRBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) & ~mask, reg)
30 #define PA_LED PORT_PADR
34 #define CMNCR 0xA4FD0000UL
35 #define CS0BCR 0xA4FD0004UL
36 #define CS2BCR 0xA4FD0008UL
37 #define CS3BCR 0xA4FD000CUL
38 #define CS4BCR 0xA4FD0010UL
39 #define CS5ABCR 0xA4FD0014UL
40 #define CS5BBCR 0xA4FD0018UL
41 #define CS6ABCR 0xA4FD001CUL
42 #define CS6BBCR 0xA4FD0020UL
43 #define CS0WCR 0xA4FD0024UL
44 #define CS2WCR 0xA4FD0028UL
45 #define CS3WCR 0xA4FD002CUL
46 #define CS4WCR 0xA4FD0030UL
47 #define CS5AWCR 0xA4FD0034UL
48 #define CS5BWCR 0xA4FD0038UL
49 #define CS6AWCR 0xA4FD003CUL
50 #define CS6BWCR 0xA4FD0040UL
55 #define PORT_UTRCTL 0xA405012CUL
56 #define PORT_UCLKCR_W 0xA40A0008UL
58 #define INTC_ICR0 0xA414FEE0UL
59 #define INTC_ICR1 0xA4140010UL
60 #define INTC_ICR2 0xA4140012UL
64 #define MPR2_MTD_BOOTLOADER_SIZE 0x00060000UL
65 #define MPR2_MTD_KERNEL_SIZE 0x00200000UL