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marb_defs_asm.h
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1 #ifndef __marb_defs_asm_h
2 #define __marb_defs_asm_h
3 
4 /*
5  * This file is autogenerated from
6  * file: ../../inst/memarb/rtl/guinness/marb_top.r
7  * id: <not found>
8  * last modfied: Mon Apr 11 16:12:16 2005
9  *
10  * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r
11  * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
12  * Any changes here will be lost.
13  *
14  * -*- buffer-read-only: t -*-
15  */
16 
17 #ifndef REG_FIELD
18 #define REG_FIELD( scope, reg, field, value ) \
19  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20 #define REG_FIELD_X_( value, shift ) ((value) << shift)
21 #endif
22 
23 #ifndef REG_STATE
24 #define REG_STATE( scope, reg, field, symbolic_value ) \
25  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26 #define REG_STATE_X_( k, shift ) (k << shift)
27 #endif
28 
29 #ifndef REG_MASK
30 #define REG_MASK( scope, reg, field ) \
31  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33 #endif
34 
35 #ifndef REG_LSB
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37 #endif
38 
39 #ifndef REG_BIT
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41 #endif
42 
43 #ifndef REG_ADDR
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46 #endif
47 
48 #ifndef REG_ADDR_VECT
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50  REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51  STRIDE_##scope##_##reg )
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53  ((inst) + offs + (index) * stride)
54 #endif
55 
56 #define STRIDE_marb_rw_int_slots 4
57 /* Register rw_int_slots, scope marb, type rw */
58 #define reg_marb_rw_int_slots___owner___lsb 0
59 #define reg_marb_rw_int_slots___owner___width 4
60 #define reg_marb_rw_int_slots_offset 0
61 
62 #define STRIDE_marb_rw_ext_slots 4
63 /* Register rw_ext_slots, scope marb, type rw */
64 #define reg_marb_rw_ext_slots___owner___lsb 0
65 #define reg_marb_rw_ext_slots___owner___width 4
66 #define reg_marb_rw_ext_slots_offset 256
67 
68 #define STRIDE_marb_rw_regs_slots 4
69 /* Register rw_regs_slots, scope marb, type rw */
70 #define reg_marb_rw_regs_slots___owner___lsb 0
71 #define reg_marb_rw_regs_slots___owner___width 4
72 #define reg_marb_rw_regs_slots_offset 512
73 
74 /* Register rw_intr_mask, scope marb, type rw */
75 #define reg_marb_rw_intr_mask___bp0___lsb 0
76 #define reg_marb_rw_intr_mask___bp0___width 1
77 #define reg_marb_rw_intr_mask___bp0___bit 0
78 #define reg_marb_rw_intr_mask___bp1___lsb 1
79 #define reg_marb_rw_intr_mask___bp1___width 1
80 #define reg_marb_rw_intr_mask___bp1___bit 1
81 #define reg_marb_rw_intr_mask___bp2___lsb 2
82 #define reg_marb_rw_intr_mask___bp2___width 1
83 #define reg_marb_rw_intr_mask___bp2___bit 2
84 #define reg_marb_rw_intr_mask___bp3___lsb 3
85 #define reg_marb_rw_intr_mask___bp3___width 1
86 #define reg_marb_rw_intr_mask___bp3___bit 3
87 #define reg_marb_rw_intr_mask_offset 528
88 
89 /* Register rw_ack_intr, scope marb, type rw */
90 #define reg_marb_rw_ack_intr___bp0___lsb 0
91 #define reg_marb_rw_ack_intr___bp0___width 1
92 #define reg_marb_rw_ack_intr___bp0___bit 0
93 #define reg_marb_rw_ack_intr___bp1___lsb 1
94 #define reg_marb_rw_ack_intr___bp1___width 1
95 #define reg_marb_rw_ack_intr___bp1___bit 1
96 #define reg_marb_rw_ack_intr___bp2___lsb 2
97 #define reg_marb_rw_ack_intr___bp2___width 1
98 #define reg_marb_rw_ack_intr___bp2___bit 2
99 #define reg_marb_rw_ack_intr___bp3___lsb 3
100 #define reg_marb_rw_ack_intr___bp3___width 1
101 #define reg_marb_rw_ack_intr___bp3___bit 3
102 #define reg_marb_rw_ack_intr_offset 532
103 
104 /* Register r_intr, scope marb, type r */
105 #define reg_marb_r_intr___bp0___lsb 0
106 #define reg_marb_r_intr___bp0___width 1
107 #define reg_marb_r_intr___bp0___bit 0
108 #define reg_marb_r_intr___bp1___lsb 1
109 #define reg_marb_r_intr___bp1___width 1
110 #define reg_marb_r_intr___bp1___bit 1
111 #define reg_marb_r_intr___bp2___lsb 2
112 #define reg_marb_r_intr___bp2___width 1
113 #define reg_marb_r_intr___bp2___bit 2
114 #define reg_marb_r_intr___bp3___lsb 3
115 #define reg_marb_r_intr___bp3___width 1
116 #define reg_marb_r_intr___bp3___bit 3
117 #define reg_marb_r_intr_offset 536
118 
119 /* Register r_masked_intr, scope marb, type r */
120 #define reg_marb_r_masked_intr___bp0___lsb 0
121 #define reg_marb_r_masked_intr___bp0___width 1
122 #define reg_marb_r_masked_intr___bp0___bit 0
123 #define reg_marb_r_masked_intr___bp1___lsb 1
124 #define reg_marb_r_masked_intr___bp1___width 1
125 #define reg_marb_r_masked_intr___bp1___bit 1
126 #define reg_marb_r_masked_intr___bp2___lsb 2
127 #define reg_marb_r_masked_intr___bp2___width 1
128 #define reg_marb_r_masked_intr___bp2___bit 2
129 #define reg_marb_r_masked_intr___bp3___lsb 3
130 #define reg_marb_r_masked_intr___bp3___width 1
131 #define reg_marb_r_masked_intr___bp3___bit 3
132 #define reg_marb_r_masked_intr_offset 540
133 
134 /* Register rw_stop_mask, scope marb, type rw */
135 #define reg_marb_rw_stop_mask___dma0___lsb 0
136 #define reg_marb_rw_stop_mask___dma0___width 1
137 #define reg_marb_rw_stop_mask___dma0___bit 0
138 #define reg_marb_rw_stop_mask___dma1___lsb 1
139 #define reg_marb_rw_stop_mask___dma1___width 1
140 #define reg_marb_rw_stop_mask___dma1___bit 1
141 #define reg_marb_rw_stop_mask___dma2___lsb 2
142 #define reg_marb_rw_stop_mask___dma2___width 1
143 #define reg_marb_rw_stop_mask___dma2___bit 2
144 #define reg_marb_rw_stop_mask___dma3___lsb 3
145 #define reg_marb_rw_stop_mask___dma3___width 1
146 #define reg_marb_rw_stop_mask___dma3___bit 3
147 #define reg_marb_rw_stop_mask___dma4___lsb 4
148 #define reg_marb_rw_stop_mask___dma4___width 1
149 #define reg_marb_rw_stop_mask___dma4___bit 4
150 #define reg_marb_rw_stop_mask___dma5___lsb 5
151 #define reg_marb_rw_stop_mask___dma5___width 1
152 #define reg_marb_rw_stop_mask___dma5___bit 5
153 #define reg_marb_rw_stop_mask___dma6___lsb 6
154 #define reg_marb_rw_stop_mask___dma6___width 1
155 #define reg_marb_rw_stop_mask___dma6___bit 6
156 #define reg_marb_rw_stop_mask___dma7___lsb 7
157 #define reg_marb_rw_stop_mask___dma7___width 1
158 #define reg_marb_rw_stop_mask___dma7___bit 7
159 #define reg_marb_rw_stop_mask___dma8___lsb 8
160 #define reg_marb_rw_stop_mask___dma8___width 1
161 #define reg_marb_rw_stop_mask___dma8___bit 8
162 #define reg_marb_rw_stop_mask___dma9___lsb 9
163 #define reg_marb_rw_stop_mask___dma9___width 1
164 #define reg_marb_rw_stop_mask___dma9___bit 9
165 #define reg_marb_rw_stop_mask___cpui___lsb 10
166 #define reg_marb_rw_stop_mask___cpui___width 1
167 #define reg_marb_rw_stop_mask___cpui___bit 10
168 #define reg_marb_rw_stop_mask___cpud___lsb 11
169 #define reg_marb_rw_stop_mask___cpud___width 1
170 #define reg_marb_rw_stop_mask___cpud___bit 11
171 #define reg_marb_rw_stop_mask___iop___lsb 12
172 #define reg_marb_rw_stop_mask___iop___width 1
173 #define reg_marb_rw_stop_mask___iop___bit 12
174 #define reg_marb_rw_stop_mask___slave___lsb 13
175 #define reg_marb_rw_stop_mask___slave___width 1
176 #define reg_marb_rw_stop_mask___slave___bit 13
177 #define reg_marb_rw_stop_mask_offset 544
178 
179 /* Register r_stopped, scope marb, type r */
180 #define reg_marb_r_stopped___dma0___lsb 0
181 #define reg_marb_r_stopped___dma0___width 1
182 #define reg_marb_r_stopped___dma0___bit 0
183 #define reg_marb_r_stopped___dma1___lsb 1
184 #define reg_marb_r_stopped___dma1___width 1
185 #define reg_marb_r_stopped___dma1___bit 1
186 #define reg_marb_r_stopped___dma2___lsb 2
187 #define reg_marb_r_stopped___dma2___width 1
188 #define reg_marb_r_stopped___dma2___bit 2
189 #define reg_marb_r_stopped___dma3___lsb 3
190 #define reg_marb_r_stopped___dma3___width 1
191 #define reg_marb_r_stopped___dma3___bit 3
192 #define reg_marb_r_stopped___dma4___lsb 4
193 #define reg_marb_r_stopped___dma4___width 1
194 #define reg_marb_r_stopped___dma4___bit 4
195 #define reg_marb_r_stopped___dma5___lsb 5
196 #define reg_marb_r_stopped___dma5___width 1
197 #define reg_marb_r_stopped___dma5___bit 5
198 #define reg_marb_r_stopped___dma6___lsb 6
199 #define reg_marb_r_stopped___dma6___width 1
200 #define reg_marb_r_stopped___dma6___bit 6
201 #define reg_marb_r_stopped___dma7___lsb 7
202 #define reg_marb_r_stopped___dma7___width 1
203 #define reg_marb_r_stopped___dma7___bit 7
204 #define reg_marb_r_stopped___dma8___lsb 8
205 #define reg_marb_r_stopped___dma8___width 1
206 #define reg_marb_r_stopped___dma8___bit 8
207 #define reg_marb_r_stopped___dma9___lsb 9
208 #define reg_marb_r_stopped___dma9___width 1
209 #define reg_marb_r_stopped___dma9___bit 9
210 #define reg_marb_r_stopped___cpui___lsb 10
211 #define reg_marb_r_stopped___cpui___width 1
212 #define reg_marb_r_stopped___cpui___bit 10
213 #define reg_marb_r_stopped___cpud___lsb 11
214 #define reg_marb_r_stopped___cpud___width 1
215 #define reg_marb_r_stopped___cpud___bit 11
216 #define reg_marb_r_stopped___iop___lsb 12
217 #define reg_marb_r_stopped___iop___width 1
218 #define reg_marb_r_stopped___iop___bit 12
219 #define reg_marb_r_stopped___slave___lsb 13
220 #define reg_marb_r_stopped___slave___width 1
221 #define reg_marb_r_stopped___slave___bit 13
222 #define reg_marb_r_stopped_offset 548
223 
224 /* Register rw_no_snoop, scope marb, type rw */
225 #define reg_marb_rw_no_snoop___dma0___lsb 0
226 #define reg_marb_rw_no_snoop___dma0___width 1
227 #define reg_marb_rw_no_snoop___dma0___bit 0
228 #define reg_marb_rw_no_snoop___dma1___lsb 1
229 #define reg_marb_rw_no_snoop___dma1___width 1
230 #define reg_marb_rw_no_snoop___dma1___bit 1
231 #define reg_marb_rw_no_snoop___dma2___lsb 2
232 #define reg_marb_rw_no_snoop___dma2___width 1
233 #define reg_marb_rw_no_snoop___dma2___bit 2
234 #define reg_marb_rw_no_snoop___dma3___lsb 3
235 #define reg_marb_rw_no_snoop___dma3___width 1
236 #define reg_marb_rw_no_snoop___dma3___bit 3
237 #define reg_marb_rw_no_snoop___dma4___lsb 4
238 #define reg_marb_rw_no_snoop___dma4___width 1
239 #define reg_marb_rw_no_snoop___dma4___bit 4
240 #define reg_marb_rw_no_snoop___dma5___lsb 5
241 #define reg_marb_rw_no_snoop___dma5___width 1
242 #define reg_marb_rw_no_snoop___dma5___bit 5
243 #define reg_marb_rw_no_snoop___dma6___lsb 6
244 #define reg_marb_rw_no_snoop___dma6___width 1
245 #define reg_marb_rw_no_snoop___dma6___bit 6
246 #define reg_marb_rw_no_snoop___dma7___lsb 7
247 #define reg_marb_rw_no_snoop___dma7___width 1
248 #define reg_marb_rw_no_snoop___dma7___bit 7
249 #define reg_marb_rw_no_snoop___dma8___lsb 8
250 #define reg_marb_rw_no_snoop___dma8___width 1
251 #define reg_marb_rw_no_snoop___dma8___bit 8
252 #define reg_marb_rw_no_snoop___dma9___lsb 9
253 #define reg_marb_rw_no_snoop___dma9___width 1
254 #define reg_marb_rw_no_snoop___dma9___bit 9
255 #define reg_marb_rw_no_snoop___cpui___lsb 10
256 #define reg_marb_rw_no_snoop___cpui___width 1
257 #define reg_marb_rw_no_snoop___cpui___bit 10
258 #define reg_marb_rw_no_snoop___cpud___lsb 11
259 #define reg_marb_rw_no_snoop___cpud___width 1
260 #define reg_marb_rw_no_snoop___cpud___bit 11
261 #define reg_marb_rw_no_snoop___iop___lsb 12
262 #define reg_marb_rw_no_snoop___iop___width 1
263 #define reg_marb_rw_no_snoop___iop___bit 12
264 #define reg_marb_rw_no_snoop___slave___lsb 13
265 #define reg_marb_rw_no_snoop___slave___width 1
266 #define reg_marb_rw_no_snoop___slave___bit 13
267 #define reg_marb_rw_no_snoop_offset 832
268 
269 /* Register rw_no_snoop_rq, scope marb, type rw */
270 #define reg_marb_rw_no_snoop_rq___cpui___lsb 10
271 #define reg_marb_rw_no_snoop_rq___cpui___width 1
272 #define reg_marb_rw_no_snoop_rq___cpui___bit 10
273 #define reg_marb_rw_no_snoop_rq___cpud___lsb 11
274 #define reg_marb_rw_no_snoop_rq___cpud___width 1
275 #define reg_marb_rw_no_snoop_rq___cpud___bit 11
276 #define reg_marb_rw_no_snoop_rq_offset 836
277 
278 
279 /* Constants */
280 #define regk_marb_cpud 0x0000000b
281 #define regk_marb_cpui 0x0000000a
282 #define regk_marb_dma0 0x00000000
283 #define regk_marb_dma1 0x00000001
284 #define regk_marb_dma2 0x00000002
285 #define regk_marb_dma3 0x00000003
286 #define regk_marb_dma4 0x00000004
287 #define regk_marb_dma5 0x00000005
288 #define regk_marb_dma6 0x00000006
289 #define regk_marb_dma7 0x00000007
290 #define regk_marb_dma8 0x00000008
291 #define regk_marb_dma9 0x00000009
292 #define regk_marb_iop 0x0000000c
293 #define regk_marb_no 0x00000000
294 #define regk_marb_r_stopped_default 0x00000000
295 #define regk_marb_rw_ext_slots_default 0x00000000
296 #define regk_marb_rw_ext_slots_size 0x00000040
297 #define regk_marb_rw_int_slots_default 0x00000000
298 #define regk_marb_rw_int_slots_size 0x00000040
299 #define regk_marb_rw_intr_mask_default 0x00000000
300 #define regk_marb_rw_no_snoop_default 0x00000000
301 #define regk_marb_rw_no_snoop_rq_default 0x00000000
302 #define regk_marb_rw_regs_slots_default 0x00000000
303 #define regk_marb_rw_regs_slots_size 0x00000004
304 #define regk_marb_rw_stop_mask_default 0x00000000
305 #define regk_marb_slave 0x0000000d
306 #define regk_marb_yes 0x00000001
307 #endif /* __marb_defs_asm_h */
308 #ifndef __marb_bp_defs_asm_h
309 #define __marb_bp_defs_asm_h
310 
311 /*
312  * This file is autogenerated from
313  * file: ../../inst/memarb/rtl/guinness/marb_top.r
314  * id: <not found>
315  * last modfied: Mon Apr 11 16:12:16 2005
316  *
317  * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r
318  * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
319  * Any changes here will be lost.
320  *
321  * -*- buffer-read-only: t -*-
322  */
323 
324 #ifndef REG_FIELD
325 #define REG_FIELD( scope, reg, field, value ) \
326  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
327 #define REG_FIELD_X_( value, shift ) ((value) << shift)
328 #endif
329 
330 #ifndef REG_STATE
331 #define REG_STATE( scope, reg, field, symbolic_value ) \
332  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
333 #define REG_STATE_X_( k, shift ) (k << shift)
334 #endif
335 
336 #ifndef REG_MASK
337 #define REG_MASK( scope, reg, field ) \
338  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
339 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
340 #endif
341 
342 #ifndef REG_LSB
343 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
344 #endif
345 
346 #ifndef REG_BIT
347 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
348 #endif
349 
350 #ifndef REG_ADDR
351 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
352 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
353 #endif
354 
355 #ifndef REG_ADDR_VECT
356 #define REG_ADDR_VECT( scope, inst, reg, index ) \
357  REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
358  STRIDE_##scope##_##reg )
359 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
360  ((inst) + offs + (index) * stride)
361 #endif
362 
363 /* Register rw_first_addr, scope marb_bp, type rw */
364 #define reg_marb_bp_rw_first_addr_offset 0
365 
366 /* Register rw_last_addr, scope marb_bp, type rw */
367 #define reg_marb_bp_rw_last_addr_offset 4
368 
369 /* Register rw_op, scope marb_bp, type rw */
370 #define reg_marb_bp_rw_op___rd___lsb 0
371 #define reg_marb_bp_rw_op___rd___width 1
372 #define reg_marb_bp_rw_op___rd___bit 0
373 #define reg_marb_bp_rw_op___wr___lsb 1
374 #define reg_marb_bp_rw_op___wr___width 1
375 #define reg_marb_bp_rw_op___wr___bit 1
376 #define reg_marb_bp_rw_op___rd_excl___lsb 2
377 #define reg_marb_bp_rw_op___rd_excl___width 1
378 #define reg_marb_bp_rw_op___rd_excl___bit 2
379 #define reg_marb_bp_rw_op___pri_wr___lsb 3
380 #define reg_marb_bp_rw_op___pri_wr___width 1
381 #define reg_marb_bp_rw_op___pri_wr___bit 3
382 #define reg_marb_bp_rw_op___us_rd___lsb 4
383 #define reg_marb_bp_rw_op___us_rd___width 1
384 #define reg_marb_bp_rw_op___us_rd___bit 4
385 #define reg_marb_bp_rw_op___us_wr___lsb 5
386 #define reg_marb_bp_rw_op___us_wr___width 1
387 #define reg_marb_bp_rw_op___us_wr___bit 5
388 #define reg_marb_bp_rw_op___us_rd_excl___lsb 6
389 #define reg_marb_bp_rw_op___us_rd_excl___width 1
390 #define reg_marb_bp_rw_op___us_rd_excl___bit 6
391 #define reg_marb_bp_rw_op___us_pri_wr___lsb 7
392 #define reg_marb_bp_rw_op___us_pri_wr___width 1
393 #define reg_marb_bp_rw_op___us_pri_wr___bit 7
394 #define reg_marb_bp_rw_op_offset 8
395 
396 /* Register rw_clients, scope marb_bp, type rw */
397 #define reg_marb_bp_rw_clients___dma0___lsb 0
398 #define reg_marb_bp_rw_clients___dma0___width 1
399 #define reg_marb_bp_rw_clients___dma0___bit 0
400 #define reg_marb_bp_rw_clients___dma1___lsb 1
401 #define reg_marb_bp_rw_clients___dma1___width 1
402 #define reg_marb_bp_rw_clients___dma1___bit 1
403 #define reg_marb_bp_rw_clients___dma2___lsb 2
404 #define reg_marb_bp_rw_clients___dma2___width 1
405 #define reg_marb_bp_rw_clients___dma2___bit 2
406 #define reg_marb_bp_rw_clients___dma3___lsb 3
407 #define reg_marb_bp_rw_clients___dma3___width 1
408 #define reg_marb_bp_rw_clients___dma3___bit 3
409 #define reg_marb_bp_rw_clients___dma4___lsb 4
410 #define reg_marb_bp_rw_clients___dma4___width 1
411 #define reg_marb_bp_rw_clients___dma4___bit 4
412 #define reg_marb_bp_rw_clients___dma5___lsb 5
413 #define reg_marb_bp_rw_clients___dma5___width 1
414 #define reg_marb_bp_rw_clients___dma5___bit 5
415 #define reg_marb_bp_rw_clients___dma6___lsb 6
416 #define reg_marb_bp_rw_clients___dma6___width 1
417 #define reg_marb_bp_rw_clients___dma6___bit 6
418 #define reg_marb_bp_rw_clients___dma7___lsb 7
419 #define reg_marb_bp_rw_clients___dma7___width 1
420 #define reg_marb_bp_rw_clients___dma7___bit 7
421 #define reg_marb_bp_rw_clients___dma8___lsb 8
422 #define reg_marb_bp_rw_clients___dma8___width 1
423 #define reg_marb_bp_rw_clients___dma8___bit 8
424 #define reg_marb_bp_rw_clients___dma9___lsb 9
425 #define reg_marb_bp_rw_clients___dma9___width 1
426 #define reg_marb_bp_rw_clients___dma9___bit 9
427 #define reg_marb_bp_rw_clients___cpui___lsb 10
428 #define reg_marb_bp_rw_clients___cpui___width 1
429 #define reg_marb_bp_rw_clients___cpui___bit 10
430 #define reg_marb_bp_rw_clients___cpud___lsb 11
431 #define reg_marb_bp_rw_clients___cpud___width 1
432 #define reg_marb_bp_rw_clients___cpud___bit 11
433 #define reg_marb_bp_rw_clients___iop___lsb 12
434 #define reg_marb_bp_rw_clients___iop___width 1
435 #define reg_marb_bp_rw_clients___iop___bit 12
436 #define reg_marb_bp_rw_clients___slave___lsb 13
437 #define reg_marb_bp_rw_clients___slave___width 1
438 #define reg_marb_bp_rw_clients___slave___bit 13
439 #define reg_marb_bp_rw_clients_offset 12
440 
441 /* Register rw_options, scope marb_bp, type rw */
442 #define reg_marb_bp_rw_options___wrap___lsb 0
443 #define reg_marb_bp_rw_options___wrap___width 1
444 #define reg_marb_bp_rw_options___wrap___bit 0
445 #define reg_marb_bp_rw_options_offset 16
446 
447 /* Register r_brk_addr, scope marb_bp, type r */
448 #define reg_marb_bp_r_brk_addr_offset 20
449 
450 /* Register r_brk_op, scope marb_bp, type r */
451 #define reg_marb_bp_r_brk_op___rd___lsb 0
452 #define reg_marb_bp_r_brk_op___rd___width 1
453 #define reg_marb_bp_r_brk_op___rd___bit 0
454 #define reg_marb_bp_r_brk_op___wr___lsb 1
455 #define reg_marb_bp_r_brk_op___wr___width 1
456 #define reg_marb_bp_r_brk_op___wr___bit 1
457 #define reg_marb_bp_r_brk_op___rd_excl___lsb 2
458 #define reg_marb_bp_r_brk_op___rd_excl___width 1
459 #define reg_marb_bp_r_brk_op___rd_excl___bit 2
460 #define reg_marb_bp_r_brk_op___pri_wr___lsb 3
461 #define reg_marb_bp_r_brk_op___pri_wr___width 1
462 #define reg_marb_bp_r_brk_op___pri_wr___bit 3
463 #define reg_marb_bp_r_brk_op___us_rd___lsb 4
464 #define reg_marb_bp_r_brk_op___us_rd___width 1
465 #define reg_marb_bp_r_brk_op___us_rd___bit 4
466 #define reg_marb_bp_r_brk_op___us_wr___lsb 5
467 #define reg_marb_bp_r_brk_op___us_wr___width 1
468 #define reg_marb_bp_r_brk_op___us_wr___bit 5
469 #define reg_marb_bp_r_brk_op___us_rd_excl___lsb 6
470 #define reg_marb_bp_r_brk_op___us_rd_excl___width 1
471 #define reg_marb_bp_r_brk_op___us_rd_excl___bit 6
472 #define reg_marb_bp_r_brk_op___us_pri_wr___lsb 7
473 #define reg_marb_bp_r_brk_op___us_pri_wr___width 1
474 #define reg_marb_bp_r_brk_op___us_pri_wr___bit 7
475 #define reg_marb_bp_r_brk_op_offset 24
476 
477 /* Register r_brk_clients, scope marb_bp, type r */
478 #define reg_marb_bp_r_brk_clients___dma0___lsb 0
479 #define reg_marb_bp_r_brk_clients___dma0___width 1
480 #define reg_marb_bp_r_brk_clients___dma0___bit 0
481 #define reg_marb_bp_r_brk_clients___dma1___lsb 1
482 #define reg_marb_bp_r_brk_clients___dma1___width 1
483 #define reg_marb_bp_r_brk_clients___dma1___bit 1
484 #define reg_marb_bp_r_brk_clients___dma2___lsb 2
485 #define reg_marb_bp_r_brk_clients___dma2___width 1
486 #define reg_marb_bp_r_brk_clients___dma2___bit 2
487 #define reg_marb_bp_r_brk_clients___dma3___lsb 3
488 #define reg_marb_bp_r_brk_clients___dma3___width 1
489 #define reg_marb_bp_r_brk_clients___dma3___bit 3
490 #define reg_marb_bp_r_brk_clients___dma4___lsb 4
491 #define reg_marb_bp_r_brk_clients___dma4___width 1
492 #define reg_marb_bp_r_brk_clients___dma4___bit 4
493 #define reg_marb_bp_r_brk_clients___dma5___lsb 5
494 #define reg_marb_bp_r_brk_clients___dma5___width 1
495 #define reg_marb_bp_r_brk_clients___dma5___bit 5
496 #define reg_marb_bp_r_brk_clients___dma6___lsb 6
497 #define reg_marb_bp_r_brk_clients___dma6___width 1
498 #define reg_marb_bp_r_brk_clients___dma6___bit 6
499 #define reg_marb_bp_r_brk_clients___dma7___lsb 7
500 #define reg_marb_bp_r_brk_clients___dma7___width 1
501 #define reg_marb_bp_r_brk_clients___dma7___bit 7
502 #define reg_marb_bp_r_brk_clients___dma8___lsb 8
503 #define reg_marb_bp_r_brk_clients___dma8___width 1
504 #define reg_marb_bp_r_brk_clients___dma8___bit 8
505 #define reg_marb_bp_r_brk_clients___dma9___lsb 9
506 #define reg_marb_bp_r_brk_clients___dma9___width 1
507 #define reg_marb_bp_r_brk_clients___dma9___bit 9
508 #define reg_marb_bp_r_brk_clients___cpui___lsb 10
509 #define reg_marb_bp_r_brk_clients___cpui___width 1
510 #define reg_marb_bp_r_brk_clients___cpui___bit 10
511 #define reg_marb_bp_r_brk_clients___cpud___lsb 11
512 #define reg_marb_bp_r_brk_clients___cpud___width 1
513 #define reg_marb_bp_r_brk_clients___cpud___bit 11
514 #define reg_marb_bp_r_brk_clients___iop___lsb 12
515 #define reg_marb_bp_r_brk_clients___iop___width 1
516 #define reg_marb_bp_r_brk_clients___iop___bit 12
517 #define reg_marb_bp_r_brk_clients___slave___lsb 13
518 #define reg_marb_bp_r_brk_clients___slave___width 1
519 #define reg_marb_bp_r_brk_clients___slave___bit 13
520 #define reg_marb_bp_r_brk_clients_offset 28
521 
522 /* Register r_brk_first_client, scope marb_bp, type r */
523 #define reg_marb_bp_r_brk_first_client___dma0___lsb 0
524 #define reg_marb_bp_r_brk_first_client___dma0___width 1
525 #define reg_marb_bp_r_brk_first_client___dma0___bit 0
526 #define reg_marb_bp_r_brk_first_client___dma1___lsb 1
527 #define reg_marb_bp_r_brk_first_client___dma1___width 1
528 #define reg_marb_bp_r_brk_first_client___dma1___bit 1
529 #define reg_marb_bp_r_brk_first_client___dma2___lsb 2
530 #define reg_marb_bp_r_brk_first_client___dma2___width 1
531 #define reg_marb_bp_r_brk_first_client___dma2___bit 2
532 #define reg_marb_bp_r_brk_first_client___dma3___lsb 3
533 #define reg_marb_bp_r_brk_first_client___dma3___width 1
534 #define reg_marb_bp_r_brk_first_client___dma3___bit 3
535 #define reg_marb_bp_r_brk_first_client___dma4___lsb 4
536 #define reg_marb_bp_r_brk_first_client___dma4___width 1
537 #define reg_marb_bp_r_brk_first_client___dma4___bit 4
538 #define reg_marb_bp_r_brk_first_client___dma5___lsb 5
539 #define reg_marb_bp_r_brk_first_client___dma5___width 1
540 #define reg_marb_bp_r_brk_first_client___dma5___bit 5
541 #define reg_marb_bp_r_brk_first_client___dma6___lsb 6
542 #define reg_marb_bp_r_brk_first_client___dma6___width 1
543 #define reg_marb_bp_r_brk_first_client___dma6___bit 6
544 #define reg_marb_bp_r_brk_first_client___dma7___lsb 7
545 #define reg_marb_bp_r_brk_first_client___dma7___width 1
546 #define reg_marb_bp_r_brk_first_client___dma7___bit 7
547 #define reg_marb_bp_r_brk_first_client___dma8___lsb 8
548 #define reg_marb_bp_r_brk_first_client___dma8___width 1
549 #define reg_marb_bp_r_brk_first_client___dma8___bit 8
550 #define reg_marb_bp_r_brk_first_client___dma9___lsb 9
551 #define reg_marb_bp_r_brk_first_client___dma9___width 1
552 #define reg_marb_bp_r_brk_first_client___dma9___bit 9
553 #define reg_marb_bp_r_brk_first_client___cpui___lsb 10
554 #define reg_marb_bp_r_brk_first_client___cpui___width 1
555 #define reg_marb_bp_r_brk_first_client___cpui___bit 10
556 #define reg_marb_bp_r_brk_first_client___cpud___lsb 11
557 #define reg_marb_bp_r_brk_first_client___cpud___width 1
558 #define reg_marb_bp_r_brk_first_client___cpud___bit 11
559 #define reg_marb_bp_r_brk_first_client___iop___lsb 12
560 #define reg_marb_bp_r_brk_first_client___iop___width 1
561 #define reg_marb_bp_r_brk_first_client___iop___bit 12
562 #define reg_marb_bp_r_brk_first_client___slave___lsb 13
563 #define reg_marb_bp_r_brk_first_client___slave___width 1
564 #define reg_marb_bp_r_brk_first_client___slave___bit 13
565 #define reg_marb_bp_r_brk_first_client_offset 32
566 
567 /* Register r_brk_size, scope marb_bp, type r */
568 #define reg_marb_bp_r_brk_size_offset 36
569 
570 /* Register rw_ack, scope marb_bp, type rw */
571 #define reg_marb_bp_rw_ack_offset 40
572 
573 
574 /* Constants */
575 #define regk_marb_bp_no 0x00000000
576 #define regk_marb_bp_rw_op_default 0x00000000
577 #define regk_marb_bp_rw_options_default 0x00000000
578 #define regk_marb_bp_yes 0x00000001
579 #endif /* __marb_bp_defs_asm_h */