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mcdi_pcol.h
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1 /****************************************************************************
2  * Driver for Solarflare Solarstorm network controllers and boards
3  * Copyright 2009-2011 Solarflare Communications Inc.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License version 2 as published
7  * by the Free Software Foundation, incorporated herein by reference.
8  */
9 
10 
11 #ifndef MCDI_PCOL_H
12 #define MCDI_PCOL_H
13 
14 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */
15 /* Power-on reset state */
16 #define MC_FW_STATE_POR (1)
17 /* If this is set in MC_RESET_STATE_REG then it should be
18  * possible to jump into IMEM without loading code from flash. */
19 #define MC_FW_WARM_BOOT_OK (2)
20 /* The MC main image has started to boot. */
21 #define MC_FW_STATE_BOOTING (4)
22 /* The Scheduler has started. */
23 #define MC_FW_STATE_SCHED (8)
24 
25 /* Siena MC shared memmory offsets */
26 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
27 #define MC_SMEM_P0_DOORBELL_OFST 0x000
28 #define MC_SMEM_P1_DOORBELL_OFST 0x004
29 /* The rest of these are firmware-defined */
30 #define MC_SMEM_P0_PDU_OFST 0x008
31 #define MC_SMEM_P1_PDU_OFST 0x108
32 #define MC_SMEM_PDU_LEN 0x100
33 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
34 #define MC_SMEM_P0_STATUS_OFST 0x7f8
35 #define MC_SMEM_P1_STATUS_OFST 0x7fc
36 
37 /* Values to be written to the per-port status dword in shared
38  * memory on reboot and assert */
39 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
40 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
41 
42 /* The current version of the MCDI protocol.
43  *
44  * Note that the ROM burnt into the card only talks V0, so at the very
45  * least every driver must support version 0 and MCDI_PCOL_VERSION
46  */
47 #define MCDI_PCOL_VERSION 1
48 
49 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */
50 
51 /* MCDI version 1
52  *
53  * Each MCDI request starts with an MCDI_HEADER, which is a 32byte
54  * structure, filled in by the client.
55  *
56  * 0 7 8 16 20 22 23 24 31
57  * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS |
58  * | | |
59  * | | \--- Response
60  * | \------- Error
61  * \------------------------------ Resync (always set)
62  *
63  * The client writes it's request into MC shared memory, and rings the
64  * doorbell. Each request is completed by either by the MC writting
65  * back into shared memory, or by writting out an event.
66  *
67  * All MCDI commands support completion by shared memory response. Each
68  * request may also contain additional data (accounted for by HEADER.LEN),
69  * and some response's may also contain additional data (again, accounted
70  * for by HEADER.LEN).
71  *
72  * Some MCDI commands support completion by event, in which any associated
73  * response data is included in the event.
74  *
75  * The protocol requires one response to be delivered for every request, a
76  * request should not be sent unless the response for the previous request
77  * has been received (either by polling shared memory, or by receiving
78  * an event).
79  */
80 
82 #define MCDI_HEADER_OFST 0
83 #define MCDI_HEADER_CODE_LBN 0
84 #define MCDI_HEADER_CODE_WIDTH 7
85 #define MCDI_HEADER_RESYNC_LBN 7
86 #define MCDI_HEADER_RESYNC_WIDTH 1
87 #define MCDI_HEADER_DATALEN_LBN 8
88 #define MCDI_HEADER_DATALEN_WIDTH 8
89 #define MCDI_HEADER_SEQ_LBN 16
90 #define MCDI_HEADER_RSVD_LBN 20
91 #define MCDI_HEADER_RSVD_WIDTH 2
92 #define MCDI_HEADER_SEQ_WIDTH 4
93 #define MCDI_HEADER_ERROR_LBN 22
94 #define MCDI_HEADER_ERROR_WIDTH 1
95 #define MCDI_HEADER_RESPONSE_LBN 23
96 #define MCDI_HEADER_RESPONSE_WIDTH 1
97 #define MCDI_HEADER_XFLAGS_LBN 24
98 #define MCDI_HEADER_XFLAGS_WIDTH 8
99 /* Request response using event */
100 #define MCDI_HEADER_XFLAGS_EVREQ 0x01
101 
102 /* Maximum number of payload bytes */
103 #define MCDI_CTL_SDU_LEN_MAX 0xfc
104 
105 /* The MC can generate events for two reasons:
106  * - To complete a shared memory request if XFLAGS_EVREQ was set
107  * - As a notification (link state, i2c event), controlled
108  * via MC_CMD_LOG_CTRL
109  *
110  * Both events share a common structure:
111  *
112  * 0 32 33 36 44 52 60
113  * | Data | Cont | Level | Src | Code | Rsvd |
114  * |
115  * \ There is another event pending in this notification
116  *
117  * If Code==CMDDONE, then the fields are further interpreted as:
118  *
119  * - LEVEL==INFO Command succeeded
120  * - LEVEL==ERR Command failed
121  *
122  * 0 8 16 24 32
123  * | Seq | Datalen | Errno | Rsvd |
124  *
125  * These fields are taken directly out of the standard MCDI header, i.e.,
126  * LEVEL==ERR, Datalen == 0 => Reboot
127  *
128  * Events can be squirted out of the UART (using LOG_CTRL) without a
129  * MCDI header. An event can be distinguished from a MCDI response by
130  * examining the first byte which is 0xc0. This corresponds to the
131  * non-existent MCDI command MC_CMD_DEBUG_LOG.
132  *
133  * 0 7 8
134  * | command | Resync | = 0xc0
135  *
136  * Since the event is written in big-endian byte order, this works
137  * providing bits 56-63 of the event are 0xc0.
138  *
139  * 56 60 63
140  * | Rsvd | Code | = 0xc0
141  *
142  * Which means for convenience the event code is 0xc for all MC
143  * generated events.
144  */
145 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
146 
147 
148 /* Non-existent command target */
149 #define MC_CMD_ERR_ENOENT 2
150 /* assert() has killed the MC */
151 #define MC_CMD_ERR_EINTR 4
152 /* Caller does not hold required locks */
153 #define MC_CMD_ERR_EACCES 13
154 /* Resource is currently unavailable (e.g. lock contention) */
155 #define MC_CMD_ERR_EBUSY 16
156 /* Invalid argument to target */
157 #define MC_CMD_ERR_EINVAL 22
158 /* Non-recursive resource is already acquired */
159 #define MC_CMD_ERR_EDEADLK 35
160 /* Operation not implemented */
161 #define MC_CMD_ERR_ENOSYS 38
162 /* Operation timed out */
163 #define MC_CMD_ERR_ETIME 62
164 
165 #define MC_CMD_ERR_CODE_OFST 0
166 
167 /* We define 8 "escape" commands to allow
168  for command number space extension */
169 
170 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78
171 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79
172 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A
173 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B
174 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C
175 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D
176 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E
177 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F
178 
179 /* Vectors in the boot ROM */
180 /* Point to the copycode entry point. */
181 #define MC_BOOTROM_COPYCODE_VEC (0x7f4)
182 /* Points to the recovery mode entry point. */
183 #define MC_BOOTROM_NOFLASH_VEC (0x7f8)
184 
185 /* The command set exported by the boot ROM (MCDI v0) */
186 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \
187  (1 << MC_CMD_READ32) | \
188  (1 << MC_CMD_WRITE32) | \
189  (1 << MC_CMD_COPYCODE) | \
190  (1 << MC_CMD_GET_VERSION), \
191  0, 0, 0 }
192 
193 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \
194  (MC_CMD_SENSOR_ENTRY_OFST + (_x))
195 
196 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \
197  (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
198  MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \
199  (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
200 
201 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \
202  (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
203  MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \
204  (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
205 
206 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \
207  (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
208  MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \
209  (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
210 
211 
212 /* MCDI_EVENT structuredef */
213 #define MCDI_EVENT_LEN 8
214 #define MCDI_EVENT_CONT_LBN 32
215 #define MCDI_EVENT_CONT_WIDTH 1
216 #define MCDI_EVENT_LEVEL_LBN 33
217 #define MCDI_EVENT_LEVEL_WIDTH 3
218 #define MCDI_EVENT_LEVEL_INFO 0x0 /* enum */
219 #define MCDI_EVENT_LEVEL_WARN 0x1 /* enum */
220 #define MCDI_EVENT_LEVEL_ERR 0x2 /* enum */
221 #define MCDI_EVENT_LEVEL_FATAL 0x3 /* enum */
222 #define MCDI_EVENT_DATA_OFST 0
223 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0
224 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8
225 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8
226 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8
227 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16
228 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8
229 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
230 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16
231 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16
232 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
233 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 /* enum */
234 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 /* enum */
235 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 /* enum */
236 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20
237 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
238 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
239 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8
240 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
241 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8
242 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8
243 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8
244 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16
245 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16
246 #define MCDI_EVENT_FWALERT_DATA_LBN 8
247 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24
248 #define MCDI_EVENT_FWALERT_REASON_LBN 0
249 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8
250 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 /* enum */
251 #define MCDI_EVENT_FLR_VF_LBN 0
252 #define MCDI_EVENT_FLR_VF_WIDTH 8
253 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0
254 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12
255 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12
256 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
257 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 /* enum */
258 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 /* enum */
259 #define MCDI_EVENT_TX_ERR_2BIG 0x3 /* enum */
260 #define MCDI_EVENT_TX_ERR_INFO_LBN 16
261 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16
262 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
263 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12
264 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0
265 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8
266 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 /* enum */
267 #define MCDI_EVENT_PTP_ERR_FILTER 0x2 /* enum */
268 #define MCDI_EVENT_PTP_ERR_FIFO 0x3 /* enum */
269 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 /* enum */
270 #define MCDI_EVENT_DATA_LBN 0
271 #define MCDI_EVENT_DATA_WIDTH 32
272 #define MCDI_EVENT_SRC_LBN 36
273 #define MCDI_EVENT_SRC_WIDTH 8
274 #define MCDI_EVENT_EV_CODE_LBN 60
275 #define MCDI_EVENT_EV_CODE_WIDTH 4
276 #define MCDI_EVENT_CODE_LBN 44
277 #define MCDI_EVENT_CODE_WIDTH 8
278 #define MCDI_EVENT_CODE_BADSSERT 0x1 /* enum */
279 #define MCDI_EVENT_CODE_PMNOTICE 0x2 /* enum */
280 #define MCDI_EVENT_CODE_CMDDONE 0x3 /* enum */
281 #define MCDI_EVENT_CODE_LINKCHANGE 0x4 /* enum */
282 #define MCDI_EVENT_CODE_SENSOREVT 0x5 /* enum */
283 #define MCDI_EVENT_CODE_SCHEDERR 0x6 /* enum */
284 #define MCDI_EVENT_CODE_REBOOT 0x7 /* enum */
285 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 /* enum */
286 #define MCDI_EVENT_CODE_FWALERT 0x9 /* enum */
287 #define MCDI_EVENT_CODE_FLR 0xa /* enum */
288 #define MCDI_EVENT_CODE_TX_ERR 0xb /* enum */
289 #define MCDI_EVENT_CODE_TX_FLUSH 0xc /* enum */
290 #define MCDI_EVENT_CODE_PTP_RX 0xd /* enum */
291 #define MCDI_EVENT_CODE_PTP_FAULT 0xe /* enum */
292 #define MCDI_EVENT_CODE_PTP_PPS 0xf /* enum */
293 #define MCDI_EVENT_CMDDONE_DATA_OFST 0
294 #define MCDI_EVENT_CMDDONE_DATA_LBN 0
295 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32
296 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0
297 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0
298 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32
299 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0
300 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0
301 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32
302 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0
303 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0
304 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32
305 #define MCDI_EVENT_TX_ERR_DATA_OFST 0
306 #define MCDI_EVENT_TX_ERR_DATA_LBN 0
307 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32
308 #define MCDI_EVENT_PTP_SECONDS_OFST 0
309 #define MCDI_EVENT_PTP_SECONDS_LBN 0
310 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32
311 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0
312 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0
313 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32
314 #define MCDI_EVENT_PTP_UUID_OFST 0
315 #define MCDI_EVENT_PTP_UUID_LBN 0
316 #define MCDI_EVENT_PTP_UUID_WIDTH 32
317 
318 
319 /***********************************/
320 /* MC_CMD_READ32
321  * Read multiple 32byte words from MC memory.
322  */
323 #define MC_CMD_READ32 0x1
324 
325 /* MC_CMD_READ32_IN msgrequest */
326 #define MC_CMD_READ32_IN_LEN 8
327 #define MC_CMD_READ32_IN_ADDR_OFST 0
328 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4
329 
330 /* MC_CMD_READ32_OUT msgresponse */
331 #define MC_CMD_READ32_OUT_LENMIN 4
332 #define MC_CMD_READ32_OUT_LENMAX 252
333 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
334 #define MC_CMD_READ32_OUT_BUFFER_OFST 0
335 #define MC_CMD_READ32_OUT_BUFFER_LEN 4
336 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1
337 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63
338 
339 
340 /***********************************/
341 /* MC_CMD_WRITE32
342  * Write multiple 32byte words to MC memory.
343  */
344 #define MC_CMD_WRITE32 0x2
345 
346 /* MC_CMD_WRITE32_IN msgrequest */
347 #define MC_CMD_WRITE32_IN_LENMIN 8
348 #define MC_CMD_WRITE32_IN_LENMAX 252
349 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))
350 #define MC_CMD_WRITE32_IN_ADDR_OFST 0
351 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4
352 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4
353 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1
354 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62
355 
356 /* MC_CMD_WRITE32_OUT msgresponse */
357 #define MC_CMD_WRITE32_OUT_LEN 0
358 
359 
360 /***********************************/
361 /* MC_CMD_COPYCODE
362  * Copy MC code between two locations and jump.
363  */
364 #define MC_CMD_COPYCODE 0x3
365 
366 /* MC_CMD_COPYCODE_IN msgrequest */
367 #define MC_CMD_COPYCODE_IN_LEN 16
368 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0
369 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4
370 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8
371 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12
372 #define MC_CMD_COPYCODE_JUMP_NONE 0x1 /* enum */
373 
374 /* MC_CMD_COPYCODE_OUT msgresponse */
375 #define MC_CMD_COPYCODE_OUT_LEN 0
376 
377 
378 /***********************************/
379 /* MC_CMD_SET_FUNC
380  */
381 #define MC_CMD_SET_FUNC 0x4
382 
383 /* MC_CMD_SET_FUNC_IN msgrequest */
384 #define MC_CMD_SET_FUNC_IN_LEN 4
385 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0
386 
387 /* MC_CMD_SET_FUNC_OUT msgresponse */
388 #define MC_CMD_SET_FUNC_OUT_LEN 0
389 
390 
391 /***********************************/
392 /* MC_CMD_GET_BOOT_STATUS
393  */
394 #define MC_CMD_GET_BOOT_STATUS 0x5
395 
396 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */
397 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0
398 
399 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */
400 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8
401 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
402 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
403 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
404 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1
405 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1
406 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1
407 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2
408 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1
409 
410 
411 /***********************************/
412 /* MC_CMD_GET_ASSERTS
413  * Get and clear any assertion status.
414  */
415 #define MC_CMD_GET_ASSERTS 0x6
416 
417 /* MC_CMD_GET_ASSERTS_IN msgrequest */
418 #define MC_CMD_GET_ASSERTS_IN_LEN 4
419 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0
420 
421 /* MC_CMD_GET_ASSERTS_OUT msgresponse */
422 #define MC_CMD_GET_ASSERTS_OUT_LEN 140
423 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0
424 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 /* enum */
425 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 /* enum */
426 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 /* enum */
427 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 /* enum */
428 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4
429 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8
430 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4
431 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31
432 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132
433 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136
434 
435 
436 /***********************************/
437 /* MC_CMD_LOG_CTRL
438  * Configure the output stream for various events and messages.
439  */
440 #define MC_CMD_LOG_CTRL 0x7
441 
442 /* MC_CMD_LOG_CTRL_IN msgrequest */
443 #define MC_CMD_LOG_CTRL_IN_LEN 8
444 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0
445 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 /* enum */
446 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 /* enum */
447 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4
448 
449 /* MC_CMD_LOG_CTRL_OUT msgresponse */
450 #define MC_CMD_LOG_CTRL_OUT_LEN 0
451 
452 
453 /***********************************/
454 /* MC_CMD_GET_VERSION
455  * Get version information about the MC firmware.
456  */
457 #define MC_CMD_GET_VERSION 0x8
458 
459 /* MC_CMD_GET_VERSION_IN msgrequest */
460 #define MC_CMD_GET_VERSION_IN_LEN 0
461 
462 /* MC_CMD_GET_VERSION_V0_OUT msgresponse */
463 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4
464 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0
465 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff /* enum */
466 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_BOOTROM 0xb0070000 /* enum */
467 
468 /* MC_CMD_GET_VERSION_OUT msgresponse */
469 #define MC_CMD_GET_VERSION_OUT_LEN 32
470 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
471 /* Enum values, see field(s): */
472 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
473 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4
474 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8
475 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16
476 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24
477 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8
478 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24
479 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28
480 
481 
482 /***********************************/
483 /* MC_CMD_GET_FPGAREG
484  * Read multiple bytes from PTP FPGA.
485  */
486 #define MC_CMD_GET_FPGAREG 0x9
487 
488 /* MC_CMD_GET_FPGAREG_IN msgrequest */
489 #define MC_CMD_GET_FPGAREG_IN_LEN 8
490 #define MC_CMD_GET_FPGAREG_IN_ADDR_OFST 0
491 #define MC_CMD_GET_FPGAREG_IN_NUMBYTES_OFST 4
492 
493 /* MC_CMD_GET_FPGAREG_OUT msgresponse */
494 #define MC_CMD_GET_FPGAREG_OUT_LENMIN 1
495 #define MC_CMD_GET_FPGAREG_OUT_LENMAX 252
496 #define MC_CMD_GET_FPGAREG_OUT_LEN(num) (0+1*(num))
497 #define MC_CMD_GET_FPGAREG_OUT_BUFFER_OFST 0
498 #define MC_CMD_GET_FPGAREG_OUT_BUFFER_LEN 1
499 #define MC_CMD_GET_FPGAREG_OUT_BUFFER_MINNUM 1
500 #define MC_CMD_GET_FPGAREG_OUT_BUFFER_MAXNUM 252
501 
502 
503 /***********************************/
504 /* MC_CMD_PUT_FPGAREG
505  * Write multiple bytes to PTP FPGA.
506  */
507 #define MC_CMD_PUT_FPGAREG 0xa
508 
509 /* MC_CMD_PUT_FPGAREG_IN msgrequest */
510 #define MC_CMD_PUT_FPGAREG_IN_LENMIN 5
511 #define MC_CMD_PUT_FPGAREG_IN_LENMAX 252
512 #define MC_CMD_PUT_FPGAREG_IN_LEN(num) (4+1*(num))
513 #define MC_CMD_PUT_FPGAREG_IN_ADDR_OFST 0
514 #define MC_CMD_PUT_FPGAREG_IN_BUFFER_OFST 4
515 #define MC_CMD_PUT_FPGAREG_IN_BUFFER_LEN 1
516 #define MC_CMD_PUT_FPGAREG_IN_BUFFER_MINNUM 1
517 #define MC_CMD_PUT_FPGAREG_IN_BUFFER_MAXNUM 248
518 
519 /* MC_CMD_PUT_FPGAREG_OUT msgresponse */
520 #define MC_CMD_PUT_FPGAREG_OUT_LEN 0
521 
522 
523 /***********************************/
524 /* MC_CMD_PTP
525  * Perform PTP operation
526  */
527 #define MC_CMD_PTP 0xb
528 
529 /* MC_CMD_PTP_IN msgrequest */
530 #define MC_CMD_PTP_IN_LEN 1
531 #define MC_CMD_PTP_IN_OP_OFST 0
532 #define MC_CMD_PTP_IN_OP_LEN 1
533 #define MC_CMD_PTP_OP_ENABLE 0x1 /* enum */
534 #define MC_CMD_PTP_OP_DISABLE 0x2 /* enum */
535 #define MC_CMD_PTP_OP_TRANSMIT 0x3 /* enum */
536 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 /* enum */
537 #define MC_CMD_PTP_OP_STATUS 0x5 /* enum */
538 #define MC_CMD_PTP_OP_ADJUST 0x6 /* enum */
539 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 /* enum */
540 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 /* enum */
541 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 /* enum */
542 #define MC_CMD_PTP_OP_RESET_STATS 0xa /* enum */
543 #define MC_CMD_PTP_OP_DEBUG 0xb /* enum */
544 #define MC_CMD_PTP_OP_MAX 0xc /* enum */
545 
546 /* MC_CMD_PTP_IN_ENABLE msgrequest */
547 #define MC_CMD_PTP_IN_ENABLE_LEN 16
548 #define MC_CMD_PTP_IN_CMD_OFST 0
549 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4
550 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8
551 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12
552 #define MC_CMD_PTP_MODE_V1 0x0 /* enum */
553 #define MC_CMD_PTP_MODE_V1_VLAN 0x1 /* enum */
554 #define MC_CMD_PTP_MODE_V2 0x2 /* enum */
555 #define MC_CMD_PTP_MODE_V2_VLAN 0x3 /* enum */
556 
557 /* MC_CMD_PTP_IN_DISABLE msgrequest */
558 #define MC_CMD_PTP_IN_DISABLE_LEN 8
559 /* MC_CMD_PTP_IN_CMD_OFST 0 */
560 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
561 
562 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */
563 #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13
564 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252
565 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))
566 /* MC_CMD_PTP_IN_CMD_OFST 0 */
567 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
568 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8
569 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12
570 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1
571 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1
572 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240
573 
574 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */
575 #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8
576 /* MC_CMD_PTP_IN_CMD_OFST 0 */
577 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
578 
579 /* MC_CMD_PTP_IN_STATUS msgrequest */
580 #define MC_CMD_PTP_IN_STATUS_LEN 8
581 /* MC_CMD_PTP_IN_CMD_OFST 0 */
582 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
583 
584 /* MC_CMD_PTP_IN_ADJUST msgrequest */
585 #define MC_CMD_PTP_IN_ADJUST_LEN 24
586 /* MC_CMD_PTP_IN_CMD_OFST 0 */
587 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
588 #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8
589 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8
590 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8
591 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12
592 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 /* enum */
593 #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16
594 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20
595 
596 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */
597 #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20
598 /* MC_CMD_PTP_IN_CMD_OFST 0 */
599 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
600 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8
601 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12
602 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8
603 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12
604 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16
605 
606 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */
607 #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8
608 /* MC_CMD_PTP_IN_CMD_OFST 0 */
609 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
610 
611 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */
612 #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12
613 /* MC_CMD_PTP_IN_CMD_OFST 0 */
614 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
615 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8
616 
617 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */
618 #define MC_CMD_PTP_IN_RESET_STATS_LEN 8
619 /* MC_CMD_PTP_IN_CMD_OFST 0 */
620 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
621 
622 /* MC_CMD_PTP_IN_DEBUG msgrequest */
623 #define MC_CMD_PTP_IN_DEBUG_LEN 12
624 /* MC_CMD_PTP_IN_CMD_OFST 0 */
625 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
626 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8
627 
628 /* MC_CMD_PTP_OUT msgresponse */
629 #define MC_CMD_PTP_OUT_LEN 0
630 
631 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */
632 #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8
633 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0
634 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4
635 
636 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */
637 #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8
638 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0
639 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4
640 
641 /* MC_CMD_PTP_OUT_STATUS msgresponse */
642 #define MC_CMD_PTP_OUT_STATUS_LEN 64
643 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0
644 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4
645 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8
646 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12
647 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16
648 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20
649 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24
650 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28
651 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32
652 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36
653 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40
654 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44
655 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48
656 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52
657 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56
658 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60
659 
660 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */
661 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20
662 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240
663 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
664 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
665 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20
666 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1
667 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12
668 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0
669 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4
670 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8
671 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12
672 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16
673 
674 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */
675 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8
676 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0
677 #define MC_CMD_PTP_MANF_SUCCESS 0x0 /* enum */
678 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 /* enum */
679 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 /* enum */
680 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 /* enum */
681 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 /* enum */
682 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 /* enum */
683 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 /* enum */
684 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 /* enum */
685 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 /* enum */
686 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 /* enum */
687 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4
688 
689 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */
690 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12
691 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0
692 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4
693 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8
694 
695 
696 /***********************************/
697 /* MC_CMD_CSR_READ32
698  * Read 32bit words from the indirect memory map.
699  */
700 #define MC_CMD_CSR_READ32 0xc
701 
702 /* MC_CMD_CSR_READ32_IN msgrequest */
703 #define MC_CMD_CSR_READ32_IN_LEN 12
704 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0
705 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4
706 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8
707 
708 /* MC_CMD_CSR_READ32_OUT msgresponse */
709 #define MC_CMD_CSR_READ32_OUT_LENMIN 4
710 #define MC_CMD_CSR_READ32_OUT_LENMAX 252
711 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
712 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0
713 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4
714 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1
715 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63
716 
717 
718 /***********************************/
719 /* MC_CMD_CSR_WRITE32
720  * Write 32bit dwords to the indirect memory map.
721  */
722 #define MC_CMD_CSR_WRITE32 0xd
723 
724 /* MC_CMD_CSR_WRITE32_IN msgrequest */
725 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12
726 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252
727 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))
728 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0
729 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4
730 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8
731 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4
732 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1
733 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61
734 
735 /* MC_CMD_CSR_WRITE32_OUT msgresponse */
736 #define MC_CMD_CSR_WRITE32_OUT_LEN 4
737 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0
738 
739 
740 /***********************************/
741 /* MC_CMD_STACKINFO
742  * Get stack information.
743  */
744 #define MC_CMD_STACKINFO 0xf
745 
746 /* MC_CMD_STACKINFO_IN msgrequest */
747 #define MC_CMD_STACKINFO_IN_LEN 0
748 
749 /* MC_CMD_STACKINFO_OUT msgresponse */
750 #define MC_CMD_STACKINFO_OUT_LENMIN 12
751 #define MC_CMD_STACKINFO_OUT_LENMAX 252
752 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))
753 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0
754 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12
755 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1
756 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21
757 
758 
759 /***********************************/
760 /* MC_CMD_MDIO_READ
761  * MDIO register read.
762  */
763 #define MC_CMD_MDIO_READ 0x10
764 
765 /* MC_CMD_MDIO_READ_IN msgrequest */
766 #define MC_CMD_MDIO_READ_IN_LEN 16
767 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0
768 #define MC_CMD_MDIO_BUS_INTERNAL 0x0 /* enum */
769 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 /* enum */
770 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4
771 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8
772 #define MC_CMD_MDIO_CLAUSE22 0x20 /* enum */
773 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12
774 
775 /* MC_CMD_MDIO_READ_OUT msgresponse */
776 #define MC_CMD_MDIO_READ_OUT_LEN 8
777 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0
778 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4
779 #define MC_CMD_MDIO_STATUS_GOOD 0x8 /* enum */
780 
781 
782 /***********************************/
783 /* MC_CMD_MDIO_WRITE
784  * MDIO register write.
785  */
786 #define MC_CMD_MDIO_WRITE 0x11
787 
788 /* MC_CMD_MDIO_WRITE_IN msgrequest */
789 #define MC_CMD_MDIO_WRITE_IN_LEN 20
790 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0
791 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */
792 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */
793 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4
794 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8
795 /* MC_CMD_MDIO_CLAUSE22 0x20 */
796 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12
797 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16
798 
799 /* MC_CMD_MDIO_WRITE_OUT msgresponse */
800 #define MC_CMD_MDIO_WRITE_OUT_LEN 4
801 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0
802 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */
803 
804 
805 /***********************************/
806 /* MC_CMD_DBI_WRITE
807  * Write DBI register(s).
808  */
809 #define MC_CMD_DBI_WRITE 0x12
810 
811 /* MC_CMD_DBI_WRITE_IN msgrequest */
812 #define MC_CMD_DBI_WRITE_IN_LENMIN 12
813 #define MC_CMD_DBI_WRITE_IN_LENMAX 252
814 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))
815 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0
816 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12
817 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1
818 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21
819 
820 /* MC_CMD_DBI_WRITE_OUT msgresponse */
821 #define MC_CMD_DBI_WRITE_OUT_LEN 0
822 
823 /* MC_CMD_DBIWROP_TYPEDEF structuredef */
824 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12
825 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0
826 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0
827 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32
828 #define MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST 4
829 #define MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_LBN 32
830 #define MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_WIDTH 32
831 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8
832 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64
833 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32
834 
835 
836 /***********************************/
837 /* MC_CMD_PORT_READ32
838  * Read a 32-bit register from the indirect port register map.
839  */
840 #define MC_CMD_PORT_READ32 0x14
841 
842 /* MC_CMD_PORT_READ32_IN msgrequest */
843 #define MC_CMD_PORT_READ32_IN_LEN 4
844 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0
845 
846 /* MC_CMD_PORT_READ32_OUT msgresponse */
847 #define MC_CMD_PORT_READ32_OUT_LEN 8
848 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0
849 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4
850 
851 
852 /***********************************/
853 /* MC_CMD_PORT_WRITE32
854  * Write a 32-bit register to the indirect port register map.
855  */
856 #define MC_CMD_PORT_WRITE32 0x15
857 
858 /* MC_CMD_PORT_WRITE32_IN msgrequest */
859 #define MC_CMD_PORT_WRITE32_IN_LEN 8
860 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0
861 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4
862 
863 /* MC_CMD_PORT_WRITE32_OUT msgresponse */
864 #define MC_CMD_PORT_WRITE32_OUT_LEN 4
865 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0
866 
867 
868 /***********************************/
869 /* MC_CMD_PORT_READ128
870  * Read a 128-bit register from the indirect port register map.
871  */
872 #define MC_CMD_PORT_READ128 0x16
873 
874 /* MC_CMD_PORT_READ128_IN msgrequest */
875 #define MC_CMD_PORT_READ128_IN_LEN 4
876 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0
877 
878 /* MC_CMD_PORT_READ128_OUT msgresponse */
879 #define MC_CMD_PORT_READ128_OUT_LEN 20
880 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0
881 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16
882 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16
883 
884 
885 /***********************************/
886 /* MC_CMD_PORT_WRITE128
887  * Write a 128-bit register to the indirect port register map.
888  */
889 #define MC_CMD_PORT_WRITE128 0x17
890 
891 /* MC_CMD_PORT_WRITE128_IN msgrequest */
892 #define MC_CMD_PORT_WRITE128_IN_LEN 20
893 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0
894 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4
895 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16
896 
897 /* MC_CMD_PORT_WRITE128_OUT msgresponse */
898 #define MC_CMD_PORT_WRITE128_OUT_LEN 4
899 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0
900 
901 
902 /***********************************/
903 /* MC_CMD_GET_BOARD_CFG
904  * Returns the MC firmware configuration structure.
905  */
906 #define MC_CMD_GET_BOARD_CFG 0x18
907 
908 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */
909 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0
910 
911 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */
912 #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96
913 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136
914 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num))
915 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
916 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
917 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32
918 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36
919 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0x0 /* enum */
920 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 0x1 /* enum */
921 #define MC_CMD_CAPABILITIES_TURBO_LBN 0x1 /* enum */
922 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 0x1 /* enum */
923 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 0x2 /* enum */
924 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 0x1 /* enum */
925 #define MC_CMD_CAPABILITIES_PTP_LBN 0x3 /* enum */
926 #define MC_CMD_CAPABILITIES_PTP_WIDTH 0x1 /* enum */
927 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40
928 /* Enum values, see field(s): */
929 /* CAPABILITIES_PORT0 */
930 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44
931 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6
932 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50
933 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6
934 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56
935 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60
936 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64
937 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68
938 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72
939 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2
940 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12
941 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32
942 
943 
944 /***********************************/
945 /* MC_CMD_DBI_READX
946  * Read DBI register(s).
947  */
948 #define MC_CMD_DBI_READX 0x19
949 
950 /* MC_CMD_DBI_READX_IN msgrequest */
951 #define MC_CMD_DBI_READX_IN_LENMIN 8
952 #define MC_CMD_DBI_READX_IN_LENMAX 248
953 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))
954 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
955 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8
956 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0
957 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4
958 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1
959 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31
960 
961 /* MC_CMD_DBI_READX_OUT msgresponse */
962 #define MC_CMD_DBI_READX_OUT_LENMIN 4
963 #define MC_CMD_DBI_READX_OUT_LENMAX 252
964 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))
965 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0
966 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4
967 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1
968 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63
969 
970 
971 /***********************************/
972 /* MC_CMD_SET_RAND_SEED
973  * Set the 16byte seed for the MC pseudo-random generator.
974  */
975 #define MC_CMD_SET_RAND_SEED 0x1a
976 
977 /* MC_CMD_SET_RAND_SEED_IN msgrequest */
978 #define MC_CMD_SET_RAND_SEED_IN_LEN 16
979 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0
980 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16
981 
982 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */
983 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0
984 
985 
986 /***********************************/
987 /* MC_CMD_LTSSM_HIST
988  * Retrieve the history of the PCIE LTSSM.
989  */
990 #define MC_CMD_LTSSM_HIST 0x1b
991 
992 /* MC_CMD_LTSSM_HIST_IN msgrequest */
993 #define MC_CMD_LTSSM_HIST_IN_LEN 0
994 
995 /* MC_CMD_LTSSM_HIST_OUT msgresponse */
996 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0
997 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252
998 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))
999 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0
1000 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4
1001 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0
1002 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63
1003 
1004 
1005 /***********************************/
1006 /* MC_CMD_DRV_ATTACH
1007  * Inform MCPU that this port is managed on the host.
1008  */
1009 #define MC_CMD_DRV_ATTACH 0x1c
1010 
1011 /* MC_CMD_DRV_ATTACH_IN msgrequest */
1012 #define MC_CMD_DRV_ATTACH_IN_LEN 8
1013 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
1014 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
1015 
1016 /* MC_CMD_DRV_ATTACH_OUT msgresponse */
1017 #define MC_CMD_DRV_ATTACH_OUT_LEN 4
1018 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0
1019 
1020 
1021 /***********************************/
1022 /* MC_CMD_NCSI_PROD
1023  * Trigger an NC-SI event.
1024  */
1025 #define MC_CMD_NCSI_PROD 0x1d
1026 
1027 /* MC_CMD_NCSI_PROD_IN msgrequest */
1028 #define MC_CMD_NCSI_PROD_IN_LEN 4
1029 #define MC_CMD_NCSI_PROD_IN_EVENTS_OFST 0
1030 #define MC_CMD_NCSI_PROD_LINKCHANGE 0x0 /* enum */
1031 #define MC_CMD_NCSI_PROD_RESET 0x1 /* enum */
1032 #define MC_CMD_NCSI_PROD_DRVATTACH 0x2 /* enum */
1033 #define MC_CMD_NCSI_PROD_IN_LINKCHANGE_LBN 0
1034 #define MC_CMD_NCSI_PROD_IN_LINKCHANGE_WIDTH 1
1035 #define MC_CMD_NCSI_PROD_IN_RESET_LBN 1
1036 #define MC_CMD_NCSI_PROD_IN_RESET_WIDTH 1
1037 #define MC_CMD_NCSI_PROD_IN_DRVATTACH_LBN 2
1038 #define MC_CMD_NCSI_PROD_IN_DRVATTACH_WIDTH 1
1039 
1040 /* MC_CMD_NCSI_PROD_OUT msgresponse */
1041 #define MC_CMD_NCSI_PROD_OUT_LEN 0
1042 
1043 
1044 /***********************************/
1045 /* MC_CMD_SHMUART
1046  * Route UART output to circular buffer in shared memory instead.
1047  */
1048 #define MC_CMD_SHMUART 0x1f
1049 
1050 /* MC_CMD_SHMUART_IN msgrequest */
1051 #define MC_CMD_SHMUART_IN_LEN 4
1052 #define MC_CMD_SHMUART_IN_FLAG_OFST 0
1053 
1054 /* MC_CMD_SHMUART_OUT msgresponse */
1055 #define MC_CMD_SHMUART_OUT_LEN 0
1056 
1057 
1058 /***********************************/
1059 /* MC_CMD_ENTITY_RESET
1060  * Generic per-port reset.
1061  */
1062 #define MC_CMD_ENTITY_RESET 0x20
1063 
1064 /* MC_CMD_ENTITY_RESET_IN msgrequest */
1065 #define MC_CMD_ENTITY_RESET_IN_LEN 4
1066 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0
1067 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0
1068 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1
1069 
1070 /* MC_CMD_ENTITY_RESET_OUT msgresponse */
1071 #define MC_CMD_ENTITY_RESET_OUT_LEN 0
1072 
1073 
1074 /***********************************/
1075 /* MC_CMD_PCIE_CREDITS
1076  * Read instantaneous and minimum flow control thresholds.
1077  */
1078 #define MC_CMD_PCIE_CREDITS 0x21
1079 
1080 /* MC_CMD_PCIE_CREDITS_IN msgrequest */
1081 #define MC_CMD_PCIE_CREDITS_IN_LEN 8
1082 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0
1083 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4
1084 
1085 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */
1086 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16
1087 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0
1088 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2
1089 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2
1090 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2
1091 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4
1092 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2
1093 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6
1094 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2
1095 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8
1096 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2
1097 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10
1098 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2
1099 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12
1100 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2
1101 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14
1102 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2
1103 
1104 
1105 /***********************************/
1106 /* MC_CMD_RXD_MONITOR
1107  * Get histogram of RX queue fill level.
1108  */
1109 #define MC_CMD_RXD_MONITOR 0x22
1110 
1111 /* MC_CMD_RXD_MONITOR_IN msgrequest */
1112 #define MC_CMD_RXD_MONITOR_IN_LEN 12
1113 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0
1114 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4
1115 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8
1116 
1117 /* MC_CMD_RXD_MONITOR_OUT msgresponse */
1118 #define MC_CMD_RXD_MONITOR_OUT_LEN 80
1119 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0
1120 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4
1121 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8
1122 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12
1123 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16
1124 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20
1125 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24
1126 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28
1127 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32
1128 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36
1129 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40
1130 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44
1131 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48
1132 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52
1133 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56
1134 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60
1135 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64
1136 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68
1137 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72
1138 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76
1139 
1140 
1141 /***********************************/
1142 /* MC_CMD_PUTS
1143  * puts(3) implementation over MCDI
1144  */
1145 #define MC_CMD_PUTS 0x23
1146 
1147 /* MC_CMD_PUTS_IN msgrequest */
1148 #define MC_CMD_PUTS_IN_LENMIN 13
1149 #define MC_CMD_PUTS_IN_LENMAX 252
1150 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num))
1151 #define MC_CMD_PUTS_IN_DEST_OFST 0
1152 #define MC_CMD_PUTS_IN_UART_LBN 0
1153 #define MC_CMD_PUTS_IN_UART_WIDTH 1
1154 #define MC_CMD_PUTS_IN_PORT_LBN 1
1155 #define MC_CMD_PUTS_IN_PORT_WIDTH 1
1156 #define MC_CMD_PUTS_IN_DHOST_OFST 4
1157 #define MC_CMD_PUTS_IN_DHOST_LEN 6
1158 #define MC_CMD_PUTS_IN_STRING_OFST 12
1159 #define MC_CMD_PUTS_IN_STRING_LEN 1
1160 #define MC_CMD_PUTS_IN_STRING_MINNUM 1
1161 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240
1162 
1163 /* MC_CMD_PUTS_OUT msgresponse */
1164 #define MC_CMD_PUTS_OUT_LEN 0
1165 
1166 
1167 /***********************************/
1168 /* MC_CMD_GET_PHY_CFG
1169  * Report PHY configuration.
1170  */
1171 #define MC_CMD_GET_PHY_CFG 0x24
1172 
1173 /* MC_CMD_GET_PHY_CFG_IN msgrequest */
1174 #define MC_CMD_GET_PHY_CFG_IN_LEN 0
1175 
1176 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */
1177 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72
1178 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
1179 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0
1180 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1
1181 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1
1182 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1
1183 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2
1184 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1
1185 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3
1186 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1
1187 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4
1188 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1
1189 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5
1190 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1
1191 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6
1192 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1
1193 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4
1194 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8
1195 #define MC_CMD_PHY_CAP_10HDX_LBN 1
1196 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1
1197 #define MC_CMD_PHY_CAP_10FDX_LBN 2
1198 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1
1199 #define MC_CMD_PHY_CAP_100HDX_LBN 3
1200 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1
1201 #define MC_CMD_PHY_CAP_100FDX_LBN 4
1202 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1
1203 #define MC_CMD_PHY_CAP_1000HDX_LBN 5
1204 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1
1205 #define MC_CMD_PHY_CAP_1000FDX_LBN 6
1206 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1
1207 #define MC_CMD_PHY_CAP_10000FDX_LBN 7
1208 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1
1209 #define MC_CMD_PHY_CAP_PAUSE_LBN 8
1210 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1
1211 #define MC_CMD_PHY_CAP_ASYM_LBN 9
1212 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1
1213 #define MC_CMD_PHY_CAP_AN_LBN 10
1214 #define MC_CMD_PHY_CAP_AN_WIDTH 1
1215 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12
1216 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16
1217 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20
1218 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24
1219 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20
1220 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44
1221 #define MC_CMD_MEDIA_XAUI 0x1 /* enum */
1222 #define MC_CMD_MEDIA_CX4 0x2 /* enum */
1223 #define MC_CMD_MEDIA_KX4 0x3 /* enum */
1224 #define MC_CMD_MEDIA_XFP 0x4 /* enum */
1225 #define MC_CMD_MEDIA_SFP_PLUS 0x5 /* enum */
1226 #define MC_CMD_MEDIA_BASE_T 0x6 /* enum */
1227 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48
1228 #define MC_CMD_MMD_CLAUSE22 0x0 /* enum */
1229 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */
1230 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */
1231 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */
1232 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */
1233 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */
1234 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */
1235 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */
1236 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d /* enum */
1237 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */
1238 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */
1239 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52
1240 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20
1241 
1242 
1243 /***********************************/
1244 /* MC_CMD_START_BIST
1245  * Start a BIST test on the PHY.
1246  */
1247 #define MC_CMD_START_BIST 0x25
1248 
1249 /* MC_CMD_START_BIST_IN msgrequest */
1250 #define MC_CMD_START_BIST_IN_LEN 4
1251 #define MC_CMD_START_BIST_IN_TYPE_OFST 0
1252 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 /* enum */
1253 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 /* enum */
1254 #define MC_CMD_BPX_SERDES_BIST 0x3 /* enum */
1255 #define MC_CMD_MC_LOOPBACK_BIST 0x4 /* enum */
1256 #define MC_CMD_PHY_BIST 0x5 /* enum */
1257 
1258 /* MC_CMD_START_BIST_OUT msgresponse */
1259 #define MC_CMD_START_BIST_OUT_LEN 0
1260 
1261 
1262 /***********************************/
1263 /* MC_CMD_POLL_BIST
1264  * Poll for BIST completion.
1265  */
1266 #define MC_CMD_POLL_BIST 0x26
1267 
1268 /* MC_CMD_POLL_BIST_IN msgrequest */
1269 #define MC_CMD_POLL_BIST_IN_LEN 0
1270 
1271 /* MC_CMD_POLL_BIST_OUT msgresponse */
1272 #define MC_CMD_POLL_BIST_OUT_LEN 8
1273 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0
1274 #define MC_CMD_POLL_BIST_RUNNING 0x1 /* enum */
1275 #define MC_CMD_POLL_BIST_PASSED 0x2 /* enum */
1276 #define MC_CMD_POLL_BIST_FAILED 0x3 /* enum */
1277 #define MC_CMD_POLL_BIST_TIMEOUT 0x4 /* enum */
1278 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4
1279 
1280 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */
1281 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36
1282 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
1283 /* Enum values, see field(s): */
1284 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
1285 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4
1286 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8
1287 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12
1288 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16
1289 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20
1290 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 /* enum */
1291 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 /* enum */
1292 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 /* enum */
1293 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 /* enum */
1294 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 /* enum */
1295 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24
1296 /* Enum values, see field(s): */
1297 /* CABLE_STATUS_A */
1298 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28
1299 /* Enum values, see field(s): */
1300 /* CABLE_STATUS_A */
1301 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32
1302 /* Enum values, see field(s): */
1303 /* CABLE_STATUS_A */
1304 
1305 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */
1306 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8
1307 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
1308 /* Enum values, see field(s): */
1309 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
1310 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4
1311 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 /* enum */
1312 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 /* enum */
1313 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 /* enum */
1314 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 /* enum */
1315 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 /* enum */
1316 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 /* enum */
1317 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 /* enum */
1318 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 /* enum */
1319 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 /* enum */
1320 
1321 
1322 /***********************************/
1323 /* MC_CMD_FLUSH_RX_QUEUES
1324  * Flush receive queue(s).
1325  */
1326 #define MC_CMD_FLUSH_RX_QUEUES 0x27
1327 
1328 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */
1329 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4
1330 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252
1331 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))
1332 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0
1333 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4
1334 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1
1335 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63
1336 
1337 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */
1338 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0
1339 
1340 
1341 /***********************************/
1342 /* MC_CMD_GET_LOOPBACK_MODES
1343  * Get port's loopback modes.
1344  */
1345 #define MC_CMD_GET_LOOPBACK_MODES 0x28
1346 
1347 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */
1348 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0
1349 
1350 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */
1351 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 32
1352 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
1353 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8
1354 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
1355 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
1356 #define MC_CMD_LOOPBACK_NONE 0x0 /* enum */
1357 #define MC_CMD_LOOPBACK_DATA 0x1 /* enum */
1358 #define MC_CMD_LOOPBACK_GMAC 0x2 /* enum */
1359 #define MC_CMD_LOOPBACK_XGMII 0x3 /* enum */
1360 #define MC_CMD_LOOPBACK_XGXS 0x4 /* enum */
1361 #define MC_CMD_LOOPBACK_XAUI 0x5 /* enum */
1362 #define MC_CMD_LOOPBACK_GMII 0x6 /* enum */
1363 #define MC_CMD_LOOPBACK_SGMII 0x7 /* enum */
1364 #define MC_CMD_LOOPBACK_XGBR 0x8 /* enum */
1365 #define MC_CMD_LOOPBACK_XFI 0x9 /* enum */
1366 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa /* enum */
1367 #define MC_CMD_LOOPBACK_GMII_FAR 0xb /* enum */
1368 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc /* enum */
1369 #define MC_CMD_LOOPBACK_XFI_FAR 0xd /* enum */
1370 #define MC_CMD_LOOPBACK_GPHY 0xe /* enum */
1371 #define MC_CMD_LOOPBACK_PHYXS 0xf /* enum */
1372 #define MC_CMD_LOOPBACK_PCS 0x10 /* enum */
1373 #define MC_CMD_LOOPBACK_PMAPMD 0x11 /* enum */
1374 #define MC_CMD_LOOPBACK_XPORT 0x12 /* enum */
1375 #define MC_CMD_LOOPBACK_XGMII_WS 0x13 /* enum */
1376 #define MC_CMD_LOOPBACK_XAUI_WS 0x14 /* enum */
1377 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 /* enum */
1378 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 /* enum */
1379 #define MC_CMD_LOOPBACK_GMII_WS 0x17 /* enum */
1380 #define MC_CMD_LOOPBACK_XFI_WS 0x18 /* enum */
1381 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 /* enum */
1382 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a /* enum */
1383 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8
1384 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8
1385 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8
1386 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12
1387 /* Enum values, see field(s): */
1388 /* 100M */
1389 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16
1390 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8
1391 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16
1392 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20
1393 /* Enum values, see field(s): */
1394 /* 100M */
1395 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24
1396 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8
1397 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24
1398 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28
1399 /* Enum values, see field(s): */
1400 /* 100M */
1401 
1402 
1403 /***********************************/
1404 /* MC_CMD_GET_LINK
1405  * Read the unified MAC/PHY link state.
1406  */
1407 #define MC_CMD_GET_LINK 0x29
1408 
1409 /* MC_CMD_GET_LINK_IN msgrequest */
1410 #define MC_CMD_GET_LINK_IN_LEN 0
1411 
1412 /* MC_CMD_GET_LINK_OUT msgresponse */
1413 #define MC_CMD_GET_LINK_OUT_LEN 28
1414 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0
1415 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
1416 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8
1417 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12
1418 /* Enum values, see field(s): */
1419 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
1420 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16
1421 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0
1422 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1
1423 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1
1424 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1
1425 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2
1426 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1
1427 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3
1428 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1
1429 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20
1430 #define MC_CMD_FCNTL_OFF 0x0 /* enum */
1431 #define MC_CMD_FCNTL_RESPOND 0x1 /* enum */
1432 #define MC_CMD_FCNTL_BIDIR 0x2 /* enum */
1433 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24
1434 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
1435 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1
1436 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1
1437 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1
1438 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2
1439 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1
1440 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3
1441 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1
1442 
1443 
1444 /***********************************/
1445 /* MC_CMD_SET_LINK
1446  * Write the unified MAC/PHY link configuration.
1447  */
1448 #define MC_CMD_SET_LINK 0x2a
1449 
1450 /* MC_CMD_SET_LINK_IN msgrequest */
1451 #define MC_CMD_SET_LINK_IN_LEN 16
1452 #define MC_CMD_SET_LINK_IN_CAP_OFST 0
1453 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4
1454 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0
1455 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1
1456 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1
1457 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1
1458 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2
1459 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1
1460 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8
1461 /* Enum values, see field(s): */
1462 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
1463 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12
1464 
1465 /* MC_CMD_SET_LINK_OUT msgresponse */
1466 #define MC_CMD_SET_LINK_OUT_LEN 0
1467 
1468 
1469 /***********************************/
1470 /* MC_CMD_SET_ID_LED
1471  * Set indentification LED state.
1472  */
1473 #define MC_CMD_SET_ID_LED 0x2b
1474 
1475 /* MC_CMD_SET_ID_LED_IN msgrequest */
1476 #define MC_CMD_SET_ID_LED_IN_LEN 4
1477 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0
1478 #define MC_CMD_LED_OFF 0x0 /* enum */
1479 #define MC_CMD_LED_ON 0x1 /* enum */
1480 #define MC_CMD_LED_DEFAULT 0x2 /* enum */
1481 
1482 /* MC_CMD_SET_ID_LED_OUT msgresponse */
1483 #define MC_CMD_SET_ID_LED_OUT_LEN 0
1484 
1485 
1486 /***********************************/
1487 /* MC_CMD_SET_MAC
1488  * Set MAC configuration.
1489  */
1490 #define MC_CMD_SET_MAC 0x2c
1491 
1492 /* MC_CMD_SET_MAC_IN msgrequest */
1493 #define MC_CMD_SET_MAC_IN_LEN 24
1494 #define MC_CMD_SET_MAC_IN_MTU_OFST 0
1495 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4
1496 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8
1497 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8
1498 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8
1499 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12
1500 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16
1501 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
1502 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1
1503 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1
1504 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1
1505 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20
1506 /* MC_CMD_FCNTL_OFF 0x0 */
1507 /* MC_CMD_FCNTL_RESPOND 0x1 */
1508 /* MC_CMD_FCNTL_BIDIR 0x2 */
1509 #define MC_CMD_FCNTL_AUTO 0x3 /* enum */
1510 
1511 /* MC_CMD_SET_MAC_OUT msgresponse */
1512 #define MC_CMD_SET_MAC_OUT_LEN 0
1513 
1514 
1515 /***********************************/
1516 /* MC_CMD_PHY_STATS
1517  * Get generic PHY statistics.
1518  */
1519 #define MC_CMD_PHY_STATS 0x2d
1520 
1521 /* MC_CMD_PHY_STATS_IN msgrequest */
1522 #define MC_CMD_PHY_STATS_IN_LEN 8
1523 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
1524 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8
1525 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
1526 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
1527 
1528 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */
1529 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0
1530 
1531 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */
1532 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3)
1533 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0
1534 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4
1535 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS
1536 #define MC_CMD_OUI 0x0 /* enum */
1537 #define MC_CMD_PMA_PMD_LINK_UP 0x1 /* enum */
1538 #define MC_CMD_PMA_PMD_RX_FAULT 0x2 /* enum */
1539 #define MC_CMD_PMA_PMD_TX_FAULT 0x3 /* enum */
1540 #define MC_CMD_PMA_PMD_SIGNAL 0x4 /* enum */
1541 #define MC_CMD_PMA_PMD_SNR_A 0x5 /* enum */
1542 #define MC_CMD_PMA_PMD_SNR_B 0x6 /* enum */
1543 #define MC_CMD_PMA_PMD_SNR_C 0x7 /* enum */
1544 #define MC_CMD_PMA_PMD_SNR_D 0x8 /* enum */
1545 #define MC_CMD_PCS_LINK_UP 0x9 /* enum */
1546 #define MC_CMD_PCS_RX_FAULT 0xa /* enum */
1547 #define MC_CMD_PCS_TX_FAULT 0xb /* enum */
1548 #define MC_CMD_PCS_BER 0xc /* enum */
1549 #define MC_CMD_PCS_BLOCK_ERRORS 0xd /* enum */
1550 #define MC_CMD_PHYXS_LINK_UP 0xe /* enum */
1551 #define MC_CMD_PHYXS_RX_FAULT 0xf /* enum */
1552 #define MC_CMD_PHYXS_TX_FAULT 0x10 /* enum */
1553 #define MC_CMD_PHYXS_ALIGN 0x11 /* enum */
1554 #define MC_CMD_PHYXS_SYNC 0x12 /* enum */
1555 #define MC_CMD_AN_LINK_UP 0x13 /* enum */
1556 #define MC_CMD_AN_COMPLETE 0x14 /* enum */
1557 #define MC_CMD_AN_10GBT_STATUS 0x15 /* enum */
1558 #define MC_CMD_CL22_LINK_UP 0x16 /* enum */
1559 #define MC_CMD_PHY_NSTATS 0x17 /* enum */
1560 
1561 
1562 /***********************************/
1563 /* MC_CMD_MAC_STATS
1564  * Get generic MAC statistics.
1565  */
1566 #define MC_CMD_MAC_STATS 0x2e
1567 
1568 /* MC_CMD_MAC_STATS_IN msgrequest */
1569 #define MC_CMD_MAC_STATS_IN_LEN 16
1570 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
1571 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8
1572 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
1573 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
1574 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8
1575 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0
1576 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1
1577 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1
1578 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1
1579 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2
1580 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1
1581 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3
1582 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1
1583 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4
1584 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1
1585 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5
1586 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1
1587 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16
1588 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16
1589 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12
1590 
1591 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */
1592 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0
1593 
1594 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */
1595 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)
1596 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
1597 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8
1598 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
1599 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
1600 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
1601 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */
1602 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */
1603 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
1604 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
1605 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
1606 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
1607 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
1608 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */
1609 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
1610 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
1611 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
1612 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
1613 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
1614 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
1615 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
1616 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
1617 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
1618 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
1619 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
1620 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
1621 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
1622 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
1623 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
1624 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
1625 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
1626 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
1627 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
1628 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
1629 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */
1630 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
1631 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
1632 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
1633 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
1634 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
1635 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
1636 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */
1637 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
1638 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
1639 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
1640 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
1641 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
1642 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
1643 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
1644 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
1645 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
1646 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
1647 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
1648 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
1649 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
1650 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
1651 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
1652 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
1653 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
1654 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
1655 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
1656 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
1657 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
1658 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
1659 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
1660 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
1661 #define MC_CMD_GMAC_DMABUF_START 0x40 /* enum */
1662 #define MC_CMD_GMAC_DMABUF_END 0x5f /* enum */
1663 #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */
1664 #define MC_CMD_MAC_NSTATS 0x61 /* enum */
1665 
1666 
1667 /***********************************/
1668 /* MC_CMD_SRIOV
1669  * to be documented
1670  */
1671 #define MC_CMD_SRIOV 0x30
1672 
1673 /* MC_CMD_SRIOV_IN msgrequest */
1674 #define MC_CMD_SRIOV_IN_LEN 12
1675 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0
1676 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4
1677 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8
1678 
1679 /* MC_CMD_SRIOV_OUT msgresponse */
1680 #define MC_CMD_SRIOV_OUT_LEN 8
1681 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0
1682 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4
1683 
1684 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */
1685 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32
1686 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0
1687 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0
1688 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32
1689 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4
1690 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32
1691 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32
1692 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8
1693 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8
1694 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8
1695 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12
1696 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64
1697 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64
1698 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16
1699 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */
1700 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128
1701 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32
1702 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20
1703 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8
1704 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20
1705 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24
1706 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160
1707 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64
1708 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28
1709 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224
1710 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32
1711 
1712 
1713 /***********************************/
1714 /* MC_CMD_MEMCPY
1715  * Perform memory copy operation.
1716  */
1717 #define MC_CMD_MEMCPY 0x31
1718 
1719 /* MC_CMD_MEMCPY_IN msgrequest */
1720 #define MC_CMD_MEMCPY_IN_LENMIN 32
1721 #define MC_CMD_MEMCPY_IN_LENMAX 224
1722 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))
1723 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0
1724 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32
1725 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1
1726 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7
1727 
1728 /* MC_CMD_MEMCPY_OUT msgresponse */
1729 #define MC_CMD_MEMCPY_OUT_LEN 0
1730 
1731 
1732 /***********************************/
1733 /* MC_CMD_WOL_FILTER_SET
1734  * Set a WoL filter.
1735  */
1736 #define MC_CMD_WOL_FILTER_SET 0x32
1737 
1738 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */
1739 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192
1740 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
1741 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
1742 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
1743 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
1744 #define MC_CMD_WOL_TYPE_MAGIC 0x0 /* enum */
1745 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 /* enum */
1746 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 /* enum */
1747 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 /* enum */
1748 #define MC_CMD_WOL_TYPE_BITMAP 0x5 /* enum */
1749 #define MC_CMD_WOL_TYPE_LINK 0x6 /* enum */
1750 #define MC_CMD_WOL_TYPE_MAX 0x7 /* enum */
1751 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8
1752 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4
1753 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46
1754 
1755 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */
1756 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16
1757 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
1758 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
1759 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8
1760 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8
1761 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8
1762 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12
1763 
1764 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */
1765 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20
1766 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
1767 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
1768 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8
1769 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12
1770 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16
1771 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2
1772 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18
1773 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2
1774 
1775 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */
1776 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44
1777 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
1778 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
1779 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8
1780 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16
1781 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24
1782 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16
1783 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40
1784 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2
1785 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42
1786 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2
1787 
1788 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */
1789 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187
1790 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
1791 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
1792 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8
1793 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48
1794 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56
1795 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128
1796 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184
1797 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1
1798 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185
1799 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1
1800 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186
1801 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1
1802 
1803 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */
1804 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12
1805 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
1806 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
1807 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8
1808 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0
1809 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1
1810 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1
1811 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1
1812 
1813 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */
1814 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4
1815 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0
1816 
1817 
1818 /***********************************/
1819 /* MC_CMD_WOL_FILTER_REMOVE
1820  * Remove a WoL filter.
1821  */
1822 #define MC_CMD_WOL_FILTER_REMOVE 0x33
1823 
1824 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */
1825 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4
1826 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0
1827 
1828 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */
1829 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0
1830 
1831 
1832 /***********************************/
1833 /* MC_CMD_WOL_FILTER_RESET
1834  * Reset (i.e. remove all) WoL filters.
1835  */
1836 #define MC_CMD_WOL_FILTER_RESET 0x34
1837 
1838 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */
1839 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4
1840 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0
1841 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */
1842 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */
1843 
1844 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */
1845 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0
1846 
1847 
1848 /***********************************/
1849 /* MC_CMD_SET_MCAST_HASH
1850  * Set the MCASH hash value.
1851  */
1852 #define MC_CMD_SET_MCAST_HASH 0x35
1853 
1854 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */
1855 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32
1856 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0
1857 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16
1858 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16
1859 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16
1860 
1861 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */
1862 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0
1863 
1864 
1865 /***********************************/
1866 /* MC_CMD_NVRAM_TYPES
1867  * Get virtual NVRAM partitions information.
1868  */
1869 #define MC_CMD_NVRAM_TYPES 0x36
1870 
1871 /* MC_CMD_NVRAM_TYPES_IN msgrequest */
1872 #define MC_CMD_NVRAM_TYPES_IN_LEN 0
1873 
1874 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */
1875 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4
1876 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0
1877 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 /* enum */
1878 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 /* enum */
1879 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 /* enum */
1880 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 /* enum */
1881 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 /* enum */
1882 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 /* enum */
1883 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 /* enum */
1884 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 /* enum */
1885 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 /* enum */
1886 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 /* enum */
1887 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa /* enum */
1888 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb /* enum */
1889 #define MC_CMD_NVRAM_TYPE_LOG 0xc /* enum */
1890 #define MC_CMD_NVRAM_TYPE_FPGA 0xd /* enum */
1891 
1892 
1893 /***********************************/
1894 /* MC_CMD_NVRAM_INFO
1895  * Read info about a virtual NVRAM partition.
1896  */
1897 #define MC_CMD_NVRAM_INFO 0x37
1898 
1899 /* MC_CMD_NVRAM_INFO_IN msgrequest */
1900 #define MC_CMD_NVRAM_INFO_IN_LEN 4
1901 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0
1902 /* Enum values, see field(s): */
1903 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
1904 
1905 /* MC_CMD_NVRAM_INFO_OUT msgresponse */
1906 #define MC_CMD_NVRAM_INFO_OUT_LEN 24
1907 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0
1908 /* Enum values, see field(s): */
1909 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
1910 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4
1911 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8
1912 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12
1913 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0
1914 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1
1915 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16
1916 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20
1917 
1918 
1919 /***********************************/
1920 /* MC_CMD_NVRAM_UPDATE_START
1921  * Start a group of update operations on a virtual NVRAM partition.
1922  */
1923 #define MC_CMD_NVRAM_UPDATE_START 0x38
1924 
1925 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */
1926 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4
1927 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0
1928 /* Enum values, see field(s): */
1929 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
1930 
1931 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */
1932 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0
1933 
1934 
1935 /***********************************/
1936 /* MC_CMD_NVRAM_READ
1937  * Read data from a virtual NVRAM partition.
1938  */
1939 #define MC_CMD_NVRAM_READ 0x39
1940 
1941 /* MC_CMD_NVRAM_READ_IN msgrequest */
1942 #define MC_CMD_NVRAM_READ_IN_LEN 12
1943 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0
1944 /* Enum values, see field(s): */
1945 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
1946 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4
1947 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8
1948 
1949 /* MC_CMD_NVRAM_READ_OUT msgresponse */
1950 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1
1951 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252
1952 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
1953 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
1954 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1
1955 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1
1956 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252
1957 
1958 
1959 /***********************************/
1960 /* MC_CMD_NVRAM_WRITE
1961  * Write data to a virtual NVRAM partition.
1962  */
1963 #define MC_CMD_NVRAM_WRITE 0x3a
1964 
1965 /* MC_CMD_NVRAM_WRITE_IN msgrequest */
1966 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13
1967 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252
1968 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))
1969 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
1970 /* Enum values, see field(s): */
1971 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
1972 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4
1973 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8
1974 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12
1975 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1
1976 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1
1977 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240
1978 
1979 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */
1980 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0
1981 
1982 
1983 /***********************************/
1984 /* MC_CMD_NVRAM_ERASE
1985  * Erase sector(s) from a virtual NVRAM partition.
1986  */
1987 #define MC_CMD_NVRAM_ERASE 0x3b
1988 
1989 /* MC_CMD_NVRAM_ERASE_IN msgrequest */
1990 #define MC_CMD_NVRAM_ERASE_IN_LEN 12
1991 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0
1992 /* Enum values, see field(s): */
1993 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
1994 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4
1995 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8
1996 
1997 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */
1998 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0
1999 
2000 
2001 /***********************************/
2002 /* MC_CMD_NVRAM_UPDATE_FINISH
2003  * Finish a group of update operations on a virtual NVRAM partition.
2004  */
2005 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
2006 
2007 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */
2008 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8
2009 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0
2010 /* Enum values, see field(s): */
2011 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
2012 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4
2013 
2014 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */
2015 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0
2016 
2017 
2018 /***********************************/
2019 /* MC_CMD_REBOOT
2020  * Reboot the MC.
2021  */
2022 #define MC_CMD_REBOOT 0x3d
2023 
2024 /* MC_CMD_REBOOT_IN msgrequest */
2025 #define MC_CMD_REBOOT_IN_LEN 4
2026 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0
2027 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */
2028 
2029 /* MC_CMD_REBOOT_OUT msgresponse */
2030 #define MC_CMD_REBOOT_OUT_LEN 0
2031 
2032 
2033 /***********************************/
2034 /* MC_CMD_SCHEDINFO
2035  * Request scheduler info.
2036  */
2037 #define MC_CMD_SCHEDINFO 0x3e
2038 
2039 /* MC_CMD_SCHEDINFO_IN msgrequest */
2040 #define MC_CMD_SCHEDINFO_IN_LEN 0
2041 
2042 /* MC_CMD_SCHEDINFO_OUT msgresponse */
2043 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4
2044 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252
2045 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))
2046 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0
2047 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4
2048 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1
2049 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63
2050 
2051 
2052 /***********************************/
2053 /* MC_CMD_REBOOT_MODE
2054  */
2055 #define MC_CMD_REBOOT_MODE 0x3f
2056 
2057 /* MC_CMD_REBOOT_MODE_IN msgrequest */
2058 #define MC_CMD_REBOOT_MODE_IN_LEN 4
2059 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0
2060 #define MC_CMD_REBOOT_MODE_NORMAL 0x0 /* enum */
2061 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 /* enum */
2062 
2063 /* MC_CMD_REBOOT_MODE_OUT msgresponse */
2064 #define MC_CMD_REBOOT_MODE_OUT_LEN 4
2065 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0
2066 
2067 
2068 /***********************************/
2069 /* MC_CMD_SENSOR_INFO
2070  * Returns information about every available sensor.
2071  */
2072 #define MC_CMD_SENSOR_INFO 0x41
2073 
2074 /* MC_CMD_SENSOR_INFO_IN msgrequest */
2075 #define MC_CMD_SENSOR_INFO_IN_LEN 0
2076 
2077 /* MC_CMD_SENSOR_INFO_OUT msgresponse */
2078 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 12
2079 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252
2080 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))
2081 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
2082 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 /* enum */
2083 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 /* enum */
2084 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 /* enum */
2085 #define MC_CMD_SENSOR_PHY0_TEMP 0x3 /* enum */
2086 #define MC_CMD_SENSOR_PHY0_COOLING 0x4 /* enum */
2087 #define MC_CMD_SENSOR_PHY1_TEMP 0x5 /* enum */
2088 #define MC_CMD_SENSOR_PHY1_COOLING 0x6 /* enum */
2089 #define MC_CMD_SENSOR_IN_1V0 0x7 /* enum */
2090 #define MC_CMD_SENSOR_IN_1V2 0x8 /* enum */
2091 #define MC_CMD_SENSOR_IN_1V8 0x9 /* enum */
2092 #define MC_CMD_SENSOR_IN_2V5 0xa /* enum */
2093 #define MC_CMD_SENSOR_IN_3V3 0xb /* enum */
2094 #define MC_CMD_SENSOR_IN_12V0 0xc /* enum */
2095 #define MC_CMD_SENSOR_IN_1V2A 0xd /* enum */
2096 #define MC_CMD_SENSOR_IN_VREF 0xe /* enum */
2097 #define MC_CMD_SENSOR_ENTRY_OFST 4
2098 #define MC_CMD_SENSOR_ENTRY_LEN 8
2099 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4
2100 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8
2101 #define MC_CMD_SENSOR_ENTRY_MINNUM 1
2102 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31
2103 
2104 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */
2105 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8
2106 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0
2107 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2
2108 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0
2109 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16
2110 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2
2111 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2
2112 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16
2113 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16
2114 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4
2115 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2
2116 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32
2117 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16
2118 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6
2119 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2
2120 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48
2121 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16
2122 
2123 
2124 /***********************************/
2125 /* MC_CMD_READ_SENSORS
2126  * Returns the current reading from each sensor.
2127  */
2128 #define MC_CMD_READ_SENSORS 0x42
2129 
2130 /* MC_CMD_READ_SENSORS_IN msgrequest */
2131 #define MC_CMD_READ_SENSORS_IN_LEN 8
2132 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
2133 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8
2134 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
2135 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
2136 
2137 /* MC_CMD_READ_SENSORS_OUT msgresponse */
2138 #define MC_CMD_READ_SENSORS_OUT_LEN 0
2139 
2140 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */
2141 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 3
2142 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0
2143 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2
2144 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0
2145 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16
2146 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2
2147 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1
2148 #define MC_CMD_SENSOR_STATE_OK 0x0 /* enum */
2149 #define MC_CMD_SENSOR_STATE_WARNING 0x1 /* enum */
2150 #define MC_CMD_SENSOR_STATE_FATAL 0x2 /* enum */
2151 #define MC_CMD_SENSOR_STATE_BROKEN 0x3 /* enum */
2152 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16
2153 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8
2154 
2155 
2156 /***********************************/
2157 /* MC_CMD_GET_PHY_STATE
2158  * Report current state of PHY.
2159  */
2160 #define MC_CMD_GET_PHY_STATE 0x43
2161 
2162 /* MC_CMD_GET_PHY_STATE_IN msgrequest */
2163 #define MC_CMD_GET_PHY_STATE_IN_LEN 0
2164 
2165 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */
2166 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4
2167 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0
2168 #define MC_CMD_PHY_STATE_OK 0x1 /* enum */
2169 #define MC_CMD_PHY_STATE_ZOMBIE 0x2 /* enum */
2170 
2171 
2172 /***********************************/
2173 /* MC_CMD_SETUP_8021QBB
2174  * 802.1Qbb control.
2175  */
2176 #define MC_CMD_SETUP_8021QBB 0x44
2177 
2178 /* MC_CMD_SETUP_8021QBB_IN msgrequest */
2179 #define MC_CMD_SETUP_8021QBB_IN_LEN 32
2180 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0
2181 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32
2182 
2183 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */
2184 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0
2185 
2186 
2187 /***********************************/
2188 /* MC_CMD_WOL_FILTER_GET
2189  * Retrieve ID of any WoL filters.
2190  */
2191 #define MC_CMD_WOL_FILTER_GET 0x45
2192 
2193 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */
2194 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0
2195 
2196 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */
2197 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4
2198 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0
2199 
2200 
2201 /***********************************/
2202 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD
2203  * Add a protocol offload to NIC for lights-out state.
2204  */
2205 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46
2206 
2207 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */
2208 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8
2209 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252
2210 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))
2211 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
2212 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */
2213 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */
2214 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4
2215 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4
2216 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1
2217 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62
2218 
2219 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */
2220 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14
2221 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
2222 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4
2223 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6
2224 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10
2225 
2226 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */
2227 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42
2228 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
2229 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4
2230 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6
2231 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10
2232 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16
2233 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26
2234 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16
2235 
2236 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */
2237 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4
2238 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0
2239 
2240 
2241 /***********************************/
2242 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD
2243  * Remove a protocol offload from NIC for lights-out state.
2244  */
2245 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47
2246 
2247 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */
2248 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8
2249 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
2250 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4
2251 
2252 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */
2253 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0
2254 
2255 
2256 /***********************************/
2257 /* MC_CMD_MAC_RESET_RESTORE
2258  * Restore MAC after block reset.
2259  */
2260 #define MC_CMD_MAC_RESET_RESTORE 0x48
2261 
2262 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */
2263 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0
2264 
2265 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */
2266 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0
2267 
2268 
2269 /***********************************/
2270 /* MC_CMD_TESTASSERT
2271  */
2272 #define MC_CMD_TESTASSERT 0x49
2273 
2274 /* MC_CMD_TESTASSERT_IN msgrequest */
2275 #define MC_CMD_TESTASSERT_IN_LEN 0
2276 
2277 /* MC_CMD_TESTASSERT_OUT msgresponse */
2278 #define MC_CMD_TESTASSERT_OUT_LEN 0
2279 
2280 
2281 /***********************************/
2282 /* MC_CMD_WORKAROUND
2283  * Enable/Disable a given workaround.
2284  */
2285 #define MC_CMD_WORKAROUND 0x4a
2286 
2287 /* MC_CMD_WORKAROUND_IN msgrequest */
2288 #define MC_CMD_WORKAROUND_IN_LEN 8
2289 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0
2290 #define MC_CMD_WORKAROUND_BUG17230 0x1 /* enum */
2291 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4
2292 
2293 /* MC_CMD_WORKAROUND_OUT msgresponse */
2294 #define MC_CMD_WORKAROUND_OUT_LEN 0
2295 
2296 
2297 /***********************************/
2298 /* MC_CMD_GET_PHY_MEDIA_INFO
2299  * Read media-specific data from PHY.
2300  */
2301 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
2302 
2303 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */
2304 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4
2305 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0
2306 
2307 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */
2308 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5
2309 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252
2310 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))
2311 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
2312 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4
2313 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1
2314 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1
2315 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248
2316 
2317 
2318 /***********************************/
2319 /* MC_CMD_NVRAM_TEST
2320  * Test a particular NVRAM partition.
2321  */
2322 #define MC_CMD_NVRAM_TEST 0x4c
2323 
2324 /* MC_CMD_NVRAM_TEST_IN msgrequest */
2325 #define MC_CMD_NVRAM_TEST_IN_LEN 4
2326 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0
2327 /* Enum values, see field(s): */
2328 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
2329 
2330 /* MC_CMD_NVRAM_TEST_OUT msgresponse */
2331 #define MC_CMD_NVRAM_TEST_OUT_LEN 4
2332 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0
2333 #define MC_CMD_NVRAM_TEST_PASS 0x0 /* enum */
2334 #define MC_CMD_NVRAM_TEST_FAIL 0x1 /* enum */
2335 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 /* enum */
2336 
2337 
2338 /***********************************/
2339 /* MC_CMD_MRSFP_TWEAK
2340  * Read status and/or set parameters for the 'mrsfp' driver.
2341  */
2342 #define MC_CMD_MRSFP_TWEAK 0x4d
2343 
2344 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */
2345 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16
2346 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0
2347 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4
2348 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8
2349 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12
2350 
2351 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */
2352 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0
2353 
2354 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */
2355 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12
2356 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0
2357 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4
2358 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8
2359 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 /* enum */
2360 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 /* enum */
2361 
2362 
2363 /***********************************/
2364 /* MC_CMD_SENSOR_SET_LIMS
2365  * Adjusts the sensor limits.
2366  */
2367 #define MC_CMD_SENSOR_SET_LIMS 0x4e
2368 
2369 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */
2370 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20
2371 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0
2372 /* Enum values, see field(s): */
2373 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
2374 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4
2375 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8
2376 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12
2377 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16
2378 
2379 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */
2380 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0
2381 
2382 
2383 /***********************************/
2384 /* MC_CMD_GET_RESOURCE_LIMITS
2385  */
2386 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f
2387 
2388 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */
2389 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0
2390 
2391 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */
2392 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16
2393 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0
2394 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4
2395 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8
2396 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12
2397 
2398 /* MC_CMD_RESOURCE_SPECIFIER enum */
2399 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff /* enum */
2400 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe /* enum */
2401 
2402 
2403 #endif /* MCDI_PCOL_H */