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mmc_core.c
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1 /*******************************************************************************
2  DWMAC Management Counters
3 
4  Copyright (C) 2011 STMicroelectronics Ltd
5 
6  This program is free software; you can redistribute it and/or modify it
7  under the terms and conditions of the GNU General Public License,
8  version 2, as published by the Free Software Foundation.
9 
10  This program is distributed in the hope it will be useful, but WITHOUT
11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13  more details.
14 
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, write to the Free Software Foundation, Inc.,
17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19  The full GNU General Public License is included in this distribution in
20  the file called "COPYING".
21 
22  Author: Giuseppe Cavallaro <[email protected]>
23 *******************************************************************************/
24 
25 #include <linux/kernel.h>
26 #include <linux/io.h>
27 #include "mmc.h"
28 
29 /* MAC Management Counters register offset */
30 
31 #define MMC_CNTRL 0x00000100 /* MMC Control */
32 #define MMC_RX_INTR 0x00000104 /* MMC RX Interrupt */
33 #define MMC_TX_INTR 0x00000108 /* MMC TX Interrupt */
34 #define MMC_RX_INTR_MASK 0x0000010c /* MMC Interrupt Mask */
35 #define MMC_TX_INTR_MASK 0x00000110 /* MMC Interrupt Mask */
36 #define MMC_DEFAULT_MASK 0xffffffff
37 
38 /* MMC TX counter registers */
39 
40 /* Note:
41  * _GB register stands for good and bad frames
42  * _G is for good only.
43  */
44 #define MMC_TX_OCTETCOUNT_GB 0x00000114
45 #define MMC_TX_FRAMECOUNT_GB 0x00000118
46 #define MMC_TX_BROADCASTFRAME_G 0x0000011c
47 #define MMC_TX_MULTICASTFRAME_G 0x00000120
48 #define MMC_TX_64_OCTETS_GB 0x00000124
49 #define MMC_TX_65_TO_127_OCTETS_GB 0x00000128
50 #define MMC_TX_128_TO_255_OCTETS_GB 0x0000012c
51 #define MMC_TX_256_TO_511_OCTETS_GB 0x00000130
52 #define MMC_TX_512_TO_1023_OCTETS_GB 0x00000134
53 #define MMC_TX_1024_TO_MAX_OCTETS_GB 0x00000138
54 #define MMC_TX_UNICAST_GB 0x0000013c
55 #define MMC_TX_MULTICAST_GB 0x00000140
56 #define MMC_TX_BROADCAST_GB 0x00000144
57 #define MMC_TX_UNDERFLOW_ERROR 0x00000148
58 #define MMC_TX_SINGLECOL_G 0x0000014c
59 #define MMC_TX_MULTICOL_G 0x00000150
60 #define MMC_TX_DEFERRED 0x00000154
61 #define MMC_TX_LATECOL 0x00000158
62 #define MMC_TX_EXESSCOL 0x0000015c
63 #define MMC_TX_CARRIER_ERROR 0x00000160
64 #define MMC_TX_OCTETCOUNT_G 0x00000164
65 #define MMC_TX_FRAMECOUNT_G 0x00000168
66 #define MMC_TX_EXCESSDEF 0x0000016c
67 #define MMC_TX_PAUSE_FRAME 0x00000170
68 #define MMC_TX_VLAN_FRAME_G 0x00000174
69 
70 /* MMC RX counter registers */
71 #define MMC_RX_FRAMECOUNT_GB 0x00000180
72 #define MMC_RX_OCTETCOUNT_GB 0x00000184
73 #define MMC_RX_OCTETCOUNT_G 0x00000188
74 #define MMC_RX_BROADCASTFRAME_G 0x0000018c
75 #define MMC_RX_MULTICASTFRAME_G 0x00000190
76 #define MMC_RX_CRC_ERRROR 0x00000194
77 #define MMC_RX_ALIGN_ERROR 0x00000198
78 #define MMC_RX_RUN_ERROR 0x0000019C
79 #define MMC_RX_JABBER_ERROR 0x000001A0
80 #define MMC_RX_UNDERSIZE_G 0x000001A4
81 #define MMC_RX_OVERSIZE_G 0x000001A8
82 #define MMC_RX_64_OCTETS_GB 0x000001AC
83 #define MMC_RX_65_TO_127_OCTETS_GB 0x000001b0
84 #define MMC_RX_128_TO_255_OCTETS_GB 0x000001b4
85 #define MMC_RX_256_TO_511_OCTETS_GB 0x000001b8
86 #define MMC_RX_512_TO_1023_OCTETS_GB 0x000001bc
87 #define MMC_RX_1024_TO_MAX_OCTETS_GB 0x000001c0
88 #define MMC_RX_UNICAST_G 0x000001c4
89 #define MMC_RX_LENGTH_ERROR 0x000001c8
90 #define MMC_RX_AUTOFRANGETYPE 0x000001cc
91 #define MMC_RX_PAUSE_FRAMES 0x000001d0
92 #define MMC_RX_FIFO_OVERFLOW 0x000001d4
93 #define MMC_RX_VLAN_FRAMES_GB 0x000001d8
94 #define MMC_RX_WATCHDOG_ERROR 0x000001dc
95 /* IPC*/
96 #define MMC_RX_IPC_INTR_MASK 0x00000200
97 #define MMC_RX_IPC_INTR 0x00000208
98 /* IPv4*/
99 #define MMC_RX_IPV4_GD 0x00000210
100 #define MMC_RX_IPV4_HDERR 0x00000214
101 #define MMC_RX_IPV4_NOPAY 0x00000218
102 #define MMC_RX_IPV4_FRAG 0x0000021C
103 #define MMC_RX_IPV4_UDSBL 0x00000220
104 
105 #define MMC_RX_IPV4_GD_OCTETS 0x00000250
106 #define MMC_RX_IPV4_HDERR_OCTETS 0x00000254
107 #define MMC_RX_IPV4_NOPAY_OCTETS 0x00000258
108 #define MMC_RX_IPV4_FRAG_OCTETS 0x0000025c
109 #define MMC_RX_IPV4_UDSBL_OCTETS 0x00000260
110 
111 /* IPV6*/
112 #define MMC_RX_IPV6_GD_OCTETS 0x00000264
113 #define MMC_RX_IPV6_HDERR_OCTETS 0x00000268
114 #define MMC_RX_IPV6_NOPAY_OCTETS 0x0000026c
115 
116 #define MMC_RX_IPV6_GD 0x00000224
117 #define MMC_RX_IPV6_HDERR 0x00000228
118 #define MMC_RX_IPV6_NOPAY 0x0000022c
119 
120 /* Protocols*/
121 #define MMC_RX_UDP_GD 0x00000230
122 #define MMC_RX_UDP_ERR 0x00000234
123 #define MMC_RX_TCP_GD 0x00000238
124 #define MMC_RX_TCP_ERR 0x0000023c
125 #define MMC_RX_ICMP_GD 0x00000240
126 #define MMC_RX_ICMP_ERR 0x00000244
127 
128 #define MMC_RX_UDP_GD_OCTETS 0x00000270
129 #define MMC_RX_UDP_ERR_OCTETS 0x00000274
130 #define MMC_RX_TCP_GD_OCTETS 0x00000278
131 #define MMC_RX_TCP_ERR_OCTETS 0x0000027c
132 #define MMC_RX_ICMP_GD_OCTETS 0x00000280
133 #define MMC_RX_ICMP_ERR_OCTETS 0x00000284
134 
135 void dwmac_mmc_ctrl(void __iomem *ioaddr, unsigned int mode)
136 {
137  u32 value = readl(ioaddr + MMC_CNTRL);
138 
139  value |= (mode & 0x3F);
140 
141  writel(value, ioaddr + MMC_CNTRL);
142 
143  pr_debug("stmmac: MMC ctrl register (offset 0x%x): 0x%08x\n",
144  MMC_CNTRL, value);
145 }
146 
147 /* To mask all all interrupts.*/
148 void dwmac_mmc_intr_all_mask(void __iomem *ioaddr)
149 {
150  writel(MMC_DEFAULT_MASK, ioaddr + MMC_RX_INTR_MASK);
151  writel(MMC_DEFAULT_MASK, ioaddr + MMC_TX_INTR_MASK);
152 }
153 
154 /* This reads the MAC core counters (if actaully supported).
155  * by default the MMC core is programmed to reset each
156  * counter after a read. So all the field of the mmc struct
157  * have to be incremented.
158  */
159 void dwmac_mmc_read(void __iomem *ioaddr, struct stmmac_counters *mmc)
160 {
161  mmc->mmc_tx_octetcount_gb += readl(ioaddr + MMC_TX_OCTETCOUNT_GB);
162  mmc->mmc_tx_framecount_gb += readl(ioaddr + MMC_TX_FRAMECOUNT_GB);
163  mmc->mmc_tx_broadcastframe_g += readl(ioaddr + MMC_TX_BROADCASTFRAME_G);
164  mmc->mmc_tx_multicastframe_g += readl(ioaddr + MMC_TX_MULTICASTFRAME_G);
165  mmc->mmc_tx_64_octets_gb += readl(ioaddr + MMC_TX_64_OCTETS_GB);
166  mmc->mmc_tx_65_to_127_octets_gb +=
167  readl(ioaddr + MMC_TX_65_TO_127_OCTETS_GB);
168  mmc->mmc_tx_128_to_255_octets_gb +=
169  readl(ioaddr + MMC_TX_128_TO_255_OCTETS_GB);
170  mmc->mmc_tx_256_to_511_octets_gb +=
171  readl(ioaddr + MMC_TX_256_TO_511_OCTETS_GB);
172  mmc->mmc_tx_512_to_1023_octets_gb +=
173  readl(ioaddr + MMC_TX_512_TO_1023_OCTETS_GB);
174  mmc->mmc_tx_1024_to_max_octets_gb +=
175  readl(ioaddr + MMC_TX_1024_TO_MAX_OCTETS_GB);
176  mmc->mmc_tx_unicast_gb += readl(ioaddr + MMC_TX_UNICAST_GB);
177  mmc->mmc_tx_multicast_gb += readl(ioaddr + MMC_TX_MULTICAST_GB);
178  mmc->mmc_tx_broadcast_gb += readl(ioaddr + MMC_TX_BROADCAST_GB);
179  mmc->mmc_tx_underflow_error += readl(ioaddr + MMC_TX_UNDERFLOW_ERROR);
180  mmc->mmc_tx_singlecol_g += readl(ioaddr + MMC_TX_SINGLECOL_G);
181  mmc->mmc_tx_multicol_g += readl(ioaddr + MMC_TX_MULTICOL_G);
182  mmc->mmc_tx_deferred += readl(ioaddr + MMC_TX_DEFERRED);
183  mmc->mmc_tx_latecol += readl(ioaddr + MMC_TX_LATECOL);
184  mmc->mmc_tx_exesscol += readl(ioaddr + MMC_TX_EXESSCOL);
185  mmc->mmc_tx_carrier_error += readl(ioaddr + MMC_TX_CARRIER_ERROR);
186  mmc->mmc_tx_octetcount_g += readl(ioaddr + MMC_TX_OCTETCOUNT_G);
187  mmc->mmc_tx_framecount_g += readl(ioaddr + MMC_TX_FRAMECOUNT_G);
188  mmc->mmc_tx_excessdef += readl(ioaddr + MMC_TX_EXCESSDEF);
189  mmc->mmc_tx_pause_frame += readl(ioaddr + MMC_TX_PAUSE_FRAME);
190  mmc->mmc_tx_vlan_frame_g += readl(ioaddr + MMC_TX_VLAN_FRAME_G);
191 
192  /* MMC RX counter registers */
193  mmc->mmc_rx_framecount_gb += readl(ioaddr + MMC_RX_FRAMECOUNT_GB);
194  mmc->mmc_rx_octetcount_gb += readl(ioaddr + MMC_RX_OCTETCOUNT_GB);
195  mmc->mmc_rx_octetcount_g += readl(ioaddr + MMC_RX_OCTETCOUNT_G);
196  mmc->mmc_rx_broadcastframe_g += readl(ioaddr + MMC_RX_BROADCASTFRAME_G);
197  mmc->mmc_rx_multicastframe_g += readl(ioaddr + MMC_RX_MULTICASTFRAME_G);
198  mmc->mmc_rx_crc_errror += readl(ioaddr + MMC_RX_CRC_ERRROR);
199  mmc->mmc_rx_align_error += readl(ioaddr + MMC_RX_ALIGN_ERROR);
200  mmc->mmc_rx_run_error += readl(ioaddr + MMC_RX_RUN_ERROR);
201  mmc->mmc_rx_jabber_error += readl(ioaddr + MMC_RX_JABBER_ERROR);
202  mmc->mmc_rx_undersize_g += readl(ioaddr + MMC_RX_UNDERSIZE_G);
203  mmc->mmc_rx_oversize_g += readl(ioaddr + MMC_RX_OVERSIZE_G);
204  mmc->mmc_rx_64_octets_gb += readl(ioaddr + MMC_RX_64_OCTETS_GB);
205  mmc->mmc_rx_65_to_127_octets_gb +=
206  readl(ioaddr + MMC_RX_65_TO_127_OCTETS_GB);
207  mmc->mmc_rx_128_to_255_octets_gb +=
208  readl(ioaddr + MMC_RX_128_TO_255_OCTETS_GB);
209  mmc->mmc_rx_256_to_511_octets_gb +=
210  readl(ioaddr + MMC_RX_256_TO_511_OCTETS_GB);
211  mmc->mmc_rx_512_to_1023_octets_gb +=
212  readl(ioaddr + MMC_RX_512_TO_1023_OCTETS_GB);
213  mmc->mmc_rx_1024_to_max_octets_gb +=
214  readl(ioaddr + MMC_RX_1024_TO_MAX_OCTETS_GB);
215  mmc->mmc_rx_unicast_g += readl(ioaddr + MMC_RX_UNICAST_G);
216  mmc->mmc_rx_length_error += readl(ioaddr + MMC_RX_LENGTH_ERROR);
217  mmc->mmc_rx_autofrangetype += readl(ioaddr + MMC_RX_AUTOFRANGETYPE);
218  mmc->mmc_rx_pause_frames += readl(ioaddr + MMC_RX_PAUSE_FRAMES);
219  mmc->mmc_rx_fifo_overflow += readl(ioaddr + MMC_RX_FIFO_OVERFLOW);
220  mmc->mmc_rx_vlan_frames_gb += readl(ioaddr + MMC_RX_VLAN_FRAMES_GB);
221  mmc->mmc_rx_watchdog_error += readl(ioaddr + MMC_RX_WATCHDOG_ERROR);
222  /* IPC */
223  mmc->mmc_rx_ipc_intr_mask += readl(ioaddr + MMC_RX_IPC_INTR_MASK);
224  mmc->mmc_rx_ipc_intr += readl(ioaddr + MMC_RX_IPC_INTR);
225  /* IPv4 */
226  mmc->mmc_rx_ipv4_gd += readl(ioaddr + MMC_RX_IPV4_GD);
227  mmc->mmc_rx_ipv4_hderr += readl(ioaddr + MMC_RX_IPV4_HDERR);
228  mmc->mmc_rx_ipv4_nopay += readl(ioaddr + MMC_RX_IPV4_NOPAY);
229  mmc->mmc_rx_ipv4_frag += readl(ioaddr + MMC_RX_IPV4_FRAG);
230  mmc->mmc_rx_ipv4_udsbl += readl(ioaddr + MMC_RX_IPV4_UDSBL);
231 
232  mmc->mmc_rx_ipv4_gd_octets += readl(ioaddr + MMC_RX_IPV4_GD_OCTETS);
233  mmc->mmc_rx_ipv4_hderr_octets +=
234  readl(ioaddr + MMC_RX_IPV4_HDERR_OCTETS);
235  mmc->mmc_rx_ipv4_nopay_octets +=
236  readl(ioaddr + MMC_RX_IPV4_NOPAY_OCTETS);
237  mmc->mmc_rx_ipv4_frag_octets += readl(ioaddr + MMC_RX_IPV4_FRAG_OCTETS);
238  mmc->mmc_rx_ipv4_udsbl_octets +=
239  readl(ioaddr + MMC_RX_IPV4_UDSBL_OCTETS);
240 
241  /* IPV6 */
242  mmc->mmc_rx_ipv6_gd_octets += readl(ioaddr + MMC_RX_IPV6_GD_OCTETS);
243  mmc->mmc_rx_ipv6_hderr_octets +=
244  readl(ioaddr + MMC_RX_IPV6_HDERR_OCTETS);
245  mmc->mmc_rx_ipv6_nopay_octets +=
246  readl(ioaddr + MMC_RX_IPV6_NOPAY_OCTETS);
247 
248  mmc->mmc_rx_ipv6_gd += readl(ioaddr + MMC_RX_IPV6_GD);
249  mmc->mmc_rx_ipv6_hderr += readl(ioaddr + MMC_RX_IPV6_HDERR);
250  mmc->mmc_rx_ipv6_nopay += readl(ioaddr + MMC_RX_IPV6_NOPAY);
251 
252  /* Protocols */
253  mmc->mmc_rx_udp_gd += readl(ioaddr + MMC_RX_UDP_GD);
254  mmc->mmc_rx_udp_err += readl(ioaddr + MMC_RX_UDP_ERR);
255  mmc->mmc_rx_tcp_gd += readl(ioaddr + MMC_RX_TCP_GD);
256  mmc->mmc_rx_tcp_err += readl(ioaddr + MMC_RX_TCP_ERR);
257  mmc->mmc_rx_icmp_gd += readl(ioaddr + MMC_RX_ICMP_GD);
258  mmc->mmc_rx_icmp_err += readl(ioaddr + MMC_RX_ICMP_ERR);
259 
260  mmc->mmc_rx_udp_gd_octets += readl(ioaddr + MMC_RX_UDP_GD_OCTETS);
261  mmc->mmc_rx_udp_err_octets += readl(ioaddr + MMC_RX_UDP_ERR_OCTETS);
262  mmc->mmc_rx_tcp_gd_octets += readl(ioaddr + MMC_RX_TCP_GD_OCTETS);
263  mmc->mmc_rx_tcp_err_octets += readl(ioaddr + MMC_RX_TCP_ERR_OCTETS);
264  mmc->mmc_rx_icmp_gd_octets += readl(ioaddr + MMC_RX_ICMP_GD_OCTETS);
265  mmc->mmc_rx_icmp_err_octets += readl(ioaddr + MMC_RX_ICMP_ERR_OCTETS);
266 }
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