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mpi_cnfg.h
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1 /*
2  * Copyright (c) 2000-2008 LSI Corporation.
3  *
4  *
5  * Name: mpi_cnfg.h
6  * Title: MPI Config message, structures, and Pages
7  * Creation Date: July 27, 2000
8  *
9  * mpi_cnfg.h Version: 01.05.18
10  *
11  * Version History
12  * ---------------
13  *
14  * Date Version Description
15  * -------- -------- ------------------------------------------------------
16  * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000.
17  * 06-06-00 01.00.01 Update version number for 1.0 release.
18  * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages.
19  * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2
20  * fields to FC_DEVICE_0 page, updated the page version.
21  * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in
22  * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages
23  * and updated the page versions.
24  * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1
25  * page and updated the page version.
26  * Added Information field and _INFO_PARAMS_NEGOTIATED
27  * definitionto SCSI_DEVICE_0 page.
28  * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the
29  * page version.
30  * Added BucketsRemaining to LAN_1 page, redefined the
31  * state values, and updated the page version.
32  * Revised bus width definitions in SCSI_PORT_0,
33  * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages.
34  * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page
35  * version.
36  * Moved FC_DEVICE_0 PageAddress description to spec.
37  * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field
38  * widths in IOC_0 page and updated the page version.
39  * 11-02-00 01.01.01 Original release for post 1.0 work
40  * Added Manufacturing pages, IO Unit Page 2, SCSI SPI
41  * Port Page 2, FC Port Page 4, FC Port Page 5
42  * 11-15-00 01.01.02 Interim changes to match proposals
43  * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01.
44  * 12-05-00 01.01.04 Modified config page actions.
45  * 01-09-01 01.01.05 Added defines for page address formats.
46  * Data size for Manufacturing pages 2 and 3 no longer
47  * defined here.
48  * Io Unit Page 2 size is fixed at 4 adapters and some
49  * flags were changed.
50  * SCSI Port Page 2 Device Settings modified.
51  * New fields added to FC Port Page 0 and some flags
52  * cleaned up.
53  * Removed impedance flash from FC Port Page 1.
54  * Added FC Port pages 6 and 7.
55  * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0.
56  * 01-29-01 01.01.07 Changed some defines to make them 32 character unique.
57  * Added some LinkType defines for FcPortPage0.
58  * 02-20-01 01.01.08 Started using MPI_POINTER.
59  * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with
60  * MPI_CONFIG_PAGETYPE_RAID_VOLUME.
61  * Added definitions and structures for IOC Page 2 and
62  * RAID Volume Page 2.
63  * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9.
64  * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID.
65  * Added VendorId and ProductRevLevel fields to
66  * RAIDVOL2_IM_PHYS_ID struct.
67  * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_
68  * defines to make them compatible to MPI version 1.0.
69  * Added structure offset comments.
70  * 04-09-01 01.01.11 Added some new defines for the PageAddress field and
71  * removed some obsolete ones.
72  * Added IO Unit Page 3.
73  * Modified defines for Scsi Port Page 2.
74  * Modified RAID Volume Pages.
75  * 08-08-01 01.02.01 Original release for v1.2 work.
76  * Added SepID and SepBus to RVP2 IMPhysicalDisk struct.
77  * Added defines for the SEP bits in RVP2 VolumeSettings.
78  * Modified the DeviceSettings field in RVP2 to use the
79  * proper structure.
80  * Added defines for SES, SAF-TE, and cross channel for
81  * IOCPage2 CapabilitiesFlags.
82  * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE.
83  * Removed define for
84  * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE.
85  * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT.
86  * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035.
87  * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY
88  * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY.
89  * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS,
90  * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and
91  * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and
92  * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED.
93  * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED
94  * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED.
95  * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1.
96  * Added rejected bits to SCSI Device Page 0 Information.
97  * Increased size of ALPA array in FC Port Page 2 by one
98  * and removed a one byte reserved field.
99  * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in
100  * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering.
101  * Added structures for Manufacturing Page 4, IO Unit
102  * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and
103  * RAID PhysDisk Page 0.
104  * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK.
105  * Modified some of the new defines to make them 32
106  * character unique.
107  * Modified how variable length pages (arrays) are defined.
108  * Added generic defines for hot spare pools and RAID
109  * volume types.
110  * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR.
111  * 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with
112  * related define, and bumped the page version define.
113  * 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a
114  * reserved byte and added a define.
115  * Added define for
116  * MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE.
117  * Added new config page: CONFIG_PAGE_IOC_5.
118  * Added MaxAliases, MaxHardAliases, and NumCurrentAliases
119  * fields to CONFIG_PAGE_FC_PORT_0.
120  * Added AltConnector and NumRequestedAliases fields to
121  * CONFIG_PAGE_FC_PORT_1.
122  * Added new config page: CONFIG_PAGE_FC_PORT_10.
123  * 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines.
124  * Added additional MPI_SCSIDEVPAGE0_NP_ defines.
125  * Added more MPI_SCSIDEVPAGE1_RP_ defines.
126  * Added define for
127  * MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE.
128  * Added new config page: CONFIG_PAGE_SCSI_DEVICE_3.
129  * Modified MPI_FCPORTPAGE5_FLAGS_ defines.
130  * 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define.
131  * 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0.
132  * Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
133  * Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0.
134  * 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for
135  * CONFIG_PAGE_FC_PORT_1.
136  * Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable
137  * an alias.
138  * Added more device id defines.
139  * 06-26-03 01.02.12 Added MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID define.
140  * Added TargetConfig and IDConfig fields to
141  * CONFIG_PAGE_SCSI_PORT_1.
142  * Added more PortFlags defines for CONFIG_PAGE_SCSI_PORT_2
143  * to control DV.
144  * Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
145  * In CONFIG_PAGE_FC_DEVICE_0, replaced Reserved1 field
146  * with ADISCHardALPA.
147  * Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define.
148  * 01-16-04 01.02.13 Added InitiatorDeviceTimeout and InitiatorIoPendTimeout
149  * fields and related defines to CONFIG_PAGE_FC_PORT_1.
150  * Added define for
151  * MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK.
152  * Added new fields to the substructures of
153  * CONFIG_PAGE_FC_PORT_10.
154  * 04-29-04 01.02.14 Added define for IDP bit for CONFIG_PAGE_SCSI_PORT_0,
155  * CONFIG_PAGE_SCSI_DEVICE_0, and
156  * CONFIG_PAGE_SCSI_DEVICE_1. Also bumped Page Version for
157  * these pages.
158  * 05-11-04 01.03.01 Added structure for CONFIG_PAGE_INBAND_0.
159  * 08-19-04 01.05.01 Modified MSG_CONFIG request to support extended config
160  * pages.
161  * Added a new structure for extended config page header.
162  * Added new extended config pages types and structures for
163  * SAS IO Unit, SAS Expander, SAS Device, and SAS PHY.
164  * Replaced a reserved byte in CONFIG_PAGE_MANUFACTURING_4
165  * to add a Flags field.
166  * Two new Manufacturing config pages (5 and 6).
167  * Two new bits defined for IO Unit Page 1 Flags field.
168  * Modified CONFIG_PAGE_IO_UNIT_2 to add three new fields
169  * to specify the BIOS boot device.
170  * Four new Flags bits defined for IO Unit Page 2.
171  * Added IO Unit Page 4.
172  * Added EEDP Flags settings to IOC Page 1.
173  * Added new BIOS Page 1 config page.
174  * 10-05-04 01.05.02 Added define for
175  * MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE.
176  * Added new Flags field to CONFIG_PAGE_MANUFACTURING_5 and
177  * associated defines.
178  * Added more defines for SAS IO Unit Page 0
179  * DiscoveryStatus field.
180  * Added define for MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK
181  * and MPI_SAS_IOUNIT0_DS_TABLE_LINK.
182  * Added defines for Physical Mapping Modes to SAS IO Unit
183  * Page 2.
184  * Added define for
185  * MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH.
186  * 10-27-04 01.05.03 Added defines for new SAS PHY page addressing mode.
187  * Added defines for MaxTargetSpinUp to BIOS Page 1.
188  * Added 5 new ControlFlags defines for SAS IO Unit
189  * Page 1.
190  * Added MaxNumPhysicalMappedIDs field to SAS IO Unit
191  * Page 2.
192  * Added AccessStatus field to SAS Device Page 0 and added
193  * new Flags bits for supported SATA features.
194  * 12-07-04 01.05.04 Added config page structures for BIOS Page 2, RAID
195  * Volume Page 1, and RAID Physical Disk Page 1.
196  * Replaced IO Unit Page 1 BootTargetID,BootBus, and
197  * BootAdapterNum with reserved field.
198  * Added DataScrubRate and ResyncRate to RAID Volume
199  * Page 0.
200  * Added MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT
201  * define.
202  * 12-09-04 01.05.05 Added Target Mode Large CDB Enable to FC Port Page 1
203  * Flags field.
204  * Added Auto Port Config flag define for SAS IOUNIT
205  * Page 1 ControlFlags.
206  * Added Disabled bad Phy define to Expander Page 1
207  * Discovery Info field.
208  * Added SAS/SATA device support to SAS IOUnit Page 1
209  * ControlFlags.
210  * Added Unsupported device to SAS Dev Page 0 Flags field
211  * Added disable use SATA Hash Address for SAS IOUNIT
212  * page 1 in ControlFields.
213  * 01-15-05 01.05.06 Added defaults for data scrub rate and resync rate to
214  * Manufacturing Page 4.
215  * Added new defines for BIOS Page 1 IOCSettings field.
216  * Added ExtDiskIdentifier field to RAID Physical Disk
217  * Page 0.
218  * Added new defines for SAS IO Unit Page 1 ControlFlags
219  * and to SAS Device Page 0 Flags to control SATA devices.
220  * Added defines and structures for the new Log Page 0, a
221  * new type of configuration page.
222  * 02-09-05 01.05.07 Added InactiveStatus field to RAID Volume Page 0.
223  * Added WWID field to RAID Volume Page 1.
224  * Added PhysicalPort field to SAS Expander pages 0 and 1.
225  * 03-11-05 01.05.08 Removed the EEDP flags from IOC Page 1.
226  * Added Enclosure/Slot boot device format to BIOS Page 2.
227  * New status value for RAID Volume Page 0 VolumeStatus
228  * (VolumeState subfield).
229  * New value for RAID Physical Page 0 InactiveStatus.
230  * Added Inactive Volume Member flag RAID Physical Disk
231  * Page 0 PhysDiskStatus field.
232  * New physical mapping mode in SAS IO Unit Page 2.
233  * Added CONFIG_PAGE_SAS_ENCLOSURE_0.
234  * Added Slot and Enclosure fields to SAS Device Page 0.
235  * 06-24-05 01.05.09 Added EEDP defines to IOC Page 1.
236  * Added more RAID type defines to IOC Page 2.
237  * Added Port Enable Delay settings to BIOS Page 1.
238  * Added Bad Block Table Full define to RAID Volume Page 0.
239  * Added Previous State defines to RAID Physical Disk
240  * Page 0.
241  * Added Max Sata Targets define for DiscoveryStatus field
242  * of SAS IO Unit Page 0.
243  * Added Device Self Test to Control Flags of SAS IO Unit
244  * Page 1.
245  * Added Direct Attach Starting Slot Number define for SAS
246  * IO Unit Page 2.
247  * Added new fields in SAS Device Page 2 for enclosure
248  * mapping.
249  * Added OwnerDevHandle and Flags field to SAS PHY Page 0.
250  * Added IOC GPIO Flags define to SAS Enclosure Page 0.
251  * Fixed the value for MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT.
252  * 08-03-05 01.05.10 Removed ISDataScrubRate and ISResyncRate from
253  * Manufacturing Page 4.
254  * Added MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE bit.
255  * Added NumDevsPerEnclosure field to SAS IO Unit page 2.
256  * Added MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP
257  * define.
258  * Added EnclosureHandle field to SAS Expander page 0.
259  * Removed redundant NumTableEntriesProg field from SAS
260  * Expander Page 1.
261  * 08-30-05 01.05.11 Added DeviceID for FC949E and changed the DeviceID for
262  * SAS1078.
263  * Added more defines for Manufacturing Page 4 Flags field.
264  * Added more defines for IOCSettings and added
265  * ExpanderSpinup field to Bios Page 1.
266  * Added postpone SATA Init bit to SAS IO Unit Page 1
267  * ControlFlags.
268  * Changed LogEntry format for Log Page 0.
269  * 03-27-06 01.05.12 Added two new Flags defines for Manufacturing Page 4.
270  * Added Manufacturing Page 7.
271  * Added MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING.
272  * Added IOC Page 6.
273  * Added PrevBootDeviceForm field to CONFIG_PAGE_BIOS_2.
274  * Added MaxLBAHigh field to RAID Volume Page 0.
275  * Added Nvdata version fields to SAS IO Unit Page 0.
276  * Added AdditionalControlFlags, MaxTargetPortConnectTime,
277  * ReportDeviceMissingDelay, and IODeviceMissingDelay
278  * fields to SAS IO Unit Page 1.
279  * 10-11-06 01.05.13 Added NumForceWWID field and ForceWWID array to
280  * Manufacturing Page 5.
281  * Added Manufacturing pages 8 through 10.
282  * Added defines for supported metadata size bits in
283  * CapabilitiesFlags field of IOC Page 6.
284  * Added defines for metadata size bits in VolumeSettings
285  * field of RAID Volume Page 0.
286  * Added SATA Link Reset settings, Enable SATA Asynchronous
287  * Notification bit, and HideNonZeroAttachedPhyIdentifiers
288  * bit to AdditionalControlFlags field of SAS IO Unit
289  * Page 1.
290  * Added defines for Enclosure Devices Unmapped and
291  * Device Limit Exceeded bits in Status field of SAS IO
292  * Unit Page 2.
293  * Added more AccessStatus values for SAS Device Page 0.
294  * Added bit for SATA Asynchronous Notification Support in
295  * Flags field of SAS Device Page 0.
296  * 02-28-07 01.05.14 Added ExtFlags field to Manufacturing Page 4.
297  * Added Disable SMART Polling for CapabilitiesFlags of
298  * IOC Page 6.
299  * Added Disable SMART Polling to DeviceSettings of BIOS
300  * Page 1.
301  * Added Multi-Port Domain bit for DiscoveryStatus field
302  * of SAS IO Unit Page.
303  * Added Multi-Port Domain Illegal flag for SAS IO Unit
304  * Page 1 AdditionalControlFlags field.
305  * 05-24-07 01.05.15 Added Hide Physical Disks with Non-Integrated RAID
306  * Metadata bit to Manufacturing Page 4 ExtFlags field.
307  * Added Internal Connector to End Device Present bit to
308  * Expander Page 0 Flags field.
309  * Fixed define for
310  * MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED.
311  * 08-07-07 01.05.16 Added MPI_IOCPAGE6_CAP_FLAGS_MULTIPORT_DRIVE_SUPPORT
312  * define.
313  * Added BIOS Page 4 structure.
314  * Added MPI_RAID_PHYS_DISK1_PATH_MAX define for RAID
315  * Physcial Disk Page 1.
316  * 01-15-07 01.05.17 Added additional bit defines for ExtFlags field of
317  * Manufacturing Page 4.
318  * Added Solid State Drives Supported bit to IOC Page 6
319  * Capabilities Flags.
320  * Added new value for AccessStatus field of SAS Device
321  * Page 0 (_SATA_NEEDS_INITIALIZATION).
322  * 03-28-08 01.05.18 Defined new bits in Manufacturing Page 4 ExtFlags field
323  * to control coercion size and the mixing of SAS and SATA
324  * SSD drives.
325  * --------------------------------------------------------------------------
326  */
327 
328 #ifndef MPI_CNFG_H
329 #define MPI_CNFG_H
330 
331 
332 /*****************************************************************************
333 *
334 * C o n f i g M e s s a g e a n d S t r u c t u r e s
335 *
336 *****************************************************************************/
337 
338 typedef struct _CONFIG_PAGE_HEADER
339 {
340  U8 PageVersion; /* 00h */
341  U8 PageLength; /* 01h */
342  U8 PageNumber; /* 02h */
343  U8 PageType; /* 03h */
344 } CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER,
345  ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t;
346 
347 typedef union _CONFIG_PAGE_HEADER_UNION
348 {
349  ConfigPageHeader_t Struct;
350  U8 Bytes[4];
351  U16 Word16[2];
352  U32 Word32;
353 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion,
354  CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION;
355 
356 typedef struct _CONFIG_EXTENDED_PAGE_HEADER
357 {
358  U8 PageVersion; /* 00h */
359  U8 Reserved1; /* 01h */
360  U8 PageNumber; /* 02h */
361  U8 PageType; /* 03h */
362  U16 ExtPageLength; /* 04h */
363  U8 ExtPageType; /* 06h */
364  U8 Reserved2; /* 07h */
365 } CONFIG_EXTENDED_PAGE_HEADER, MPI_POINTER PTR_CONFIG_EXTENDED_PAGE_HEADER,
366  ConfigExtendedPageHeader_t, MPI_POINTER pConfigExtendedPageHeader_t;
367 
368 
369 
370 /****************************************************************************
371 * PageType field values
372 ****************************************************************************/
373 #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00)
374 #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10)
375 #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20)
376 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30)
377 #define MPI_CONFIG_PAGEATTR_MASK (0xF0)
378 
379 #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00)
380 #define MPI_CONFIG_PAGETYPE_IOC (0x01)
381 #define MPI_CONFIG_PAGETYPE_BIOS (0x02)
382 #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03)
383 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04)
384 #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05)
385 #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06)
386 #define MPI_CONFIG_PAGETYPE_LAN (0x07)
387 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
388 #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09)
389 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
390 #define MPI_CONFIG_PAGETYPE_INBAND (0x0B)
391 #define MPI_CONFIG_PAGETYPE_EXTENDED (0x0F)
392 #define MPI_CONFIG_PAGETYPE_MASK (0x0F)
393 
394 #define MPI_CONFIG_TYPENUM_MASK (0x0FFF)
395 
396 
397 /****************************************************************************
398 * ExtPageType field values
399 ****************************************************************************/
400 #define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
401 #define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
402 #define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
403 #define MPI_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
404 #define MPI_CONFIG_EXTPAGETYPE_LOG (0x14)
405 #define MPI_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
406 
407 
408 /****************************************************************************
409 * PageAddress field values
410 ****************************************************************************/
411 #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF)
412 
413 #define MPI_SCSI_DEVICE_FORM_MASK (0xF0000000)
414 #define MPI_SCSI_DEVICE_FORM_BUS_TID (0x00000000)
415 #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF)
416 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0)
417 #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00)
418 #define MPI_SCSI_DEVICE_BUS_SHIFT (8)
419 #define MPI_SCSI_DEVICE_FORM_TARGET_MODE (0x10000000)
420 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_MASK (0x000000FF)
421 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_SHIFT (0)
422 #define MPI_SCSI_DEVICE_TM_BUS_MASK (0x0000FF00)
423 #define MPI_SCSI_DEVICE_TM_BUS_SHIFT (8)
424 #define MPI_SCSI_DEVICE_TM_INIT_ID_MASK (0x00FF0000)
425 #define MPI_SCSI_DEVICE_TM_INIT_ID_SHIFT (16)
426 
427 #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000)
428 #define MPI_FC_PORT_PGAD_PORT_SHIFT (28)
429 #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000)
430 #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000)
431 #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF)
432 #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0)
433 
434 #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000)
435 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28)
436 #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000)
437 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000)
438 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000)
439 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28)
440 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF)
441 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0)
442 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000)
443 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
444 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8)
445 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
446 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0)
447 
448 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
449 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0)
450 
451 #define MPI_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
452 #define MPI_SAS_EXPAND_PGAD_FORM_SHIFT (28)
453 #define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
454 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x00000001)
455 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE (0x00000002)
456 #define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE (0x0000FFFF)
457 #define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE (0)
458 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY (0x00FF0000)
459 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY (16)
460 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE (0x0000FFFF)
461 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE (0)
462 #define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE (0x0000FFFF)
463 #define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE (0)
464 
465 #define MPI_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
466 #define MPI_SAS_DEVICE_PGAD_FORM_SHIFT (28)
467 #define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
468 #define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID (0x00000001)
469 #define MPI_SAS_DEVICE_PGAD_FORM_HANDLE (0x00000002)
470 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK (0x0000FFFF)
471 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT (0)
472 #define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
473 #define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT (8)
474 #define MPI_SAS_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
475 #define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT (0)
476 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK (0x0000FFFF)
477 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT (0)
478 
479 #define MPI_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
480 #define MPI_SAS_PHY_PGAD_FORM_SHIFT (28)
481 #define MPI_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x0)
482 #define MPI_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x1)
483 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
484 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (0)
485 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
486 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_SHIFT (0)
487 
488 #define MPI_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
489 #define MPI_SAS_ENCLOS_PGAD_FORM_SHIFT (28)
490 #define MPI_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
491 #define MPI_SAS_ENCLOS_PGAD_FORM_HANDLE (0x00000001)
492 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_MASK (0x0000FFFF)
493 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_SHIFT (0)
494 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_MASK (0x0000FFFF)
495 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_SHIFT (0)
496 
497 
498 
499 /****************************************************************************
500 * Config Request Message
501 ****************************************************************************/
502 typedef struct _MSG_CONFIG
503 {
504  U8 Action; /* 00h */
505  U8 Reserved; /* 01h */
506  U8 ChainOffset; /* 02h */
507  U8 Function; /* 03h */
508  U16 ExtPageLength; /* 04h */
509  U8 ExtPageType; /* 06h */
510  U8 MsgFlags; /* 07h */
511  U32 MsgContext; /* 08h */
512  U8 Reserved2[8]; /* 0Ch */
513  CONFIG_PAGE_HEADER Header; /* 14h */
514  U32 PageAddress; /* 18h */
515  SGE_IO_UNION PageBufferSGE; /* 1Ch */
516 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG,
517  Config_t, MPI_POINTER pConfig_t;
518 
519 
520 /****************************************************************************
521 * Action field values
522 ****************************************************************************/
523 #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00)
524 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
525 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
526 #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03)
527 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
528 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
529 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
530 
531 
532 /* Config Reply Message */
533 typedef struct _MSG_CONFIG_REPLY
534 {
535  U8 Action; /* 00h */
536  U8 Reserved; /* 01h */
537  U8 MsgLength; /* 02h */
538  U8 Function; /* 03h */
539  U16 ExtPageLength; /* 04h */
540  U8 ExtPageType; /* 06h */
541  U8 MsgFlags; /* 07h */
542  U32 MsgContext; /* 08h */
543  U8 Reserved2[2]; /* 0Ch */
544  U16 IOCStatus; /* 0Eh */
545  U32 IOCLogInfo; /* 10h */
546  CONFIG_PAGE_HEADER Header; /* 14h */
547 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY,
548  ConfigReply_t, MPI_POINTER pConfigReply_t;
549 
550 
551 
552 /*****************************************************************************
553 *
554 * C o n f i g u r a t i o n P a g e s
555 *
556 *****************************************************************************/
557 
558 /****************************************************************************
559 * Manufacturing Config pages
560 ****************************************************************************/
561 #define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000)
562 /* Fibre Channel */
563 #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621)
564 #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624)
565 #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622)
566 #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628)
567 #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626)
568 #define MPI_MANUFACTPAGE_DEVICEID_FC939X (0x0642)
569 #define MPI_MANUFACTPAGE_DEVICEID_FC949X (0x0640)
570 #define MPI_MANUFACTPAGE_DEVICEID_FC949E (0x0646)
571 /* SCSI */
572 #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030)
573 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031)
574 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032)
575 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033)
576 #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040)
577 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041)
578 /* SAS */
579 #define MPI_MANUFACTPAGE_DEVID_SAS1064 (0x0050)
580 #define MPI_MANUFACTPAGE_DEVID_SAS1064A (0x005C)
581 #define MPI_MANUFACTPAGE_DEVID_SAS1064E (0x0056)
582 #define MPI_MANUFACTPAGE_DEVID_SAS1066 (0x005E)
583 #define MPI_MANUFACTPAGE_DEVID_SAS1066E (0x005A)
584 #define MPI_MANUFACTPAGE_DEVID_SAS1068 (0x0054)
585 #define MPI_MANUFACTPAGE_DEVID_SAS1068E (0x0058)
586 #define MPI_MANUFACTPAGE_DEVID_SAS1068_820XELP (0x0059)
587 #define MPI_MANUFACTPAGE_DEVID_SAS1078 (0x0062)
588 
589 
590 typedef struct _CONFIG_PAGE_MANUFACTURING_0
591 {
592  CONFIG_PAGE_HEADER Header; /* 00h */
593  U8 ChipName[16]; /* 04h */
594  U8 ChipRevision[8]; /* 14h */
595  U8 BoardName[16]; /* 1Ch */
596  U8 BoardAssembly[16]; /* 2Ch */
597  U8 BoardTracerNumber[16]; /* 3Ch */
598 
599 } CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0,
600  ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t;
601 
602 #define MPI_MANUFACTURING0_PAGEVERSION (0x00)
603 
604 
605 typedef struct _CONFIG_PAGE_MANUFACTURING_1
606 {
607  CONFIG_PAGE_HEADER Header; /* 00h */
608  U8 VPD[256]; /* 04h */
609 } CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1,
610  ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t;
611 
612 #define MPI_MANUFACTURING1_PAGEVERSION (0x00)
613 
614 
615 typedef struct _MPI_CHIP_REVISION_ID
616 {
617  U16 DeviceID; /* 00h */
618  U8 PCIRevisionID; /* 02h */
619  U8 Reserved; /* 03h */
620 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID,
621  MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t;
622 
623 
624 /*
625  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
626  * one and check Header.PageLength at runtime.
627  */
628 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS
629 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
630 #endif
631 
632 typedef struct _CONFIG_PAGE_MANUFACTURING_2
633 {
634  CONFIG_PAGE_HEADER Header; /* 00h */
635  MPI_CHIP_REVISION_ID ChipId; /* 04h */
636  U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */
637 } CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2,
638  ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t;
639 
640 #define MPI_MANUFACTURING2_PAGEVERSION (0x00)
641 
642 
643 /*
644  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
645  * one and check Header.PageLength at runtime.
646  */
647 #ifndef MPI_MAN_PAGE_3_INFO_WORDS
648 #define MPI_MAN_PAGE_3_INFO_WORDS (1)
649 #endif
650 
651 typedef struct _CONFIG_PAGE_MANUFACTURING_3
652 {
653  CONFIG_PAGE_HEADER Header; /* 00h */
654  MPI_CHIP_REVISION_ID ChipId; /* 04h */
655  U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */
656 } CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3,
657  ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t;
658 
659 #define MPI_MANUFACTURING3_PAGEVERSION (0x00)
660 
661 
662 typedef struct _CONFIG_PAGE_MANUFACTURING_4
663 {
664  CONFIG_PAGE_HEADER Header; /* 00h */
665  U32 Reserved1; /* 04h */
666  U8 InfoOffset0; /* 08h */
667  U8 InfoSize0; /* 09h */
668  U8 InfoOffset1; /* 0Ah */
669  U8 InfoSize1; /* 0Bh */
670  U8 InquirySize; /* 0Ch */
671  U8 Flags; /* 0Dh */
672  U16 ExtFlags; /* 0Eh */
673  U8 InquiryData[56]; /* 10h */
674  U32 ISVolumeSettings; /* 48h */
675  U32 IMEVolumeSettings; /* 4Ch */
676  U32 IMVolumeSettings; /* 50h */
677  U32 Reserved3; /* 54h */
678  U32 Reserved4; /* 58h */
679  U32 Reserved5; /* 5Ch */
680  U8 IMEDataScrubRate; /* 60h */
681  U8 IMEResyncRate; /* 61h */
682  U16 Reserved6; /* 62h */
683  U8 IMDataScrubRate; /* 64h */
684  U8 IMResyncRate; /* 65h */
685  U16 Reserved7; /* 66h */
686  U32 Reserved8; /* 68h */
687  U32 Reserved9; /* 6Ch */
688 } CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4,
689  ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t;
690 
691 #define MPI_MANUFACTURING4_PAGEVERSION (0x05)
692 
693 /* defines for the Flags field */
694 #define MPI_MANPAGE4_FORCE_BAD_BLOCK_TABLE (0x80)
695 #define MPI_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x40)
696 #define MPI_MANPAGE4_IME_DISABLE (0x20)
697 #define MPI_MANPAGE4_IM_DISABLE (0x10)
698 #define MPI_MANPAGE4_IS_DISABLE (0x08)
699 #define MPI_MANPAGE4_IR_MODEPAGE8_DISABLE (0x04)
700 #define MPI_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x02)
701 #define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA (0x01)
702 
703 /* defines for the ExtFlags field */
704 #define MPI_MANPAGE4_EXTFLAGS_MASK_COERCION_SIZE (0x0180)
705 #define MPI_MANPAGE4_EXTFLAGS_SHIFT_COERCION_SIZE (7)
706 #define MPI_MANPAGE4_EXTFLAGS_1GB_COERCION_SIZE (0)
707 #define MPI_MANPAGE4_EXTFLAGS_128MB_COERCION_SIZE (1)
708 
709 #define MPI_MANPAGE4_EXTFLAGS_NO_MIX_SSD_SAS_SATA (0x0040)
710 #define MPI_MANPAGE4_EXTFLAGS_MIX_SSD_AND_NON_SSD (0x0020)
711 #define MPI_MANPAGE4_EXTFLAGS_DUAL_PORT_SUPPORT (0x0010)
712 #define MPI_MANPAGE4_EXTFLAGS_HIDE_NON_IR_METADATA (0x0008)
713 #define MPI_MANPAGE4_EXTFLAGS_SAS_CACHE_DISABLE (0x0004)
714 #define MPI_MANPAGE4_EXTFLAGS_SATA_CACHE_DISABLE (0x0002)
715 #define MPI_MANPAGE4_EXTFLAGS_LEGACY_MODE (0x0001)
716 
717 
718 #ifndef MPI_MANPAGE5_NUM_FORCEWWID
719 #define MPI_MANPAGE5_NUM_FORCEWWID (1)
720 #endif
721 
722 typedef struct _CONFIG_PAGE_MANUFACTURING_5
723 {
724  CONFIG_PAGE_HEADER Header; /* 00h */
725  U64 BaseWWID; /* 04h */
726  U8 Flags; /* 0Ch */
727  U8 NumForceWWID; /* 0Dh */
728  U16 Reserved2; /* 0Eh */
729  U32 Reserved3; /* 10h */
730  U32 Reserved4; /* 14h */
731  U64 ForceWWID[MPI_MANPAGE5_NUM_FORCEWWID]; /* 18h */
732 } CONFIG_PAGE_MANUFACTURING_5, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_5,
733  ManufacturingPage5_t, MPI_POINTER pManufacturingPage5_t;
734 
735 #define MPI_MANUFACTURING5_PAGEVERSION (0x02)
736 
737 /* defines for the Flags field */
738 #define MPI_MANPAGE5_TWO_WWID_PER_PHY (0x01)
739 
740 
741 typedef struct _CONFIG_PAGE_MANUFACTURING_6
742 {
743  CONFIG_PAGE_HEADER Header; /* 00h */
744  U32 ProductSpecificInfo;/* 04h */
745 } CONFIG_PAGE_MANUFACTURING_6, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_6,
746  ManufacturingPage6_t, MPI_POINTER pManufacturingPage6_t;
747 
748 #define MPI_MANUFACTURING6_PAGEVERSION (0x00)
749 
750 
751 typedef struct _MPI_MANPAGE7_CONNECTOR_INFO
752 {
753  U32 Pinout; /* 00h */
754  U8 Connector[16]; /* 04h */
755  U8 Location; /* 14h */
756  U8 Reserved1; /* 15h */
757  U16 Slot; /* 16h */
758  U32 Reserved2; /* 18h */
759 } MPI_MANPAGE7_CONNECTOR_INFO, MPI_POINTER PTR_MPI_MANPAGE7_CONNECTOR_INFO,
760  MpiManPage7ConnectorInfo_t, MPI_POINTER pMpiManPage7ConnectorInfo_t;
761 
762 /* defines for the Pinout field */
763 #define MPI_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000)
764 #define MPI_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000)
765 #define MPI_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000)
766 #define MPI_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000)
767 #define MPI_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800)
768 #define MPI_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400)
769 #define MPI_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200)
770 #define MPI_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100)
771 #define MPI_MANPAGE7_PINOUT_SFF_8482 (0x00000002)
772 #define MPI_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001)
773 
774 /* defines for the Location field */
775 #define MPI_MANPAGE7_LOCATION_UNKNOWN (0x01)
776 #define MPI_MANPAGE7_LOCATION_INTERNAL (0x02)
777 #define MPI_MANPAGE7_LOCATION_EXTERNAL (0x04)
778 #define MPI_MANPAGE7_LOCATION_SWITCHABLE (0x08)
779 #define MPI_MANPAGE7_LOCATION_AUTO (0x10)
780 #define MPI_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
781 #define MPI_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
782 
783 /*
784  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
785  * one and check NumPhys at runtime.
786  */
787 #ifndef MPI_MANPAGE7_CONNECTOR_INFO_MAX
788 #define MPI_MANPAGE7_CONNECTOR_INFO_MAX (1)
789 #endif
790 
791 typedef struct _CONFIG_PAGE_MANUFACTURING_7
792 {
793  CONFIG_PAGE_HEADER Header; /* 00h */
794  U32 Reserved1; /* 04h */
795  U32 Reserved2; /* 08h */
796  U32 Flags; /* 0Ch */
797  U8 EnclosureName[16]; /* 10h */
798  U8 NumPhys; /* 20h */
799  U8 Reserved3; /* 21h */
800  U16 Reserved4; /* 22h */
801  MPI_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI_MANPAGE7_CONNECTOR_INFO_MAX]; /* 24h */
802 } CONFIG_PAGE_MANUFACTURING_7, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_7,
803  ManufacturingPage7_t, MPI_POINTER pManufacturingPage7_t;
804 
805 #define MPI_MANUFACTURING7_PAGEVERSION (0x00)
806 
807 /* defines for the Flags field */
808 #define MPI_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
809 
810 
811 typedef struct _CONFIG_PAGE_MANUFACTURING_8
812 {
813  CONFIG_PAGE_HEADER Header; /* 00h */
814  U32 ProductSpecificInfo;/* 04h */
815 } CONFIG_PAGE_MANUFACTURING_8, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_8,
816  ManufacturingPage8_t, MPI_POINTER pManufacturingPage8_t;
817 
818 #define MPI_MANUFACTURING8_PAGEVERSION (0x00)
819 
820 
821 typedef struct _CONFIG_PAGE_MANUFACTURING_9
822 {
823  CONFIG_PAGE_HEADER Header; /* 00h */
824  U32 ProductSpecificInfo;/* 04h */
825 } CONFIG_PAGE_MANUFACTURING_9, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_9,
826  ManufacturingPage9_t, MPI_POINTER pManufacturingPage9_t;
827 
828 #define MPI_MANUFACTURING9_PAGEVERSION (0x00)
829 
830 
831 typedef struct _CONFIG_PAGE_MANUFACTURING_10
832 {
833  CONFIG_PAGE_HEADER Header; /* 00h */
834  U32 ProductSpecificInfo;/* 04h */
835 } CONFIG_PAGE_MANUFACTURING_10, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_10,
836  ManufacturingPage10_t, MPI_POINTER pManufacturingPage10_t;
837 
838 #define MPI_MANUFACTURING10_PAGEVERSION (0x00)
839 
840 
841 /****************************************************************************
842 * IO Unit Config Pages
843 ****************************************************************************/
844 
845 typedef struct _CONFIG_PAGE_IO_UNIT_0
846 {
847  CONFIG_PAGE_HEADER Header; /* 00h */
848  U64 UniqueValue; /* 04h */
849 } CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0,
850  IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t;
851 
852 #define MPI_IOUNITPAGE0_PAGEVERSION (0x00)
853 
854 
855 typedef struct _CONFIG_PAGE_IO_UNIT_1
856 {
857  CONFIG_PAGE_HEADER Header; /* 00h */
858  U32 Flags; /* 04h */
859 } CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1,
860  IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t;
861 
862 #define MPI_IOUNITPAGE1_PAGEVERSION (0x02)
863 
864 /* IO Unit Page 1 Flags defines */
865 #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000)
866 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001)
867 #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002)
868 #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
869 #define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
870 #define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING (0x00000020)
871 #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040)
872 #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080)
873 #define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
874 #define MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE (0x00000200)
875 
876 typedef struct _MPI_ADAPTER_INFO
877 {
878  U8 PciBusNumber; /* 00h */
879  U8 PciDeviceAndFunctionNumber; /* 01h */
880  U16 AdapterFlags; /* 02h */
881 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO,
882  MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t;
883 
884 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
885 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
886 
887 typedef struct _CONFIG_PAGE_IO_UNIT_2
888 {
889  CONFIG_PAGE_HEADER Header; /* 00h */
890  U32 Flags; /* 04h */
891  U32 BiosVersion; /* 08h */
892  MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */
893  U32 Reserved1; /* 1Ch */
894 } CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2,
895  IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t;
896 
897 #define MPI_IOUNITPAGE2_PAGEVERSION (0x02)
898 
899 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002)
900 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004)
901 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008)
902 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010)
903 
904 #define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
905 #define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
906 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY (0x00000020)
907 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
908 
909 
910 /*
911  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
912  * one and check Header.PageLength at runtime.
913  */
914 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX
915 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
916 #endif
917 
918 typedef struct _CONFIG_PAGE_IO_UNIT_3
919 {
920  CONFIG_PAGE_HEADER Header; /* 00h */
921  U8 GPIOCount; /* 04h */
922  U8 Reserved1; /* 05h */
923  U16 Reserved2; /* 06h */
924  U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */
925 } CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3,
926  IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t;
927 
928 #define MPI_IOUNITPAGE3_PAGEVERSION (0x01)
929 
930 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC)
931 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
932 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00)
933 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01)
934 
935 
936 typedef struct _CONFIG_PAGE_IO_UNIT_4
937 {
938  CONFIG_PAGE_HEADER Header; /* 00h */
939  U32 Reserved1; /* 04h */
940  SGE_SIMPLE_UNION FWImageSGE; /* 08h */
941 } CONFIG_PAGE_IO_UNIT_4, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_4,
942  IOUnitPage4_t, MPI_POINTER pIOUnitPage4_t;
943 
944 #define MPI_IOUNITPAGE4_PAGEVERSION (0x00)
945 
946 
947 /****************************************************************************
948 * IOC Config Pages
949 ****************************************************************************/
950 
951 typedef struct _CONFIG_PAGE_IOC_0
952 {
953  CONFIG_PAGE_HEADER Header; /* 00h */
954  U32 TotalNVStore; /* 04h */
955  U32 FreeNVStore; /* 08h */
956  U16 VendorID; /* 0Ch */
957  U16 DeviceID; /* 0Eh */
958  U8 RevisionID; /* 10h */
959  U8 Reserved[3]; /* 11h */
960  U32 ClassCode; /* 14h */
961  U16 SubsystemVendorID; /* 18h */
962  U16 SubsystemID; /* 1Ah */
963 } CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0,
964  IOCPage0_t, MPI_POINTER pIOCPage0_t;
965 
966 #define MPI_IOCPAGE0_PAGEVERSION (0x01)
967 
968 
969 typedef struct _CONFIG_PAGE_IOC_1
970 {
971  CONFIG_PAGE_HEADER Header; /* 00h */
972  U32 Flags; /* 04h */
973  U32 CoalescingTimeout; /* 08h */
974  U8 CoalescingDepth; /* 0Ch */
975  U8 PCISlotNum; /* 0Dh */
976  U8 Reserved[2]; /* 0Eh */
977 } CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1,
978  IOCPage1_t, MPI_POINTER pIOCPage1_t;
979 
980 #define MPI_IOCPAGE1_PAGEVERSION (0x03)
981 
982 /* defines for the Flags field */
983 #define MPI_IOCPAGE1_EEDP_MODE_MASK (0x07000000)
984 #define MPI_IOCPAGE1_EEDP_MODE_OFF (0x00000000)
985 #define MPI_IOCPAGE1_EEDP_MODE_T10 (0x01000000)
986 #define MPI_IOCPAGE1_EEDP_MODE_LSI_1 (0x02000000)
987 #define MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE (0x00000010)
988 #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001)
989 
990 #define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
991 
992 
993 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL
994 {
995  U8 VolumeID; /* 00h */
996  U8 VolumeBus; /* 01h */
997  U8 VolumeIOC; /* 02h */
998  U8 VolumePageNumber; /* 03h */
999  U8 VolumeType; /* 04h */
1000  U8 Flags; /* 05h */
1001  U16 Reserved3; /* 06h */
1002 } CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL,
1003  ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t;
1004 
1005 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */
1006 
1007 #define MPI_RAID_VOL_TYPE_IS (0x00)
1008 #define MPI_RAID_VOL_TYPE_IME (0x01)
1009 #define MPI_RAID_VOL_TYPE_IM (0x02)
1010 #define MPI_RAID_VOL_TYPE_RAID_5 (0x03)
1011 #define MPI_RAID_VOL_TYPE_RAID_6 (0x04)
1012 #define MPI_RAID_VOL_TYPE_RAID_10 (0x05)
1013 #define MPI_RAID_VOL_TYPE_RAID_50 (0x06)
1014 #define MPI_RAID_VOL_TYPE_UNKNOWN (0xFF)
1015 
1016 /* IOC Page 2 Volume Flags values */
1017 
1018 #define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08)
1019 
1020 /*
1021  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1022  * one and check Header.PageLength at runtime.
1023  */
1024 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX
1025 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1)
1026 #endif
1027 
1028 typedef struct _CONFIG_PAGE_IOC_2
1029 {
1030  CONFIG_PAGE_HEADER Header; /* 00h */
1031  U32 CapabilitiesFlags; /* 04h */
1032  U8 NumActiveVolumes; /* 08h */
1033  U8 MaxVolumes; /* 09h */
1034  U8 NumActivePhysDisks; /* 0Ah */
1035  U8 MaxPhysDisks; /* 0Bh */
1036  CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */
1037 } CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2,
1038  IOCPage2_t, MPI_POINTER pIOCPage2_t;
1039 
1040 #define MPI_IOCPAGE2_PAGEVERSION (0x04)
1041 
1042 /* IOC Page 2 Capabilities flags */
1043 
1044 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001)
1045 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002)
1046 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004)
1047 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_5_SUPPORT (0x00000008)
1048 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_6_SUPPORT (0x00000010)
1049 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_10_SUPPORT (0x00000020)
1050 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_50_SUPPORT (0x00000040)
1051 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING (0x10000000)
1052 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000)
1053 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000)
1054 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000)
1055 
1056 
1057 typedef struct _IOC_3_PHYS_DISK
1058 {
1059  U8 PhysDiskID; /* 00h */
1060  U8 PhysDiskBus; /* 01h */
1061  U8 PhysDiskIOC; /* 02h */
1062  U8 PhysDiskNum; /* 03h */
1063 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK,
1064  Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t;
1065 
1066 /*
1067  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1068  * one and check Header.PageLength at runtime.
1069  */
1070 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX
1071 #define MPI_IOC_PAGE_3_PHYSDISK_MAX (1)
1072 #endif
1073 
1074 typedef struct _CONFIG_PAGE_IOC_3
1075 {
1076  CONFIG_PAGE_HEADER Header; /* 00h */
1077  U8 NumPhysDisks; /* 04h */
1078  U8 Reserved1; /* 05h */
1079  U16 Reserved2; /* 06h */
1080  IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */
1081 } CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3,
1082  IOCPage3_t, MPI_POINTER pIOCPage3_t;
1083 
1084 #define MPI_IOCPAGE3_PAGEVERSION (0x00)
1085 
1086 
1087 typedef struct _IOC_4_SEP
1088 {
1089  U8 SEPTargetID; /* 00h */
1090  U8 SEPBus; /* 01h */
1091  U16 Reserved; /* 02h */
1092 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP,
1093  Ioc4Sep_t, MPI_POINTER pIoc4Sep_t;
1094 
1095 /*
1096  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1097  * one and check Header.PageLength at runtime.
1098  */
1099 #ifndef MPI_IOC_PAGE_4_SEP_MAX
1100 #define MPI_IOC_PAGE_4_SEP_MAX (1)
1101 #endif
1102 
1103 typedef struct _CONFIG_PAGE_IOC_4
1104 {
1105  CONFIG_PAGE_HEADER Header; /* 00h */
1106  U8 ActiveSEP; /* 04h */
1107  U8 MaxSEP; /* 05h */
1108  U16 Reserved1; /* 06h */
1109  IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */
1110 } CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4,
1111  IOCPage4_t, MPI_POINTER pIOCPage4_t;
1112 
1113 #define MPI_IOCPAGE4_PAGEVERSION (0x00)
1114 
1115 
1116 typedef struct _IOC_5_HOT_SPARE
1117 {
1118  U8 PhysDiskNum; /* 00h */
1119  U8 Reserved; /* 01h */
1120  U8 HotSparePool; /* 02h */
1121  U8 Flags; /* 03h */
1122 } IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE,
1123  Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t;
1124 
1125 /* IOC Page 5 HotSpare Flags */
1126 #define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01)
1127 
1128 /*
1129  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1130  * one and check Header.PageLength at runtime.
1131  */
1132 #ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX
1133 #define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1)
1134 #endif
1135 
1136 typedef struct _CONFIG_PAGE_IOC_5
1137 {
1138  CONFIG_PAGE_HEADER Header; /* 00h */
1139  U32 Reserved1; /* 04h */
1140  U8 NumHotSpares; /* 08h */
1141  U8 Reserved2; /* 09h */
1142  U16 Reserved3; /* 0Ah */
1143  IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */
1144 } CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5,
1145  IOCPage5_t, MPI_POINTER pIOCPage5_t;
1146 
1147 #define MPI_IOCPAGE5_PAGEVERSION (0x00)
1148 
1149 typedef struct _CONFIG_PAGE_IOC_6
1150 {
1151  CONFIG_PAGE_HEADER Header; /* 00h */
1152  U32 CapabilitiesFlags; /* 04h */
1153  U8 MaxDrivesIS; /* 08h */
1154  U8 MaxDrivesIM; /* 09h */
1155  U8 MaxDrivesIME; /* 0Ah */
1156  U8 Reserved1; /* 0Bh */
1157  U8 MinDrivesIS; /* 0Ch */
1158  U8 MinDrivesIM; /* 0Dh */
1159  U8 MinDrivesIME; /* 0Eh */
1160  U8 Reserved2; /* 0Fh */
1161  U8 MaxGlobalHotSpares; /* 10h */
1162  U8 Reserved3; /* 11h */
1163  U16 Reserved4; /* 12h */
1164  U32 Reserved5; /* 14h */
1165  U32 SupportedStripeSizeMapIS; /* 18h */
1166  U32 SupportedStripeSizeMapIME; /* 1Ch */
1167  U32 Reserved6; /* 20h */
1168  U8 MetadataSize; /* 24h */
1169  U8 Reserved7; /* 25h */
1170  U16 Reserved8; /* 26h */
1171  U16 MaxBadBlockTableEntries; /* 28h */
1172  U16 Reserved9; /* 2Ah */
1173  U16 IRNvsramUsage; /* 2Ch */
1174  U16 Reserved10; /* 2Eh */
1175  U32 IRNvsramVersion; /* 30h */
1176  U32 Reserved11; /* 34h */
1177  U32 Reserved12; /* 38h */
1178 } CONFIG_PAGE_IOC_6, MPI_POINTER PTR_CONFIG_PAGE_IOC_6,
1179  IOCPage6_t, MPI_POINTER pIOCPage6_t;
1180 
1181 #define MPI_IOCPAGE6_PAGEVERSION (0x01)
1182 
1183 /* IOC Page 6 Capabilities Flags */
1184 
1185 #define MPI_IOCPAGE6_CAP_FLAGS_SSD_SUPPORT (0x00000020)
1186 #define MPI_IOCPAGE6_CAP_FLAGS_MULTIPORT_DRIVE_SUPPORT (0x00000010)
1187 #define MPI_IOCPAGE6_CAP_FLAGS_DISABLE_SMART_POLLING (0x00000008)
1188 
1189 #define MPI_IOCPAGE6_CAP_FLAGS_MASK_METADATA_SIZE (0x00000006)
1190 #define MPI_IOCPAGE6_CAP_FLAGS_64MB_METADATA_SIZE (0x00000000)
1191 #define MPI_IOCPAGE6_CAP_FLAGS_512MB_METADATA_SIZE (0x00000002)
1192 
1193 #define MPI_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1194 
1195 
1196 /****************************************************************************
1197 * BIOS Config Pages
1198 ****************************************************************************/
1199 
1200 typedef struct _CONFIG_PAGE_BIOS_1
1201 {
1202  CONFIG_PAGE_HEADER Header; /* 00h */
1203  U32 BiosOptions; /* 04h */
1204  U32 IOCSettings; /* 08h */
1205  U32 Reserved1; /* 0Ch */
1206  U32 DeviceSettings; /* 10h */
1207  U16 NumberOfDevices; /* 14h */
1208  U8 ExpanderSpinup; /* 16h */
1209  U8 Reserved2; /* 17h */
1210  U16 IOTimeoutBlockDevicesNonRM; /* 18h */
1211  U16 IOTimeoutSequential; /* 1Ah */
1212  U16 IOTimeoutOther; /* 1Ch */
1213  U16 IOTimeoutBlockDevicesRM; /* 1Eh */
1214 } CONFIG_PAGE_BIOS_1, MPI_POINTER PTR_CONFIG_PAGE_BIOS_1,
1215  BIOSPage1_t, MPI_POINTER pBIOSPage1_t;
1216 
1217 #define MPI_BIOSPAGE1_PAGEVERSION (0x03)
1218 
1219 /* values for the BiosOptions field */
1220 #define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE (0x00000400)
1221 #define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE (0x00000200)
1222 #define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE (0x00000100)
1223 #define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1224 
1225 /* values for the IOCSettings field */
1226 #define MPI_BIOSPAGE1_IOCSET_MASK_INITIAL_SPINUP_DELAY (0x0F000000)
1227 #define MPI_BIOSPAGE1_IOCSET_SHIFT_INITIAL_SPINUP_DELAY (24)
1228 
1229 #define MPI_BIOSPAGE1_IOCSET_MASK_PORT_ENABLE_DELAY (0x00F00000)
1230 #define MPI_BIOSPAGE1_IOCSET_SHIFT_PORT_ENABLE_DELAY (20)
1231 
1232 #define MPI_BIOSPAGE1_IOCSET_AUTO_PORT_ENABLE (0x00080000)
1233 #define MPI_BIOSPAGE1_IOCSET_DIRECT_ATTACH_SPINUP_MODE (0x00040000)
1234 
1235 #define MPI_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1236 #define MPI_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1237 #define MPI_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1238 
1239 #define MPI_BIOSPAGE1_IOCSET_MASK_MAX_TARGET_SPIN_UP (0x0000F000)
1240 #define MPI_BIOSPAGE1_IOCSET_SHIFT_MAX_TARGET_SPIN_UP (12)
1241 
1242 #define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY (0x00000F00)
1243 #define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY (8)
1244 
1245 #define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1246 #define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1247 #define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1248 #define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1249 
1250 #define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1251 #define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1252 #define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1253 #define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1254 #define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1255 
1256 #define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1257 
1258 /* values for the DeviceSettings field */
1259 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1260 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1261 #define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1262 #define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1263 #define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1264 
1265 /* defines for the ExpanderSpinup field */
1266 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_MAX_TARGET (0xF0)
1267 #define MPI_BIOSPAGE1_EXPSPINUP_SHIFT_MAX_TARGET (4)
1268 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_DELAY (0x0F)
1269 
1270 typedef struct _MPI_BOOT_DEVICE_ADAPTER_ORDER
1271 {
1272  U32 Reserved1; /* 00h */
1273  U32 Reserved2; /* 04h */
1274  U32 Reserved3; /* 08h */
1275  U32 Reserved4; /* 0Ch */
1276  U32 Reserved5; /* 10h */
1277  U32 Reserved6; /* 14h */
1278  U32 Reserved7; /* 18h */
1279  U32 Reserved8; /* 1Ch */
1280  U32 Reserved9; /* 20h */
1281  U32 Reserved10; /* 24h */
1282  U32 Reserved11; /* 28h */
1283  U32 Reserved12; /* 2Ch */
1284  U32 Reserved13; /* 30h */
1285  U32 Reserved14; /* 34h */
1286  U32 Reserved15; /* 38h */
1287  U32 Reserved16; /* 3Ch */
1288  U32 Reserved17; /* 40h */
1289 } MPI_BOOT_DEVICE_ADAPTER_ORDER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_ORDER;
1290 
1291 typedef struct _MPI_BOOT_DEVICE_ADAPTER_NUMBER
1292 {
1293  U8 TargetID; /* 00h */
1294  U8 Bus; /* 01h */
1295  U8 AdapterNumber; /* 02h */
1296  U8 Reserved1; /* 03h */
1297  U32 Reserved2; /* 04h */
1298  U32 Reserved3; /* 08h */
1299  U32 Reserved4; /* 0Ch */
1300  U8 LUN[8]; /* 10h */
1301  U32 Reserved5; /* 18h */
1302  U32 Reserved6; /* 1Ch */
1303  U32 Reserved7; /* 20h */
1304  U32 Reserved8; /* 24h */
1305  U32 Reserved9; /* 28h */
1306  U32 Reserved10; /* 2Ch */
1307  U32 Reserved11; /* 30h */
1308  U32 Reserved12; /* 34h */
1309  U32 Reserved13; /* 38h */
1310  U32 Reserved14; /* 3Ch */
1311  U32 Reserved15; /* 40h */
1312 } MPI_BOOT_DEVICE_ADAPTER_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_NUMBER;
1313 
1314 typedef struct _MPI_BOOT_DEVICE_PCI_ADDRESS
1315 {
1316  U8 TargetID; /* 00h */
1317  U8 Bus; /* 01h */
1318  U16 PCIAddress; /* 02h */
1319  U32 Reserved1; /* 04h */
1320  U32 Reserved2; /* 08h */
1321  U32 Reserved3; /* 0Ch */
1322  U8 LUN[8]; /* 10h */
1323  U32 Reserved4; /* 18h */
1324  U32 Reserved5; /* 1Ch */
1325  U32 Reserved6; /* 20h */
1326  U32 Reserved7; /* 24h */
1327  U32 Reserved8; /* 28h */
1328  U32 Reserved9; /* 2Ch */
1329  U32 Reserved10; /* 30h */
1330  U32 Reserved11; /* 34h */
1331  U32 Reserved12; /* 38h */
1332  U32 Reserved13; /* 3Ch */
1333  U32 Reserved14; /* 40h */
1334 } MPI_BOOT_DEVICE_PCI_ADDRESS, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_ADDRESS;
1335 
1336 typedef struct _MPI_BOOT_DEVICE_SLOT_NUMBER
1337 {
1338  U8 TargetID; /* 00h */
1339  U8 Bus; /* 01h */
1340  U8 PCISlotNumber; /* 02h */
1341  U8 Reserved1; /* 03h */
1342  U32 Reserved2; /* 04h */
1343  U32 Reserved3; /* 08h */
1344  U32 Reserved4; /* 0Ch */
1345  U8 LUN[8]; /* 10h */
1346  U32 Reserved5; /* 18h */
1347  U32 Reserved6; /* 1Ch */
1348  U32 Reserved7; /* 20h */
1349  U32 Reserved8; /* 24h */
1350  U32 Reserved9; /* 28h */
1351  U32 Reserved10; /* 2Ch */
1352  U32 Reserved11; /* 30h */
1353  U32 Reserved12; /* 34h */
1354  U32 Reserved13; /* 38h */
1355  U32 Reserved14; /* 3Ch */
1356  U32 Reserved15; /* 40h */
1357 } MPI_BOOT_DEVICE_PCI_SLOT_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_SLOT_NUMBER;
1358 
1359 typedef struct _MPI_BOOT_DEVICE_FC_WWN
1360 {
1361  U64 WWPN; /* 00h */
1362  U32 Reserved1; /* 08h */
1363  U32 Reserved2; /* 0Ch */
1364  U8 LUN[8]; /* 10h */
1365  U32 Reserved3; /* 18h */
1366  U32 Reserved4; /* 1Ch */
1367  U32 Reserved5; /* 20h */
1368  U32 Reserved6; /* 24h */
1369  U32 Reserved7; /* 28h */
1370  U32 Reserved8; /* 2Ch */
1371  U32 Reserved9; /* 30h */
1372  U32 Reserved10; /* 34h */
1373  U32 Reserved11; /* 38h */
1374  U32 Reserved12; /* 3Ch */
1375  U32 Reserved13; /* 40h */
1376 } MPI_BOOT_DEVICE_FC_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_FC_WWN;
1377 
1378 typedef struct _MPI_BOOT_DEVICE_SAS_WWN
1379 {
1380  U64 SASAddress; /* 00h */
1381  U32 Reserved1; /* 08h */
1382  U32 Reserved2; /* 0Ch */
1383  U8 LUN[8]; /* 10h */
1384  U32 Reserved3; /* 18h */
1385  U32 Reserved4; /* 1Ch */
1386  U32 Reserved5; /* 20h */
1387  U32 Reserved6; /* 24h */
1388  U32 Reserved7; /* 28h */
1389  U32 Reserved8; /* 2Ch */
1390  U32 Reserved9; /* 30h */
1391  U32 Reserved10; /* 34h */
1392  U32 Reserved11; /* 38h */
1393  U32 Reserved12; /* 3Ch */
1394  U32 Reserved13; /* 40h */
1395 } MPI_BOOT_DEVICE_SAS_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_SAS_WWN;
1396 
1397 typedef struct _MPI_BOOT_DEVICE_ENCLOSURE_SLOT
1398 {
1399  U64 EnclosureLogicalID; /* 00h */
1400  U32 Reserved1; /* 08h */
1401  U32 Reserved2; /* 0Ch */
1402  U8 LUN[8]; /* 10h */
1403  U16 SlotNumber; /* 18h */
1404  U16 Reserved3; /* 1Ah */
1405  U32 Reserved4; /* 1Ch */
1406  U32 Reserved5; /* 20h */
1407  U32 Reserved6; /* 24h */
1408  U32 Reserved7; /* 28h */
1409  U32 Reserved8; /* 2Ch */
1410  U32 Reserved9; /* 30h */
1411  U32 Reserved10; /* 34h */
1412  U32 Reserved11; /* 38h */
1413  U32 Reserved12; /* 3Ch */
1414  U32 Reserved13; /* 40h */
1415 } MPI_BOOT_DEVICE_ENCLOSURE_SLOT,
1416  MPI_POINTER PTR_MPI_BOOT_DEVICE_ENCLOSURE_SLOT;
1417 
1418 typedef union _MPI_BIOSPAGE2_BOOT_DEVICE
1419 {
1420  MPI_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1421  MPI_BOOT_DEVICE_ADAPTER_NUMBER AdapterNumber;
1422  MPI_BOOT_DEVICE_PCI_ADDRESS PCIAddress;
1423  MPI_BOOT_DEVICE_PCI_SLOT_NUMBER PCISlotNumber;
1424  MPI_BOOT_DEVICE_FC_WWN FcWwn;
1425  MPI_BOOT_DEVICE_SAS_WWN SasWwn;
1426  MPI_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1427 } MPI_BIOSPAGE2_BOOT_DEVICE, MPI_POINTER PTR_MPI_BIOSPAGE2_BOOT_DEVICE;
1428 
1429 typedef struct _CONFIG_PAGE_BIOS_2
1430 {
1431  CONFIG_PAGE_HEADER Header; /* 00h */
1432  U32 Reserved1; /* 04h */
1433  U32 Reserved2; /* 08h */
1434  U32 Reserved3; /* 0Ch */
1435  U32 Reserved4; /* 10h */
1436  U32 Reserved5; /* 14h */
1437  U32 Reserved6; /* 18h */
1438  U8 BootDeviceForm; /* 1Ch */
1439  U8 PrevBootDeviceForm; /* 1Ch */
1440  U16 Reserved8; /* 1Eh */
1441  MPI_BIOSPAGE2_BOOT_DEVICE BootDevice; /* 20h */
1442 } CONFIG_PAGE_BIOS_2, MPI_POINTER PTR_CONFIG_PAGE_BIOS_2,
1443  BIOSPage2_t, MPI_POINTER pBIOSPage2_t;
1444 
1445 #define MPI_BIOSPAGE2_PAGEVERSION (0x02)
1446 
1447 #define MPI_BIOSPAGE2_FORM_MASK (0x0F)
1448 #define MPI_BIOSPAGE2_FORM_ADAPTER_ORDER (0x00)
1449 #define MPI_BIOSPAGE2_FORM_ADAPTER_NUMBER (0x01)
1450 #define MPI_BIOSPAGE2_FORM_PCI_ADDRESS (0x02)
1451 #define MPI_BIOSPAGE2_FORM_PCI_SLOT_NUMBER (0x03)
1452 #define MPI_BIOSPAGE2_FORM_FC_WWN (0x04)
1453 #define MPI_BIOSPAGE2_FORM_SAS_WWN (0x05)
1454 #define MPI_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1455 
1456 typedef struct _CONFIG_PAGE_BIOS_4
1457 {
1458  CONFIG_PAGE_HEADER Header; /* 00h */
1459  U64 ReassignmentBaseWWID; /* 04h */
1460 } CONFIG_PAGE_BIOS_4, MPI_POINTER PTR_CONFIG_PAGE_BIOS_4,
1461  BIOSPage4_t, MPI_POINTER pBIOSPage4_t;
1462 
1463 #define MPI_BIOSPAGE4_PAGEVERSION (0x00)
1464 
1465 
1466 /****************************************************************************
1467 * SCSI Port Config Pages
1468 ****************************************************************************/
1469 
1470 typedef struct _CONFIG_PAGE_SCSI_PORT_0
1471 {
1472  CONFIG_PAGE_HEADER Header; /* 00h */
1473  U32 Capabilities; /* 04h */
1474  U32 PhysicalInterface; /* 08h */
1475 } CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0,
1476  SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t;
1477 
1478 #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x02)
1479 
1480 #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001)
1481 #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002)
1482 #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004)
1483 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
1484 #define MPI_SCSIPORTPAGE0_SYNC_ASYNC (0x00)
1485 #define MPI_SCSIPORTPAGE0_SYNC_5 (0x32)
1486 #define MPI_SCSIPORTPAGE0_SYNC_10 (0x19)
1487 #define MPI_SCSIPORTPAGE0_SYNC_20 (0x0C)
1488 #define MPI_SCSIPORTPAGE0_SYNC_33_33 (0x0B)
1489 #define MPI_SCSIPORTPAGE0_SYNC_40 (0x0A)
1490 #define MPI_SCSIPORTPAGE0_SYNC_80 (0x09)
1491 #define MPI_SCSIPORTPAGE0_SYNC_160 (0x08)
1492 #define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN (0xFF)
1493 
1494 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD (8)
1495 #define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap) \
1496  ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK) \
1497  >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD \
1498  )
1499 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
1500 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET (16)
1501 #define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap) \
1502  ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK) \
1503  >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET \
1504  )
1505 #define MPI_SCSIPORTPAGE0_CAP_IDP (0x08000000)
1506 #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000)
1507 #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000)
1508 
1509 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003)
1510 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01)
1511 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02)
1512 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03)
1513 #define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000)
1514 #define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24)
1515 #define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE)
1516 #define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF)
1517 
1518 
1519 typedef struct _CONFIG_PAGE_SCSI_PORT_1
1520 {
1521  CONFIG_PAGE_HEADER Header; /* 00h */
1522  U32 Configuration; /* 04h */
1523  U32 OnBusTimerValue; /* 08h */
1524  U8 TargetConfig; /* 0Ch */
1525  U8 Reserved1; /* 0Dh */
1526  U16 IDConfig; /* 0Eh */
1527 } CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1,
1528  SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t;
1529 
1530 #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03)
1531 
1532 /* Configuration values */
1533 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF)
1534 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000)
1535 #define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID (16)
1536 
1537 /* TargetConfig values */
1538 #define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01)
1539 #define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG (0x02)
1540 
1541 
1542 typedef struct _MPI_DEVICE_INFO
1543 {
1544  U8 Timeout; /* 00h */
1545  U8 SyncFactor; /* 01h */
1546  U16 DeviceFlags; /* 02h */
1547 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO,
1548  MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t;
1549 
1550 typedef struct _CONFIG_PAGE_SCSI_PORT_2
1551 {
1552  CONFIG_PAGE_HEADER Header; /* 00h */
1553  U32 PortFlags; /* 04h */
1554  U32 PortSettings; /* 08h */
1555  MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */
1556 } CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2,
1557  SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t;
1558 
1559 #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x02)
1560 
1561 /* PortFlags values */
1562 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001)
1563 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004)
1564 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
1565 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010)
1566 
1567 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK (0x00000060)
1568 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV (0x00000000)
1569 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020)
1570 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060)
1571 
1572 
1573 /* PortSettings values */
1574 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F)
1575 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030)
1576 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000)
1577 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010)
1578 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020)
1579 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030)
1580 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0)
1581 #define MPI_SCSIPORTPAGE2_PORT_RM_NONE (0x00000000)
1582 #define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY (0x00000040)
1583 #define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA (0x00000080)
1584 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00)
1585 #define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY (8)
1586 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000)
1587 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000)
1588 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000)
1589 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000)
1590 
1591 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001)
1592 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002)
1593 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004)
1594 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008)
1595 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010)
1596 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020)
1597 
1598 
1599 /****************************************************************************
1600 * SCSI Target Device Config Pages
1601 ****************************************************************************/
1602 
1603 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0
1604 {
1605  CONFIG_PAGE_HEADER Header; /* 00h */
1606  U32 NegotiatedParameters; /* 04h */
1607  U32 Information; /* 08h */
1608 } CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0,
1609  SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t;
1610 
1611 #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x04)
1612 
1613 #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001)
1614 #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002)
1615 #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004)
1616 #define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008)
1617 #define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010)
1618 #define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020)
1619 #define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040)
1620 #define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080)
1621 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00)
1622 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD (8)
1623 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000)
1624 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET (16)
1625 #define MPI_SCSIDEVPAGE0_NP_IDP (0x08000000)
1626 #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000)
1627 #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000)
1628 
1629 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001)
1630 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002)
1631 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004)
1632 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008)
1633 
1634 
1635 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1
1636 {
1637  CONFIG_PAGE_HEADER Header; /* 00h */
1638  U32 RequestedParameters; /* 04h */
1639  U32 Reserved; /* 08h */
1640  U32 Configuration; /* 0Ch */
1641 } CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1,
1642  SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t;
1643 
1644 #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x05)
1645 
1646 #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001)
1647 #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002)
1648 #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004)
1649 #define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008)
1650 #define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010)
1651 #define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020)
1652 #define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040)
1653 #define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080)
1654 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
1655 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD (8)
1656 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
1657 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET (16)
1658 #define MPI_SCSIDEVPAGE1_RP_IDP (0x08000000)
1659 #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000)
1660 #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000)
1661 
1662 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002)
1663 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004)
1664 #define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008)
1665 #define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010)
1666 
1667 
1668 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2
1669 {
1670  CONFIG_PAGE_HEADER Header; /* 00h */
1671  U32 DomainValidation; /* 04h */
1672  U32 ParityPipeSelect; /* 08h */
1673  U32 DataPipeSelect; /* 0Ch */
1674 } CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2,
1675  SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t;
1676 
1677 #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01)
1678 
1679 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010)
1680 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020)
1681 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380)
1682 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00)
1683 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000)
1684 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000)
1685 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000)
1686 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000)
1687 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000)
1688 
1689 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003)
1690 
1691 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003)
1692 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C)
1693 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030)
1694 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0)
1695 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300)
1696 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00)
1697 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000)
1698 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000)
1699 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000)
1700 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000)
1701 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000)
1702 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000)
1703 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000)
1704 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000)
1705 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000)
1706 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000)
1707 
1708 
1709 typedef struct _CONFIG_PAGE_SCSI_DEVICE_3
1710 {
1711  CONFIG_PAGE_HEADER Header; /* 00h */
1712  U16 MsgRejectCount; /* 04h */
1713  U16 PhaseErrorCount; /* 06h */
1714  U16 ParityErrorCount; /* 08h */
1715  U16 Reserved; /* 0Ah */
1716 } CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3,
1717  SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t;
1718 
1719 #define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00)
1720 
1721 #define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE)
1722 #define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF)
1723 
1724 
1725 /****************************************************************************
1726 * FC Port Config Pages
1727 ****************************************************************************/
1728 
1729 typedef struct _CONFIG_PAGE_FC_PORT_0
1730 {
1731  CONFIG_PAGE_HEADER Header; /* 00h */
1732  U32 Flags; /* 04h */
1733  U8 MPIPortNumber; /* 08h */
1734  U8 LinkType; /* 09h */
1735  U8 PortState; /* 0Ah */
1736  U8 Reserved; /* 0Bh */
1737  U32 PortIdentifier; /* 0Ch */
1738  U64 WWNN; /* 10h */
1739  U64 WWPN; /* 18h */
1740  U32 SupportedServiceClass; /* 20h */
1741  U32 SupportedSpeeds; /* 24h */
1742  U32 CurrentSpeed; /* 28h */
1743  U32 MaxFrameSize; /* 2Ch */
1744  U64 FabricWWNN; /* 30h */
1745  U64 FabricWWPN; /* 38h */
1746  U32 DiscoveredPortsCount; /* 40h */
1747  U32 MaxInitiators; /* 44h */
1748  U8 MaxAliasesSupported; /* 48h */
1749  U8 MaxHardAliasesSupported; /* 49h */
1750  U8 NumCurrentAliases; /* 4Ah */
1751  U8 Reserved1; /* 4Bh */
1752 } CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0,
1753  FCPortPage0_t, MPI_POINTER pFCPortPage0_t;
1754 
1755 #define MPI_FCPORTPAGE0_PAGEVERSION (0x02)
1756 
1757 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F)
1758 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR)
1759 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET)
1760 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN)
1761 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR)
1762 
1763 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010)
1764 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020)
1765 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040)
1766 
1767 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00)
1768 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000)
1769 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100)
1770 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200)
1771 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400)
1772 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800)
1773 
1774 #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00)
1775 #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01)
1776 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02)
1777 #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03)
1778 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04)
1779 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05)
1780 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06)
1781 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07)
1782 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08)
1783 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09)
1784 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A)
1785 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B)
1786 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C)
1787 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D)
1788 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E)
1789 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F)
1790 
1791 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */
1792 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */
1793 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */
1794 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */
1795 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */
1796 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */
1797 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */
1798 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */
1799 
1800 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001)
1801 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002)
1802 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004)
1803 
1804 #define MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN (0x00000000) /* (SNIA)HBA_PORTSPEED_UNKNOWN 0 Unknown - transceiver incapable of reporting */
1805 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */
1806 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */
1807 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */
1808 #define MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED (0x00000008) /* (SNIA)HBA_PORTSPEED_4GBIT 8 4 GBit/sec */
1809 
1810 #define MPI_FCPORTPAGE0_CURRENT_SPEED_UKNOWN MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN
1811 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED
1812 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED
1813 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED
1814 #define MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED
1815 #define MPI_FCPORTPAGE0_CURRENT_SPEED_NOT_NEGOTIATED (0x00008000) /* (SNIA)HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) Speed not established */
1816 
1817 
1818 typedef struct _CONFIG_PAGE_FC_PORT_1
1819 {
1820  CONFIG_PAGE_HEADER Header; /* 00h */
1821  U32 Flags; /* 04h */
1822  U64 NoSEEPROMWWNN; /* 08h */
1823  U64 NoSEEPROMWWPN; /* 10h */
1824  U8 HardALPA; /* 18h */
1825  U8 LinkConfig; /* 19h */
1826  U8 TopologyConfig; /* 1Ah */
1827  U8 AltConnector; /* 1Bh */
1828  U8 NumRequestedAliases; /* 1Ch */
1829  U8 RR_TOV; /* 1Dh */
1830  U8 InitiatorDeviceTimeout; /* 1Eh */
1831  U8 InitiatorIoPendTimeout; /* 1Fh */
1832 } CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1,
1833  FCPortPage1_t, MPI_POINTER pFCPortPage1_t;
1834 
1835 #define MPI_FCPORTPAGE1_PAGEVERSION (0x06)
1836 
1837 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000)
1838 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000)
1839 #define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000)
1840 #define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000)
1841 #define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000)
1842 #define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE (0x00400000)
1843 #define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK (0x00200000)
1844 #define MPI_FCPORTPAGE1_FLAGS_TARGET_LARGE_CDB_ENABLE (0x00000080)
1845 #define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070)
1846 #define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG (0x00000008)
1847 #define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO (0x00000004)
1848 #define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002)
1849 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001)
1850 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000)
1851 
1852 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000)
1853 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28)
1854 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1855 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1856 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1857 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1858 
1859 #define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000)
1860 #define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010)
1861 #define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030)
1862 #define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050)
1863 
1864 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF)
1865 
1866 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F)
1867 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00)
1868 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01)
1869 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02)
1870 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03)
1871 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F)
1872 
1873 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F)
1874 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01)
1875 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02)
1876 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F)
1877 
1878 #define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00)
1879 
1880 #define MPI_FCPORTPAGE1_INITIATOR_DEV_TIMEOUT_MASK (0x7F)
1881 #define MPI_FCPORTPAGE1_INITIATOR_DEV_UNIT_16 (0x80)
1882 
1883 
1884 typedef struct _CONFIG_PAGE_FC_PORT_2
1885 {
1886  CONFIG_PAGE_HEADER Header; /* 00h */
1887  U8 NumberActive; /* 04h */
1888  U8 ALPA[127]; /* 05h */
1889 } CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2,
1890  FCPortPage2_t, MPI_POINTER pFCPortPage2_t;
1891 
1892 #define MPI_FCPORTPAGE2_PAGEVERSION (0x01)
1893 
1894 
1895 typedef struct _WWN_FORMAT
1896 {
1897  U64 WWNN; /* 00h */
1898  U64 WWPN; /* 08h */
1899 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT,
1900  WWNFormat, MPI_POINTER pWWNFormat;
1901 
1902 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID
1903 {
1904  WWN_FORMAT WWN;
1905  U32 Did;
1906 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID,
1907  PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t;
1908 
1909 typedef struct _FC_PORT_PERSISTENT
1910 {
1911  FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */
1912  U8 TargetID; /* 10h */
1913  U8 Bus; /* 11h */
1914  U16 Flags; /* 12h */
1915 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT,
1916  PersistentData_t, MPI_POINTER pPersistentData_t;
1917 
1918 #define MPI_PERSISTENT_FLAGS_SHIFT (16)
1919 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001)
1920 #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002)
1921 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004)
1922 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008)
1923 #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080)
1924 
1925 /*
1926  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1927  * one and check Header.PageLength at runtime.
1928  */
1929 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX
1930 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1)
1931 #endif
1932 
1933 typedef struct _CONFIG_PAGE_FC_PORT_3
1934 {
1935  CONFIG_PAGE_HEADER Header; /* 00h */
1936  FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */
1937 } CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3,
1938  FCPortPage3_t, MPI_POINTER pFCPortPage3_t;
1939 
1940 #define MPI_FCPORTPAGE3_PAGEVERSION (0x01)
1941 
1942 
1943 typedef struct _CONFIG_PAGE_FC_PORT_4
1944 {
1945  CONFIG_PAGE_HEADER Header; /* 00h */
1946  U32 PortFlags; /* 04h */
1947  U32 PortSettings; /* 08h */
1948 } CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4,
1949  FCPortPage4_t, MPI_POINTER pFCPortPage4_t;
1950 
1951 #define MPI_FCPORTPAGE4_PAGEVERSION (0x00)
1952 
1953 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
1954 
1955 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030)
1956 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000)
1957 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010)
1958 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020)
1959 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030)
1960 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0)
1961 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00)
1962 
1963 
1964 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO
1965 {
1966  U8 Flags; /* 00h */
1967  U8 AliasAlpa; /* 01h */
1968  U16 Reserved; /* 02h */
1969  U64 AliasWWNN; /* 04h */
1970  U64 AliasWWPN; /* 0Ch */
1971 } CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1972  MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1973  FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t;
1974 
1975 typedef struct _CONFIG_PAGE_FC_PORT_5
1976 {
1977  CONFIG_PAGE_HEADER Header; /* 00h */
1978  CONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */
1979 } CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5,
1980  FCPortPage5_t, MPI_POINTER pFCPortPage5_t;
1981 
1982 #define MPI_FCPORTPAGE5_PAGEVERSION (0x02)
1983 
1984 #define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01)
1985 #define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02)
1986 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04)
1987 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08)
1988 #define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10)
1989 
1990 typedef struct _CONFIG_PAGE_FC_PORT_6
1991 {
1992  CONFIG_PAGE_HEADER Header; /* 00h */
1993  U32 Reserved; /* 04h */
1994  U64 TimeSinceReset; /* 08h */
1995  U64 TxFrames; /* 10h */
1996  U64 RxFrames; /* 18h */
1997  U64 TxWords; /* 20h */
1998  U64 RxWords; /* 28h */
1999  U64 LipCount; /* 30h */
2000  U64 NosCount; /* 38h */
2001  U64 ErrorFrames; /* 40h */
2002  U64 DumpedFrames; /* 48h */
2003  U64 LinkFailureCount; /* 50h */
2004  U64 LossOfSyncCount; /* 58h */
2005  U64 LossOfSignalCount; /* 60h */
2006  U64 PrimativeSeqErrCount; /* 68h */
2007  U64 InvalidTxWordCount; /* 70h */
2008  U64 InvalidCrcCount; /* 78h */
2009  U64 FcpInitiatorIoCount; /* 80h */
2010 } CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6,
2011  FCPortPage6_t, MPI_POINTER pFCPortPage6_t;
2012 
2013 #define MPI_FCPORTPAGE6_PAGEVERSION (0x00)
2014 
2015 
2016 typedef struct _CONFIG_PAGE_FC_PORT_7
2017 {
2018  CONFIG_PAGE_HEADER Header; /* 00h */
2019  U32 Reserved; /* 04h */
2020  U8 PortSymbolicName[256]; /* 08h */
2021 } CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7,
2022  FCPortPage7_t, MPI_POINTER pFCPortPage7_t;
2023 
2024 #define MPI_FCPORTPAGE7_PAGEVERSION (0x00)
2025 
2026 
2027 typedef struct _CONFIG_PAGE_FC_PORT_8
2028 {
2029  CONFIG_PAGE_HEADER Header; /* 00h */
2030  U32 BitVector[8]; /* 04h */
2031 } CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8,
2032  FCPortPage8_t, MPI_POINTER pFCPortPage8_t;
2033 
2034 #define MPI_FCPORTPAGE8_PAGEVERSION (0x00)
2035 
2036 
2037 typedef struct _CONFIG_PAGE_FC_PORT_9
2038 {
2039  CONFIG_PAGE_HEADER Header; /* 00h */
2040  U32 Reserved; /* 04h */
2041  U64 GlobalWWPN; /* 08h */
2042  U64 GlobalWWNN; /* 10h */
2043  U32 UnitType; /* 18h */
2044  U32 PhysicalPortNumber; /* 1Ch */
2045  U32 NumAttachedNodes; /* 20h */
2046  U16 IPVersion; /* 24h */
2047  U16 UDPPortNumber; /* 26h */
2048  U8 IPAddress[16]; /* 28h */
2049  U16 Reserved1; /* 38h */
2050  U16 TopologyDiscoveryFlags; /* 3Ah */
2051 } CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9,
2052  FCPortPage9_t, MPI_POINTER pFCPortPage9_t;
2053 
2054 #define MPI_FCPORTPAGE9_PAGEVERSION (0x00)
2055 
2056 
2057 typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA
2058 {
2059  U8 Id; /* 10h */
2060  U8 ExtId; /* 11h */
2061  U8 Connector; /* 12h */
2062  U8 Transceiver[8]; /* 13h */
2063  U8 Encoding; /* 1Bh */
2064  U8 BitRate_100mbs; /* 1Ch */
2065  U8 Reserved1; /* 1Dh */
2066  U8 Length9u_km; /* 1Eh */
2067  U8 Length9u_100m; /* 1Fh */
2068  U8 Length50u_10m; /* 20h */
2069  U8 Length62p5u_10m; /* 21h */
2070  U8 LengthCopper_m; /* 22h */
2071  U8 Reseverved2; /* 22h */
2072  U8 VendorName[16]; /* 24h */
2073  U8 Reserved3; /* 34h */
2074  U8 VendorOUI[3]; /* 35h */
2075  U8 VendorPN[16]; /* 38h */
2076  U8 VendorRev[4]; /* 48h */
2077  U16 Wavelength; /* 4Ch */
2078  U8 Reserved4; /* 4Eh */
2079  U8 CC_BASE; /* 4Fh */
2080 } CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
2081  MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
2082  FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t;
2083 
2084 #define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00)
2085 #define MPI_FCPORT10_BASE_ID_GBIC (0x01)
2086 #define MPI_FCPORT10_BASE_ID_FIXED (0x02)
2087 #define MPI_FCPORT10_BASE_ID_SFP (0x03)
2088 #define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04)
2089 #define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F)
2090 #define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80)
2091 
2092 #define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00)
2093 #define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01)
2094 #define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02)
2095 #define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03)
2096 #define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04)
2097 #define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05)
2098 #define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06)
2099 #define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07)
2100 #define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80)
2101 
2102 #define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00)
2103 #define MPI_FCPORT10_BASE_CONN_SC (0x01)
2104 #define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02)
2105 #define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03)
2106 #define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04)
2107 #define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05)
2108 #define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06)
2109 #define MPI_FCPORT10_BASE_CONN_LC (0x07)
2110 #define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08)
2111 #define MPI_FCPORT10_BASE_CONN_MU (0x09)
2112 #define MPI_FCPORT10_BASE_CONN_SG (0x0A)
2113 #define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B)
2114 #define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C)
2115 #define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F)
2116 #define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20)
2117 #define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21)
2118 #define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22)
2119 #define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F)
2120 #define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80)
2121 
2122 #define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00)
2123 #define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01)
2124 #define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02)
2125 #define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03)
2126 #define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04)
2127 
2128 
2129 typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA
2130 {
2131  U8 Options[2]; /* 50h */
2132  U8 BitRateMax; /* 52h */
2133  U8 BitRateMin; /* 53h */
2134  U8 VendorSN[16]; /* 54h */
2135  U8 DateCode[8]; /* 64h */
2136  U8 DiagMonitoringType; /* 6Ch */
2137  U8 EnhancedOptions; /* 6Dh */
2138  U8 SFF8472Compliance; /* 6Eh */
2139  U8 CC_EXT; /* 6Fh */
2140 } CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
2141  MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
2142  FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t;
2143 
2144 #define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20)
2145 #define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10)
2146 #define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08)
2147 #define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04)
2148 #define MPI_FCPORT10_EXT_OPTION1_LOS (0x02)
2149 
2150 
2151 typedef struct _CONFIG_PAGE_FC_PORT_10
2152 {
2153  CONFIG_PAGE_HEADER Header; /* 00h */
2154  U8 Flags; /* 04h */
2155  U8 Reserved1; /* 05h */
2156  U16 Reserved2; /* 06h */
2157  U32 HwConfig1; /* 08h */
2158  U32 HwConfig2; /* 0Ch */
2159  CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */
2160  CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */
2161  U8 VendorSpecific[32]; /* 70h */
2162 } CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10,
2163  FCPortPage10_t, MPI_POINTER pFCPortPage10_t;
2164 
2165 #define MPI_FCPORTPAGE10_PAGEVERSION (0x01)
2166 
2167 /* standard MODDEF pin definitions (from GBIC spec.) */
2168 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007)
2169 #define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001)
2170 #define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002)
2171 #define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004)
2172 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007)
2173 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006)
2174 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005)
2175 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004)
2176 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003)
2177 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002)
2178 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001)
2179 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000)
2180 
2181 #define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010)
2182 #define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020)
2183 
2184 
2185 /****************************************************************************
2186 * FC Device Config Pages
2187 ****************************************************************************/
2188 
2189 typedef struct _CONFIG_PAGE_FC_DEVICE_0
2190 {
2191  CONFIG_PAGE_HEADER Header; /* 00h */
2192  U64 WWNN; /* 04h */
2193  U64 WWPN; /* 0Ch */
2194  U32 PortIdentifier; /* 14h */
2195  U8 Protocol; /* 18h */
2196  U8 Flags; /* 19h */
2197  U16 BBCredit; /* 1Ah */
2198  U16 MaxRxFrameSize; /* 1Ch */
2199  U8 ADISCHardALPA; /* 1Eh */
2200  U8 PortNumber; /* 1Fh */
2201  U8 FcPhLowestVersion; /* 20h */
2202  U8 FcPhHighestVersion; /* 21h */
2203  U8 CurrentTargetID; /* 22h */
2204  U8 CurrentBus; /* 23h */
2205 } CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0,
2206  FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t;
2207 
2208 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x03)
2209 
2210 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01)
2211 #define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02)
2212 #define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04)
2213 
2214 #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01)
2215 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02)
2216 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04)
2217 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY (0x08)
2218 
2219 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK)
2220 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK)
2221 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
2222 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID)
2223 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK)
2224 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK)
2225 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT)
2226 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK)
2227 
2228 #define MPI_FC_DEVICE_PAGE0_HARD_ALPA_UNKNOWN (0xFF)
2229 
2230 /****************************************************************************
2231 * RAID Volume Config Pages
2232 ****************************************************************************/
2233 
2234 typedef struct _RAID_VOL0_PHYS_DISK
2235 {
2236  U16 Reserved; /* 00h */
2237  U8 PhysDiskMap; /* 02h */
2238  U8 PhysDiskNum; /* 03h */
2239 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK,
2240  RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t;
2241 
2242 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
2243 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
2244 
2245 typedef struct _RAID_VOL0_STATUS
2246 {
2247  U8 Flags; /* 00h */
2248  U8 State; /* 01h */
2249  U16 Reserved; /* 02h */
2250 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS,
2251  RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t;
2252 
2253 /* RAID Volume Page 0 VolumeStatus defines */
2254 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01)
2255 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02)
2256 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04)
2257 #define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08)
2258 #define MPI_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x10)
2259 
2260 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00)
2261 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01)
2262 #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02)
2263 #define MPI_RAIDVOL0_STATUS_STATE_MISSING (0x03)
2264 
2265 typedef struct _RAID_VOL0_SETTINGS
2266 {
2267  U16 Settings; /* 00h */
2268  U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */
2269  U8 Reserved; /* 02h */
2270 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS,
2271  RaidVol0Settings, MPI_POINTER pRaidVol0Settings;
2272 
2273 /* RAID Volume Page 0 VolumeSettings defines */
2274 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001)
2275 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002)
2276 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004)
2277 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008)
2278 #define MPI_RAIDVOL0_SETTING_FAST_DATA_SCRUBBING_0102 (0x0020) /* obsolete */
2279 
2280 #define MPI_RAIDVOL0_SETTING_MASK_METADATA_SIZE (0x00C0)
2281 #define MPI_RAIDVOL0_SETTING_64MB_METADATA_SIZE (0x0000)
2282 #define MPI_RAIDVOL0_SETTING_512MB_METADATA_SIZE (0x0040)
2283 
2284 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010)
2285 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000)
2286 
2287 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
2288 #define MPI_RAID_HOT_SPARE_POOL_0 (0x01)
2289 #define MPI_RAID_HOT_SPARE_POOL_1 (0x02)
2290 #define MPI_RAID_HOT_SPARE_POOL_2 (0x04)
2291 #define MPI_RAID_HOT_SPARE_POOL_3 (0x08)
2292 #define MPI_RAID_HOT_SPARE_POOL_4 (0x10)
2293 #define MPI_RAID_HOT_SPARE_POOL_5 (0x20)
2294 #define MPI_RAID_HOT_SPARE_POOL_6 (0x40)
2295 #define MPI_RAID_HOT_SPARE_POOL_7 (0x80)
2296 
2297 /*
2298  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2299  * one and check Header.PageLength at runtime.
2300  */
2301 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX
2302 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
2303 #endif
2304 
2305 typedef struct _CONFIG_PAGE_RAID_VOL_0
2306 {
2307  CONFIG_PAGE_HEADER Header; /* 00h */
2308  U8 VolumeID; /* 04h */
2309  U8 VolumeBus; /* 05h */
2310  U8 VolumeIOC; /* 06h */
2311  U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */
2312  RAID_VOL0_STATUS VolumeStatus; /* 08h */
2313  RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */
2314  U32 MaxLBA; /* 10h */
2315  U32 MaxLBAHigh; /* 14h */
2316  U32 StripeSize; /* 18h */
2317  U32 Reserved2; /* 1Ch */
2318  U32 Reserved3; /* 20h */
2319  U8 NumPhysDisks; /* 24h */
2320  U8 DataScrubRate; /* 25h */
2321  U8 ResyncRate; /* 26h */
2322  U8 InactiveStatus; /* 27h */
2323  RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */
2324 } CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0,
2325  RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t;
2326 
2327 #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x07)
2328 
2329 /* values for RAID Volume Page 0 InactiveStatus field */
2330 #define MPI_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
2331 #define MPI_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
2332 #define MPI_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
2333 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
2334 #define MPI_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
2335 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
2336 #define MPI_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
2337 
2338 
2339 typedef struct _CONFIG_PAGE_RAID_VOL_1
2340 {
2341  CONFIG_PAGE_HEADER Header; /* 00h */
2342  U8 VolumeID; /* 04h */
2343  U8 VolumeBus; /* 05h */
2344  U8 VolumeIOC; /* 06h */
2345  U8 Reserved0; /* 07h */
2346  U8 GUID[24]; /* 08h */
2347  U8 Name[32]; /* 20h */
2348  U64 WWID; /* 40h */
2349  U32 Reserved1; /* 48h */
2350  U32 Reserved2; /* 4Ch */
2351 } CONFIG_PAGE_RAID_VOL_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_1,
2352  RaidVolumePage1_t, MPI_POINTER pRaidVolumePage1_t;
2353 
2354 #define MPI_RAIDVOLPAGE1_PAGEVERSION (0x01)
2355 
2356 
2357 /****************************************************************************
2358 * RAID Physical Disk Config Pages
2359 ****************************************************************************/
2360 
2361 typedef struct _RAID_PHYS_DISK0_ERROR_DATA
2362 {
2363  U8 ErrorCdbByte; /* 00h */
2364  U8 ErrorSenseKey; /* 01h */
2365  U16 Reserved; /* 02h */
2366  U16 ErrorCount; /* 04h */
2367  U8 ErrorASC; /* 06h */
2368  U8 ErrorASCQ; /* 07h */
2369  U16 SmartCount; /* 08h */
2370  U8 SmartASC; /* 0Ah */
2371  U8 SmartASCQ; /* 0Bh */
2372 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA,
2373  RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t;
2374 
2375 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA
2376 {
2377  U8 VendorID[8]; /* 00h */
2378  U8 ProductID[16]; /* 08h */
2379  U8 ProductRevLevel[4]; /* 18h */
2380  U8 Info[32]; /* 1Ch */
2381 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA,
2382  RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData;
2383 
2384 typedef struct _RAID_PHYS_DISK0_SETTINGS
2385 {
2386  U8 SepID; /* 00h */
2387  U8 SepBus; /* 01h */
2388  U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */
2389  U8 PhysDiskSettings; /* 03h */
2390 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS,
2391  RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t;
2392 
2393 typedef struct _RAID_PHYS_DISK0_STATUS
2394 {
2395  U8 Flags; /* 00h */
2396  U8 State; /* 01h */
2397  U16 Reserved; /* 02h */
2398 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS,
2399  RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t;
2400 
2401 /* RAID Physical Disk PhysDiskStatus flags */
2402 
2403 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01)
2404 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02)
2405 #define MPI_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x04)
2406 #define MPI_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00)
2407 #define MPI_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x08)
2408 
2409 #define MPI_PHYSDISK0_STATUS_ONLINE (0x00)
2410 #define MPI_PHYSDISK0_STATUS_MISSING (0x01)
2411 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02)
2412 #define MPI_PHYSDISK0_STATUS_FAILED (0x03)
2413 #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04)
2414 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05)
2415 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06)
2416 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF)
2417 
2418 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0
2419 {
2420  CONFIG_PAGE_HEADER Header; /* 00h */
2421  U8 PhysDiskID; /* 04h */
2422  U8 PhysDiskBus; /* 05h */
2423  U8 PhysDiskIOC; /* 06h */
2424  U8 PhysDiskNum; /* 07h */
2425  RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */
2426  U32 Reserved1; /* 0Ch */
2427  U8 ExtDiskIdentifier[8]; /* 10h */
2428  U8 DiskIdentifier[16]; /* 18h */
2429  RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */
2430  RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */
2431  U32 MaxLBA; /* 68h */
2432  RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */
2433 } CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0,
2434  RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t;
2435 
2436 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x02)
2437 
2438 
2439 typedef struct _RAID_PHYS_DISK1_PATH
2440 {
2441  U8 PhysDiskID; /* 00h */
2442  U8 PhysDiskBus; /* 01h */
2443  U16 Reserved1; /* 02h */
2444  U64 WWID; /* 04h */
2445  U64 OwnerWWID; /* 0Ch */
2446  U8 OwnerIdentifier; /* 14h */
2447  U8 Reserved2; /* 15h */
2448  U16 Flags; /* 16h */
2449 } RAID_PHYS_DISK1_PATH, MPI_POINTER PTR_RAID_PHYS_DISK1_PATH,
2450  RaidPhysDisk1Path_t, MPI_POINTER pRaidPhysDisk1Path_t;
2451 
2452 /* RAID Physical Disk Page 1 Flags field defines */
2453 #define MPI_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
2454 #define MPI_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
2455 
2456 
2457 /*
2458  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2459  * one and check Header.PageLength or NumPhysDiskPaths at runtime.
2460  */
2461 #ifndef MPI_RAID_PHYS_DISK1_PATH_MAX
2462 #define MPI_RAID_PHYS_DISK1_PATH_MAX (1)
2463 #endif
2464 
2465 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_1
2466 {
2467  CONFIG_PAGE_HEADER Header; /* 00h */
2468  U8 NumPhysDiskPaths; /* 04h */
2469  U8 PhysDiskNum; /* 05h */
2470  U16 Reserved2; /* 06h */
2471  U32 Reserved1; /* 08h */
2472  RAID_PHYS_DISK1_PATH Path[MPI_RAID_PHYS_DISK1_PATH_MAX];/* 0Ch */
2473 } CONFIG_PAGE_RAID_PHYS_DISK_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_1,
2474  RaidPhysDiskPage1_t, MPI_POINTER pRaidPhysDiskPage1_t;
2475 
2476 #define MPI_RAIDPHYSDISKPAGE1_PAGEVERSION (0x00)
2477 
2478 
2479 /****************************************************************************
2480 * LAN Config Pages
2481 ****************************************************************************/
2482 
2483 typedef struct _CONFIG_PAGE_LAN_0
2484 {
2485  ConfigPageHeader_t Header; /* 00h */
2486  U16 TxRxModes; /* 04h */
2487  U16 Reserved; /* 06h */
2488  U32 PacketPrePad; /* 08h */
2489 } CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0,
2490  LANPage0_t, MPI_POINTER pLANPage0_t;
2491 
2492 #define MPI_LAN_PAGE0_PAGEVERSION (0x01)
2493 
2494 #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000)
2495 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001)
2496 #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001)
2497 
2498 typedef struct _CONFIG_PAGE_LAN_1
2499 {
2500  ConfigPageHeader_t Header; /* 00h */
2501  U16 Reserved; /* 04h */
2502  U8 CurrentDeviceState; /* 06h */
2503  U8 Reserved1; /* 07h */
2504  U32 MinPacketSize; /* 08h */
2505  U32 MaxPacketSize; /* 0Ch */
2506  U32 HardwareAddressLow; /* 10h */
2507  U32 HardwareAddressHigh; /* 14h */
2508  U32 MaxWireSpeedLow; /* 18h */
2509  U32 MaxWireSpeedHigh; /* 1Ch */
2510  U32 BucketsRemaining; /* 20h */
2511  U32 MaxReplySize; /* 24h */
2512  U32 NegWireSpeedLow; /* 28h */
2513  U32 NegWireSpeedHigh; /* 2Ch */
2514 } CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1,
2515  LANPage1_t, MPI_POINTER pLANPage1_t;
2516 
2517 #define MPI_LAN_PAGE1_PAGEVERSION (0x03)
2518 
2519 #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00)
2520 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01)
2521 
2522 
2523 /****************************************************************************
2524 * Inband Config Pages
2525 ****************************************************************************/
2526 
2527 typedef struct _CONFIG_PAGE_INBAND_0
2528 {
2529  CONFIG_PAGE_HEADER Header; /* 00h */
2530  MPI_VERSION_FORMAT InbandVersion; /* 04h */
2531  U16 MaximumBuffers; /* 08h */
2532  U16 Reserved1; /* 0Ah */
2533 } CONFIG_PAGE_INBAND_0, MPI_POINTER PTR_CONFIG_PAGE_INBAND_0,
2534  InbandPage0_t, MPI_POINTER pInbandPage0_t;
2535 
2536 #define MPI_INBAND_PAGEVERSION (0x00)
2537 
2538 
2539 
2540 /****************************************************************************
2541 * SAS IO Unit Config Pages
2542 ****************************************************************************/
2543 
2544 typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA
2545 {
2546  U8 Port; /* 00h */
2547  U8 PortFlags; /* 01h */
2548  U8 PhyFlags; /* 02h */
2549  U8 NegotiatedLinkRate; /* 03h */
2550  U32 ControllerPhyDeviceInfo;/* 04h */
2551  U16 AttachedDeviceHandle; /* 08h */
2552  U16 ControllerDevHandle; /* 0Ah */
2553  U32 DiscoveryStatus; /* 0Ch */
2554 } MPI_SAS_IO_UNIT0_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT0_PHY_DATA,
2555  SasIOUnit0PhyData, MPI_POINTER pSasIOUnit0PhyData;
2556 
2557 /*
2558  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2559  * one and check Header.PageLength at runtime.
2560  */
2561 #ifndef MPI_SAS_IOUNIT0_PHY_MAX
2562 #define MPI_SAS_IOUNIT0_PHY_MAX (1)
2563 #endif
2564 
2565 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_0
2566 {
2567  CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2568  U16 NvdataVersionDefault; /* 08h */
2569  U16 NvdataVersionPersistent; /* 0Ah */
2570  U8 NumPhys; /* 0Ch */
2571  U8 Reserved2; /* 0Dh */
2572  U16 Reserved3; /* 0Eh */
2573  MPI_SAS_IO_UNIT0_PHY_DATA PhyData[MPI_SAS_IOUNIT0_PHY_MAX]; /* 10h */
2574 } CONFIG_PAGE_SAS_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_0,
2575  SasIOUnitPage0_t, MPI_POINTER pSasIOUnitPage0_t;
2576 
2577 #define MPI_SASIOUNITPAGE0_PAGEVERSION (0x04)
2578 
2579 /* values for SAS IO Unit Page 0 PortFlags */
2580 #define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS (0x08)
2581 #define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)
2582 #define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)
2583 #define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2584 
2585 /* values for SAS IO Unit Page 0 PhyFlags */
2586 #define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED (0x04)
2587 #define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT (0x02)
2588 #define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT (0x01)
2589 
2590 /* values for SAS IO Unit Page 0 NegotiatedLinkRate */
2591 #define MPI_SAS_IOUNIT0_RATE_UNKNOWN (0x00)
2592 #define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED (0x01)
2593 #define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION (0x02)
2594 #define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE (0x03)
2595 #define MPI_SAS_IOUNIT0_RATE_1_5 (0x08)
2596 #define MPI_SAS_IOUNIT0_RATE_3_0 (0x09)
2597 #define MPI_SAS_IOUNIT0_RATE_6_0 (0x0A)
2598 
2599 /* see mpi_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
2600 
2601 /* values for SAS IO Unit Page 0 DiscoveryStatus */
2602 #define MPI_SAS_IOUNIT0_DS_LOOP_DETECTED (0x00000001)
2603 #define MPI_SAS_IOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2604 #define MPI_SAS_IOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
2605 #define MPI_SAS_IOUNIT0_DS_EXPANDER_ERR (0x00000008)
2606 #define MPI_SAS_IOUNIT0_DS_SMP_TIMEOUT (0x00000010)
2607 #define MPI_SAS_IOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2608 #define MPI_SAS_IOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
2609 #define MPI_SAS_IOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
2610 #define MPI_SAS_IOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
2611 #define MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
2612 #define MPI_SAS_IOUNIT0_DS_TABLE_LINK (0x00000400)
2613 #define MPI_SAS_IOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
2614 #define MPI_SAS_IOUNIT0_DS_MAX_SATA_TARGETS (0x00001000)
2615 #define MPI_SAS_IOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
2616 
2617 
2618 typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA
2619 {
2620  U8 Port; /* 00h */
2621  U8 PortFlags; /* 01h */
2622  U8 PhyFlags; /* 02h */
2623  U8 MaxMinLinkRate; /* 03h */
2624  U32 ControllerPhyDeviceInfo; /* 04h */
2625  U16 MaxTargetPortConnectTime; /* 08h */
2626  U16 Reserved1; /* 0Ah */
2627 } MPI_SAS_IO_UNIT1_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT1_PHY_DATA,
2628  SasIOUnit1PhyData, MPI_POINTER pSasIOUnit1PhyData;
2629 
2630 /*
2631  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2632  * one and check Header.PageLength at runtime.
2633  */
2634 #ifndef MPI_SAS_IOUNIT1_PHY_MAX
2635 #define MPI_SAS_IOUNIT1_PHY_MAX (1)
2636 #endif
2637 
2638 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_1
2639 {
2640  CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2641  U16 ControlFlags; /* 08h */
2642  U16 MaxNumSATATargets; /* 0Ah */
2643  U16 AdditionalControlFlags; /* 0Ch */
2644  U16 Reserved1; /* 0Eh */
2645  U8 NumPhys; /* 10h */
2646  U8 SATAMaxQDepth; /* 11h */
2647  U8 ReportDeviceMissingDelay; /* 12h */
2648  U8 IODeviceMissingDelay; /* 13h */
2649  MPI_SAS_IO_UNIT1_PHY_DATA PhyData[MPI_SAS_IOUNIT1_PHY_MAX]; /* 14h */
2650 } CONFIG_PAGE_SAS_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_1,
2651  SasIOUnitPage1_t, MPI_POINTER pSasIOUnitPage1_t;
2652 
2653 #define MPI_SASIOUNITPAGE1_PAGEVERSION (0x07)
2654 
2655 /* values for SAS IO Unit Page 1 ControlFlags */
2656 #define MPI_SAS_IOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
2657 #define MPI_SAS_IOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
2658 #define MPI_SAS_IOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
2659 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
2660 #define MPI_SAS_IOUNIT1_CONTROL_DISABLE_SAS_HASH (0x0800)
2661 
2662 #define MPI_SAS_IOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
2663 #define MPI_SAS_IOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
2664 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x00)
2665 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x01)
2666 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x02)
2667 
2668 #define MPI_SAS_IOUNIT1_CONTROL_POSTPONE_SATA_INIT (0x0100)
2669 #define MPI_SAS_IOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
2670 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
2671 #define MPI_SAS_IOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
2672 #define MPI_SAS_IOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
2673 #define MPI_SAS_IOUNIT1_CONTROL_PHY_ENABLE_ORDER_HIGH (0x0008)
2674 #define MPI_SAS_IOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
2675 #define MPI_SAS_IOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
2676 #define MPI_SAS_IOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
2677 
2678 /* values for SAS IO Unit Page 1 AdditionalControlFlags */
2679 #define MPI_SAS_IOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
2680 #define MPI_SAS_IOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
2681 #define MPI_SAS_IOUNIT1_ACONTROL_HIDE_NONZERO_ATTACHED_PHY_IDENT (0x0020)
2682 #define MPI_SAS_IOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
2683 #define MPI_SAS_IOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
2684 #define MPI_SAS_IOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
2685 #define MPI_SAS_IOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
2686 #define MPI_SAS_IOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
2687 
2688 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2689 #define MPI_SAS_IOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
2690 #define MPI_SAS_IOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
2691 
2692 /* values for SAS IO Unit Page 1 PortFlags */
2693 #define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)
2694 #define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)
2695 #define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2696 
2697 /* values for SAS IO Unit Page 0 PhyFlags */
2698 #define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE (0x04)
2699 #define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT (0x02)
2700 #define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT (0x01)
2701 
2702 /* values for SAS IO Unit Page 0 MaxMinLinkRate */
2703 #define MPI_SAS_IOUNIT1_MAX_RATE_MASK (0xF0)
2704 #define MPI_SAS_IOUNIT1_MAX_RATE_1_5 (0x80)
2705 #define MPI_SAS_IOUNIT1_MAX_RATE_3_0 (0x90)
2706 #define MPI_SAS_IOUNIT1_MIN_RATE_MASK (0x0F)
2707 #define MPI_SAS_IOUNIT1_MIN_RATE_1_5 (0x08)
2708 #define MPI_SAS_IOUNIT1_MIN_RATE_3_0 (0x09)
2709 
2710 /* see mpi_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2711 
2712 
2713 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_2
2714 {
2715  CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2716  U8 NumDevsPerEnclosure; /* 08h */
2717  U8 Reserved1; /* 09h */
2718  U16 Reserved2; /* 0Ah */
2719  U16 MaxPersistentIDs; /* 0Ch */
2720  U16 NumPersistentIDsUsed; /* 0Eh */
2721  U8 Status; /* 10h */
2722  U8 Flags; /* 11h */
2723  U16 MaxNumPhysicalMappedIDs;/* 12h */
2724 } CONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2,
2725  SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t;
2726 
2727 #define MPI_SASIOUNITPAGE2_PAGEVERSION (0x06)
2728 
2729 /* values for SAS IO Unit Page 2 Status field */
2730 #define MPI_SAS_IOUNIT2_STATUS_DEVICE_LIMIT_EXCEEDED (0x08)
2731 #define MPI_SAS_IOUNIT2_STATUS_ENCLOSURE_DEVICES_UNMAPPED (0x04)
2732 #define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS (0x02)
2733 #define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS (0x01)
2734 
2735 /* values for SAS IO Unit Page 2 Flags field */
2736 #define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS (0x01)
2737 /* Physical Mapping Modes */
2738 #define MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE (0x0E)
2739 #define MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE (1)
2740 #define MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP (0x00)
2741 #define MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP (0x01)
2742 #define MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP (0x02)
2743 #define MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP (0x07)
2744 
2745 #define MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT (0x10)
2746 #define MPI_SAS_IOUNIT2_FLAGS_DA_STARTING_SLOT (0x20)
2747 
2748 
2749 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_3
2750 {
2751  CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2752  U32 Reserved1; /* 08h */
2753  U32 MaxInvalidDwordCount; /* 0Ch */
2754  U32 InvalidDwordCountTime; /* 10h */
2755  U32 MaxRunningDisparityErrorCount; /* 14h */
2756  U32 RunningDisparityErrorTime; /* 18h */
2757  U32 MaxLossDwordSynchCount; /* 1Ch */
2758  U32 LossDwordSynchCountTime; /* 20h */
2759  U32 MaxPhyResetProblemCount; /* 24h */
2760  U32 PhyResetProblemTime; /* 28h */
2761 } CONFIG_PAGE_SAS_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_3,
2762  SasIOUnitPage3_t, MPI_POINTER pSasIOUnitPage3_t;
2763 
2764 #define MPI_SASIOUNITPAGE3_PAGEVERSION (0x00)
2765 
2766 
2767 /****************************************************************************
2768 * SAS Expander Config Pages
2769 ****************************************************************************/
2770 
2771 typedef struct _CONFIG_PAGE_SAS_EXPANDER_0
2772 {
2773  CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2774  U8 PhysicalPort; /* 08h */
2775  U8 Reserved1; /* 09h */
2776  U16 EnclosureHandle; /* 0Ah */
2777  U64 SASAddress; /* 0Ch */
2778  U32 DiscoveryStatus; /* 14h */
2779  U16 DevHandle; /* 18h */
2780  U16 ParentDevHandle; /* 1Ah */
2781  U16 ExpanderChangeCount; /* 1Ch */
2782  U16 ExpanderRouteIndexes; /* 1Eh */
2783  U8 NumPhys; /* 20h */
2784  U8 SASLevel; /* 21h */
2785  U8 Flags; /* 22h */
2786  U8 Reserved3; /* 23h */
2787 } CONFIG_PAGE_SAS_EXPANDER_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_0,
2788  SasExpanderPage0_t, MPI_POINTER pSasExpanderPage0_t;
2789 
2790 #define MPI_SASEXPANDER0_PAGEVERSION (0x03)
2791 
2792 /* values for SAS Expander Page 0 DiscoveryStatus field */
2793 #define MPI_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2794 #define MPI_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2795 #define MPI_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2796 #define MPI_SAS_EXPANDER0_DS_EXPANDER_ERR (0x00000008)
2797 #define MPI_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2798 #define MPI_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2799 #define MPI_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2800 #define MPI_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2801 #define MPI_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2802 #define MPI_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2803 #define MPI_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2804 #define MPI_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2805 
2806 /* values for SAS Expander Page 0 Flags field */
2807 #define MPI_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x04)
2808 #define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x02)
2809 #define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x01)
2810 
2811 
2812 typedef struct _CONFIG_PAGE_SAS_EXPANDER_1
2813 {
2814  CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2815  U8 PhysicalPort; /* 08h */
2816  U8 Reserved1; /* 09h */
2817  U16 Reserved2; /* 0Ah */
2818  U8 NumPhys; /* 0Ch */
2819  U8 Phy; /* 0Dh */
2820  U16 NumTableEntriesProgrammed; /* 0Eh */
2821  U8 ProgrammedLinkRate; /* 10h */
2822  U8 HwLinkRate; /* 11h */
2823  U16 AttachedDevHandle; /* 12h */
2824  U32 PhyInfo; /* 14h */
2825  U32 AttachedDeviceInfo; /* 18h */
2826  U16 OwnerDevHandle; /* 1Ch */
2827  U8 ChangeCount; /* 1Eh */
2828  U8 NegotiatedLinkRate; /* 1Fh */
2829  U8 PhyIdentifier; /* 20h */
2830  U8 AttachedPhyIdentifier; /* 21h */
2831  U8 Reserved3; /* 22h */
2832  U8 DiscoveryInfo; /* 23h */
2833  U32 Reserved4; /* 24h */
2834 } CONFIG_PAGE_SAS_EXPANDER_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_1,
2835  SasExpanderPage1_t, MPI_POINTER pSasExpanderPage1_t;
2836 
2837 #define MPI_SASEXPANDER1_PAGEVERSION (0x01)
2838 
2839 /* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */
2840 
2841 /* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */
2842 
2843 /* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */
2844 
2845 /* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */
2846 
2847 /* values for SAS Expander Page 1 DiscoveryInfo field */
2848 #define MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2849 #define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2850 #define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2851 
2852 /* values for SAS Expander Page 1 NegotiatedLinkRate field */
2853 #define MPI_SAS_EXPANDER1_NEG_RATE_UNKNOWN (0x00)
2854 #define MPI_SAS_EXPANDER1_NEG_RATE_PHY_DISABLED (0x01)
2855 #define MPI_SAS_EXPANDER1_NEG_RATE_FAILED_NEGOTIATION (0x02)
2856 #define MPI_SAS_EXPANDER1_NEG_RATE_SATA_OOB_COMPLETE (0x03)
2857 #define MPI_SAS_EXPANDER1_NEG_RATE_1_5 (0x08)
2858 #define MPI_SAS_EXPANDER1_NEG_RATE_3_0 (0x09)
2859 
2860 
2861 /****************************************************************************
2862 * SAS Device Config Pages
2863 ****************************************************************************/
2864 
2865 typedef struct _CONFIG_PAGE_SAS_DEVICE_0
2866 {
2867  CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2868  U16 Slot; /* 08h */
2869  U16 EnclosureHandle; /* 0Ah */
2870  U64 SASAddress; /* 0Ch */
2871  U16 ParentDevHandle; /* 14h */
2872  U8 PhyNum; /* 16h */
2873  U8 AccessStatus; /* 17h */
2874  U16 DevHandle; /* 18h */
2875  U8 TargetID; /* 1Ah */
2876  U8 Bus; /* 1Bh */
2877  U32 DeviceInfo; /* 1Ch */
2878  U16 Flags; /* 20h */
2879  U8 PhysicalPort; /* 22h */
2880  U8 Reserved2; /* 23h */
2881 } CONFIG_PAGE_SAS_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_0,
2882  SasDevicePage0_t, MPI_POINTER pSasDevicePage0_t;
2883 
2884 #define MPI_SASDEVICE0_PAGEVERSION (0x05)
2885 
2886 /* values for SAS Device Page 0 AccessStatus field */
2887 #define MPI_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2888 #define MPI_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2889 #define MPI_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2890 #define MPI_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2891 #define MPI_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2892 /* specific values for SATA Init failures */
2893 #define MPI_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2894 #define MPI_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2895 #define MPI_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2896 #define MPI_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2897 #define MPI_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2898 #define MPI_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2899 #define MPI_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2900 #define MPI_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2901 #define MPI_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2902 #define MPI_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2903 #define MPI_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2904 
2905 /* values for SAS Device Page 0 Flags field */
2906 #define MPI_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2907 #define MPI_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2908 #define MPI_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2909 #define MPI_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2910 #define MPI_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2911 #define MPI_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2912 #define MPI_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2913 #define MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2914 #define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT (0x0004)
2915 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED (0x0002)
2916 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2917 
2918 /* see mpi_sas.h for values for SAS Device Page 0 DeviceInfo values */
2919 
2920 
2921 typedef struct _CONFIG_PAGE_SAS_DEVICE_1
2922 {
2923  CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2924  U32 Reserved1; /* 08h */
2925  U64 SASAddress; /* 0Ch */
2926  U32 Reserved2; /* 14h */
2927  U16 DevHandle; /* 18h */
2928  U8 TargetID; /* 1Ah */
2929  U8 Bus; /* 1Bh */
2930  U8 InitialRegDeviceFIS[20];/* 1Ch */
2931 } CONFIG_PAGE_SAS_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_1,
2932  SasDevicePage1_t, MPI_POINTER pSasDevicePage1_t;
2933 
2934 #define MPI_SASDEVICE1_PAGEVERSION (0x00)
2935 
2936 
2937 typedef struct _CONFIG_PAGE_SAS_DEVICE_2
2938 {
2939  CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2940  U64 PhysicalIdentifier; /* 08h */
2941  U32 EnclosureMapping; /* 10h */
2942 } CONFIG_PAGE_SAS_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_2,
2943  SasDevicePage2_t, MPI_POINTER pSasDevicePage2_t;
2944 
2945 #define MPI_SASDEVICE2_PAGEVERSION (0x01)
2946 
2947 /* defines for SAS Device Page 2 EnclosureMapping field */
2948 #define MPI_SASDEVICE2_ENC_MAP_MASK_MISSING_COUNT (0x0000000F)
2949 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_MISSING_COUNT (0)
2950 #define MPI_SASDEVICE2_ENC_MAP_MASK_NUM_SLOTS (0x000007F0)
2951 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_NUM_SLOTS (4)
2952 #define MPI_SASDEVICE2_ENC_MAP_MASK_START_INDEX (0x001FF800)
2953 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_START_INDEX (11)
2954 
2955 
2956 /****************************************************************************
2957 * SAS PHY Config Pages
2958 ****************************************************************************/
2959 
2960 typedef struct _CONFIG_PAGE_SAS_PHY_0
2961 {
2962  CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2963  U16 OwnerDevHandle; /* 08h */
2964  U16 Reserved1; /* 0Ah */
2965  U64 SASAddress; /* 0Ch */
2966  U16 AttachedDevHandle; /* 14h */
2967  U8 AttachedPhyIdentifier; /* 16h */
2968  U8 Reserved2; /* 17h */
2969  U32 AttachedDeviceInfo; /* 18h */
2970  U8 ProgrammedLinkRate; /* 1Ch */
2971  U8 HwLinkRate; /* 1Dh */
2972  U8 ChangeCount; /* 1Eh */
2973  U8 Flags; /* 1Fh */
2974  U32 PhyInfo; /* 20h */
2975 } CONFIG_PAGE_SAS_PHY_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_0,
2976  SasPhyPage0_t, MPI_POINTER pSasPhyPage0_t;
2977 
2978 #define MPI_SASPHY0_PAGEVERSION (0x01)
2979 
2980 /* values for SAS PHY Page 0 ProgrammedLinkRate field */
2981 #define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK (0xF0)
2982 #define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
2983 #define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5 (0x80)
2984 #define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0 (0x90)
2985 #define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK (0x0F)
2986 #define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
2987 #define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5 (0x08)
2988 #define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0 (0x09)
2989 
2990 /* values for SAS PHY Page 0 HwLinkRate field */
2991 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK (0xF0)
2992 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5 (0x80)
2993 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0 (0x90)
2994 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK (0x0F)
2995 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5 (0x08)
2996 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0 (0x09)
2997 
2998 /* values for SAS PHY Page 0 Flags field */
2999 #define MPI_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
3000 
3001 /* values for SAS PHY Page 0 PhyInfo field */
3002 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
3003 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR (0x00002000)
3004 #define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY (0x00001000)
3005 
3006 #define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
3007 #define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
3008 
3009 #define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
3010 #define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING (0x00000000)
3011 #define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
3012 #define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING (0x00000020)
3013 
3014 #define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE (0x0000000F)
3015 #define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE (0x00000000)
3016 #define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED (0x00000001)
3017 #define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED (0x00000002)
3018 #define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE (0x00000003)
3019 #define MPI_SAS_PHY0_PHYINFO_RATE_1_5 (0x00000008)
3020 #define MPI_SAS_PHY0_PHYINFO_RATE_3_0 (0x00000009)
3021 
3022 
3023 typedef struct _CONFIG_PAGE_SAS_PHY_1
3024 {
3025  CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
3026  U32 Reserved1; /* 08h */
3027  U32 InvalidDwordCount; /* 0Ch */
3028  U32 RunningDisparityErrorCount; /* 10h */
3029  U32 LossDwordSynchCount; /* 14h */
3030  U32 PhyResetProblemCount; /* 18h */
3031 } CONFIG_PAGE_SAS_PHY_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_1,
3032  SasPhyPage1_t, MPI_POINTER pSasPhyPage1_t;
3033 
3034 #define MPI_SASPHY1_PAGEVERSION (0x00)
3035 
3036 
3037 /****************************************************************************
3038 * SAS Enclosure Config Pages
3039 ****************************************************************************/
3040 
3041 typedef struct _CONFIG_PAGE_SAS_ENCLOSURE_0
3042 {
3043  CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
3044  U32 Reserved1; /* 08h */
3045  U64 EnclosureLogicalID; /* 0Ch */
3046  U16 Flags; /* 14h */
3047  U16 EnclosureHandle; /* 16h */
3048  U16 NumSlots; /* 18h */
3049  U16 StartSlot; /* 1Ah */
3050  U8 StartTargetID; /* 1Ch */
3051  U8 StartBus; /* 1Dh */
3052  U8 SEPTargetID; /* 1Eh */
3053  U8 SEPBus; /* 1Fh */
3054  U32 Reserved2; /* 20h */
3055  U32 Reserved3; /* 24h */
3056 } CONFIG_PAGE_SAS_ENCLOSURE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_ENCLOSURE_0,
3057  SasEnclosurePage0_t, MPI_POINTER pSasEnclosurePage0_t;
3058 
3059 #define MPI_SASENCLOSURE0_PAGEVERSION (0x01)
3060 
3061 /* values for SAS Enclosure Page 0 Flags field */
3062 #define MPI_SAS_ENCLS0_FLAGS_SEP_BUS_ID_VALID (0x0020)
3063 #define MPI_SAS_ENCLS0_FLAGS_START_BUS_ID_VALID (0x0010)
3064 
3065 #define MPI_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
3066 #define MPI_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
3067 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
3068 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
3069 #define MPI_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
3070 #define MPI_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
3071 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
3072 
3073 
3074 /****************************************************************************
3075 * Log Config Pages
3076 ****************************************************************************/
3077 /*
3078  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3079  * one and check NumLogEntries at runtime.
3080  */
3081 #ifndef MPI_LOG_0_NUM_LOG_ENTRIES
3082 #define MPI_LOG_0_NUM_LOG_ENTRIES (1)
3083 #endif
3084 
3085 #define MPI_LOG_0_LOG_DATA_LENGTH (0x1C)
3086 
3087 typedef struct _MPI_LOG_0_ENTRY
3088 {
3089  U32 TimeStamp; /* 00h */
3090  U32 Reserved1; /* 04h */
3091  U16 LogSequence; /* 08h */
3092  U16 LogEntryQualifier; /* 0Ah */
3093  U8 LogData[MPI_LOG_0_LOG_DATA_LENGTH]; /* 0Ch */
3094 } MPI_LOG_0_ENTRY, MPI_POINTER PTR_MPI_LOG_0_ENTRY,
3095  MpiLog0Entry_t, MPI_POINTER pMpiLog0Entry_t;
3096 
3097 /* values for Log Page 0 LogEntry LogEntryQualifier field */
3098 #define MPI_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
3099 #define MPI_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
3100 
3101 typedef struct _CONFIG_PAGE_LOG_0
3102 {
3103  CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
3104  U32 Reserved1; /* 08h */
3105  U32 Reserved2; /* 0Ch */
3106  U16 NumLogEntries; /* 10h */
3107  U16 Reserved3; /* 12h */
3108  MPI_LOG_0_ENTRY LogEntry[MPI_LOG_0_NUM_LOG_ENTRIES]; /* 14h */
3109 } CONFIG_PAGE_LOG_0, MPI_POINTER PTR_CONFIG_PAGE_LOG_0,
3110  LogPage0_t, MPI_POINTER pLogPage0_t;
3111 
3112 #define MPI_LOG_0_PAGEVERSION (0x01)
3113 
3114 
3115 #endif
3116 
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