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bfi.h
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1 /*
2  * Linux network driver for Brocade Converged Network Adapter.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms of the GNU General Public License (GPL) Version 2 as
6  * published by the Free Software Foundation
7  *
8  * This program is distributed in the hope that it will be useful, but
9  * WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11  * General Public License for more details.
12  */
13 /*
14  * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15  * All rights reserved
16  * www.brocade.com
17  */
18 #ifndef __BFI_H__
19 #define __BFI_H__
20 
21 #include "bfa_defs.h"
22 
23 #pragma pack(1)
24 
25 /* BFI FW image type */
26 #define BFI_FLASH_CHUNK_SZ 256
27 #define BFI_FLASH_CHUNK_SZ_WORDS (BFI_FLASH_CHUNK_SZ/sizeof(u32))
28 
29 /* Msg header common to all msgs */
30 struct bfi_mhdr {
31  u8 msg_class;
32  u8 msg_id;
33  union {
34  struct {
35  u8 qid;
36  u8 fn_lpu;
37  } h2i;
38  u16 i2htok;
39  } mtag;
40 };
41 
42 #define bfi_fn_lpu(__fn, __lpu) ((__fn) << 1 | (__lpu))
43 #define bfi_mhdr_2_fn(_mh) ((_mh)->mtag.h2i.fn_lpu >> 1)
44 #define bfi_mhdr_2_qid(_mh) ((_mh)->mtag.h2i.qid)
45 
46 #define bfi_h2i_set(_mh, _mc, _op, _fn_lpu) do { \
47  (_mh).msg_class = (_mc); \
48  (_mh).msg_id = (_op); \
49  (_mh).mtag.h2i.fn_lpu = (_fn_lpu); \
50 } while (0)
51 
52 #define bfi_i2h_set(_mh, _mc, _op, _i2htok) do { \
53  (_mh).msg_class = (_mc); \
54  (_mh).msg_id = (_op); \
55  (_mh).mtag.i2htok = (_i2htok); \
56 } while (0)
57 
58 /*
59  * Message opcodes: 0-127 to firmware, 128-255 to host
60  */
61 #define BFI_I2H_OPCODE_BASE 128
62 #define BFA_I2HM(_x) ((_x) + BFI_I2H_OPCODE_BASE)
63 
64 /****************************************************************************
65  *
66  * Scatter Gather Element and Page definition
67  *
68  ****************************************************************************
69  */
70 
71 /* DMA addresses */
72 union bfi_addr_u {
73  struct {
74  u32 addr_lo;
75  u32 addr_hi;
76  } a32;
77 };
78 
79 /* Generic DMA addr-len pair. */
80 struct bfi_alen {
81  union bfi_addr_u al_addr; /* DMA addr of buffer */
82  u32 al_len; /* length of buffer */
83 };
84 
85 /*
86  * Large Message structure - 128 Bytes size Msgs
87  */
88 #define BFI_LMSG_SZ 128
89 #define BFI_LMSG_PL_WSZ \
90  ((BFI_LMSG_SZ - sizeof(struct bfi_mhdr)) / 4)
91 
92 /* Mailbox message structure */
93 #define BFI_MBMSG_SZ 7
94 struct bfi_mbmsg {
95  struct bfi_mhdr mh;
96  u32 pl[BFI_MBMSG_SZ];
97 };
98 
99 /* Supported PCI function class codes (personality) */
100 enum bfi_pcifn_class {
101  BFI_PCIFN_CLASS_FC = 0x0c04,
102  BFI_PCIFN_CLASS_ETH = 0x0200,
103 };
104 
105 /* Message Classes */
106 enum bfi_mclass {
107  BFI_MC_IOC = 1,
108  BFI_MC_DIAG = 2,
109  BFI_MC_FLASH = 3,
110  BFI_MC_CEE = 4,
111  BFI_MC_FCPORT = 5,
112  BFI_MC_IOCFC = 6,
113  BFI_MC_LL = 7,
114  BFI_MC_UF = 8,
115  BFI_MC_FCXP = 9,
116  BFI_MC_LPS = 10,
117  BFI_MC_RPORT = 11,
118  BFI_MC_ITNIM = 12,
119  BFI_MC_IOIM_READ = 13,
120  BFI_MC_IOIM_WRITE = 14,
121  BFI_MC_IOIM_IO = 15,
122  BFI_MC_IOIM = 16,
123  BFI_MC_IOIM_IOCOM = 17,
124  BFI_MC_TSKIM = 18,
125  BFI_MC_SBOOT = 19,
126  BFI_MC_IPFC = 20,
127  BFI_MC_PORT = 21,
128  BFI_MC_SFP = 22,
129  BFI_MC_MSGQ = 23,
130  BFI_MC_ENET = 24,
131  BFI_MC_PHY = 25,
132  BFI_MC_NBOOT = 26,
133  BFI_MC_TIO_READ = 27,
134  BFI_MC_TIO_WRITE = 28,
135  BFI_MC_TIO_DATA_XFERED = 29,
136  BFI_MC_TIO_IO = 30,
137  BFI_MC_TIO = 31,
138  BFI_MC_MFG = 32,
139  BFI_MC_EDMA = 33,
140  BFI_MC_MAX = 34
141 };
142 
143 #define BFI_IOC_MSGLEN_MAX 32 /* 32 bytes */
144 
145 #define BFI_FWBOOT_ENV_OS 0
146 
147 /*----------------------------------------------------------------------
148  * IOC
149  *----------------------------------------------------------------------
150  */
151 
152 /* Different asic generations */
153 enum bfi_asic_gen {
154  BFI_ASIC_GEN_CB = 1,
155  BFI_ASIC_GEN_CT = 2,
156  BFI_ASIC_GEN_CT2 = 3,
157 };
158 
159 enum bfi_asic_mode {
160  BFI_ASIC_MODE_FC = 1, /* FC upto 8G speed */
161  BFI_ASIC_MODE_FC16 = 2, /* FC upto 16G speed */
162  BFI_ASIC_MODE_ETH = 3, /* Ethernet ports */
163  BFI_ASIC_MODE_COMBO = 4, /* FC 16G and Ethernet 10G port */
164 };
165 
166 enum bfi_ioc_h2i_msgs {
167  BFI_IOC_H2I_ENABLE_REQ = 1,
168  BFI_IOC_H2I_DISABLE_REQ = 2,
169  BFI_IOC_H2I_GETATTR_REQ = 3,
170  BFI_IOC_H2I_DBG_SYNC = 4,
171  BFI_IOC_H2I_DBG_DUMP = 5,
172 };
173 
174 enum bfi_ioc_i2h_msgs {
175  BFI_IOC_I2H_ENABLE_REPLY = BFA_I2HM(1),
176  BFI_IOC_I2H_DISABLE_REPLY = BFA_I2HM(2),
177  BFI_IOC_I2H_GETATTR_REPLY = BFA_I2HM(3),
178  BFI_IOC_I2H_HBEAT = BFA_I2HM(4),
179 };
180 
181 /* BFI_IOC_H2I_GETATTR_REQ message */
182 struct bfi_ioc_getattr_req {
183  struct bfi_mhdr mh;
184  union bfi_addr_u attr_addr;
185 };
186 
187 struct bfi_ioc_attr {
188  u64 mfg_pwwn;
189  u64 mfg_nwwn;
190  mac_t mfg_mac;
191  u8 port_mode; /* enum bfi_port_mode */
192  u8 rsvd_a;
193  u64 pwwn;
194  u64 nwwn;
195  mac_t mac;
196  u16 rsvd_b;
197  mac_t fcoe_mac;
198  u16 rsvd_c;
199  char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
200  u8 pcie_gen;
201  u8 pcie_lanes_orig;
202  u8 pcie_lanes;
203  u8 rx_bbcredit;
204  u32 adapter_prop;
205  u16 maxfrsize;
206  char asic_rev;
207  u8 rsvd_d;
208  char fw_version[BFA_VERSION_LEN];
209  char optrom_version[BFA_VERSION_LEN];
210  struct bfa_mfg_vpd vpd;
211  u32 card_type;
212 };
213 
214 /* BFI_IOC_I2H_GETATTR_REPLY message */
215 struct bfi_ioc_getattr_reply {
216  struct bfi_mhdr mh;
217  u8 status;
218  u8 rsvd[3];
219 };
220 
221 /* Firmware memory page offsets */
222 #define BFI_IOC_SMEM_PG0_CB (0x40)
223 #define BFI_IOC_SMEM_PG0_CT (0x180)
224 
225 /* Firmware statistic offset */
226 #define BFI_IOC_FWSTATS_OFF (0x6B40)
227 #define BFI_IOC_FWSTATS_SZ (4096)
228 
229 /* Firmware trace offset */
230 #define BFI_IOC_TRC_OFF (0x4b00)
231 #define BFI_IOC_TRC_ENTS 256
232 #define BFI_IOC_TRC_ENT_SZ 16
233 #define BFI_IOC_TRC_HDR_SZ 32
234 
235 #define BFI_IOC_FW_SIGNATURE (0xbfadbfad)
236 #define BFI_IOC_MD5SUM_SZ 4
237 struct bfi_ioc_image_hdr {
238  u32 signature;
239  u8 asic_gen;
240  u8 asic_mode;
241  u8 port0_mode;
242  u8 port1_mode;
243  u32 exec;
244  u32 bootenv;
245  u32 rsvd_b[4];
246  u32 md5sum[BFI_IOC_MD5SUM_SZ];
247 };
248 
249 #define BFI_FWBOOT_DEVMODE_OFF 4
250 #define BFI_FWBOOT_TYPE_OFF 8
251 #define BFI_FWBOOT_ENV_OFF 12
252 #define BFI_FWBOOT_DEVMODE(__asic_gen, __asic_mode, __p0_mode, __p1_mode) \
253  (((u32)(__asic_gen)) << 24 | \
254  ((u32)(__asic_mode)) << 16 | \
255  ((u32)(__p0_mode)) << 8 | \
256  ((u32)(__p1_mode)))
257 
258 enum bfi_fwboot_type {
259  BFI_FWBOOT_TYPE_NORMAL = 0,
260  BFI_FWBOOT_TYPE_FLASH = 1,
261  BFI_FWBOOT_TYPE_MEMTEST = 2,
262 };
263 
264 enum bfi_port_mode {
265  BFI_PORT_MODE_FC = 1,
266  BFI_PORT_MODE_ETH = 2,
267 };
268 
269 struct bfi_ioc_hbeat {
270  struct bfi_mhdr mh;
271  u32 hb_count;
272 };
273 
274 /* IOC hardware/firmware state */
275 enum bfi_ioc_state {
276  BFI_IOC_UNINIT = 0,
277  BFI_IOC_INITING = 1,
278  BFI_IOC_HWINIT = 2,
279  BFI_IOC_CFG = 3,
280  BFI_IOC_OP = 4,
281  BFI_IOC_DISABLING = 5,
282  BFI_IOC_DISABLED = 6,
283  BFI_IOC_CFG_DISABLED = 7,
284  BFI_IOC_FAIL = 8,
285  BFI_IOC_MEMTEST = 9,
286 };
287 
288 #define BFI_IOC_ENDIAN_SIG 0x12345678
289 
290 enum {
291  BFI_ADAPTER_TYPE_FC = 0x01,
292  BFI_ADAPTER_TYPE_MK = 0x0f0000,
293  BFI_ADAPTER_TYPE_SH = 16,
294  BFI_ADAPTER_NPORTS_MK = 0xff00,
295  BFI_ADAPTER_NPORTS_SH = 8,
296  BFI_ADAPTER_SPEED_MK = 0xff,
297  BFI_ADAPTER_SPEED_SH = 0,
298  BFI_ADAPTER_PROTO = 0x100000,
299  BFI_ADAPTER_TTV = 0x200000,
300  BFI_ADAPTER_UNSUPP = 0x400000,
301 };
302 
303 #define BFI_ADAPTER_GETP(__prop, __adap_prop) \
304  (((__adap_prop) & BFI_ADAPTER_ ## __prop ## _MK) >> \
305  BFI_ADAPTER_ ## __prop ## _SH)
306 #define BFI_ADAPTER_SETP(__prop, __val) \
307  ((__val) << BFI_ADAPTER_ ## __prop ## _SH)
308 #define BFI_ADAPTER_IS_PROTO(__adap_type) \
309  ((__adap_type) & BFI_ADAPTER_PROTO)
310 #define BFI_ADAPTER_IS_TTV(__adap_type) \
311  ((__adap_type) & BFI_ADAPTER_TTV)
312 #define BFI_ADAPTER_IS_UNSUPP(__adap_type) \
313  ((__adap_type) & BFI_ADAPTER_UNSUPP)
314 #define BFI_ADAPTER_IS_SPECIAL(__adap_type) \
315  ((__adap_type) & (BFI_ADAPTER_TTV | BFI_ADAPTER_PROTO | \
316  BFI_ADAPTER_UNSUPP))
317 
318 /* BFI_IOC_H2I_ENABLE_REQ & BFI_IOC_H2I_DISABLE_REQ messages */
319 struct bfi_ioc_ctrl_req {
320  struct bfi_mhdr mh;
321  u16 clscode;
322  u16 rsvd;
323  u32 tv_sec;
324 };
325 
326 /* BFI_IOC_I2H_ENABLE_REPLY & BFI_IOC_I2H_DISABLE_REPLY messages */
327 struct bfi_ioc_ctrl_reply {
328  struct bfi_mhdr mh;
329  u8 status;
330  u8 port_mode;
331  u8 cap_bm;
332  u8 rsvd;
333 };
334 
335 #define BFI_IOC_MSGSZ 8
336 /* H2I Messages */
337 union bfi_ioc_h2i_msg_u {
338  struct bfi_mhdr mh;
339  struct bfi_ioc_ctrl_req enable_req;
340  struct bfi_ioc_ctrl_req disable_req;
341  struct bfi_ioc_getattr_req getattr_req;
342  u32 mboxmsg[BFI_IOC_MSGSZ];
343 };
344 
345 /* I2H Messages */
346 union bfi_ioc_i2h_msg_u {
347  struct bfi_mhdr mh;
348  struct bfi_ioc_ctrl_reply fw_event;
349  u32 mboxmsg[BFI_IOC_MSGSZ];
350 };
351 
352 /*----------------------------------------------------------------------
353  * MSGQ
354  *----------------------------------------------------------------------
355  */
356 
357 enum bfi_msgq_h2i_msgs {
358  BFI_MSGQ_H2I_INIT_REQ = 1,
359  BFI_MSGQ_H2I_DOORBELL_PI = 2,
360  BFI_MSGQ_H2I_DOORBELL_CI = 3,
361  BFI_MSGQ_H2I_CMDQ_COPY_RSP = 4,
362 };
363 
364 enum bfi_msgq_i2h_msgs {
365  BFI_MSGQ_I2H_INIT_RSP = BFA_I2HM(BFI_MSGQ_H2I_INIT_REQ),
366  BFI_MSGQ_I2H_DOORBELL_PI = BFA_I2HM(BFI_MSGQ_H2I_DOORBELL_PI),
367  BFI_MSGQ_I2H_DOORBELL_CI = BFA_I2HM(BFI_MSGQ_H2I_DOORBELL_CI),
368  BFI_MSGQ_I2H_CMDQ_COPY_REQ = BFA_I2HM(BFI_MSGQ_H2I_CMDQ_COPY_RSP),
369 };
370 
371 /* Messages(commands/responsed/AENS will have the following header */
372 struct bfi_msgq_mhdr {
373  u8 msg_class;
374  u8 msg_id;
375  u16 msg_token;
376  u16 num_entries;
377  u8 enet_id;
378  u8 rsvd[1];
379 };
380 
381 #define bfi_msgq_mhdr_set(_mh, _mc, _mid, _tok, _enet_id) do { \
382  (_mh).msg_class = (_mc); \
383  (_mh).msg_id = (_mid); \
384  (_mh).msg_token = (_tok); \
385  (_mh).enet_id = (_enet_id); \
386 } while (0)
387 
388 /*
389  * Mailbox for messaging interface
390  */
391 #define BFI_MSGQ_CMD_ENTRY_SIZE (64) /* TBD */
392 #define BFI_MSGQ_RSP_ENTRY_SIZE (64) /* TBD */
393 
394 #define bfi_msgq_num_cmd_entries(_size) \
395  (((_size) + BFI_MSGQ_CMD_ENTRY_SIZE - 1) / BFI_MSGQ_CMD_ENTRY_SIZE)
396 
397 struct bfi_msgq {
398  union bfi_addr_u addr;
399  u16 q_depth; /* Total num of entries in the queue */
400  u8 rsvd[2];
401 };
402 
403 /* BFI_ENET_MSGQ_CFG_REQ TBD init or cfg? */
404 struct bfi_msgq_cfg_req {
405  struct bfi_mhdr mh;
406  struct bfi_msgq cmdq;
407  struct bfi_msgq rspq;
408 };
409 
410 /* BFI_ENET_MSGQ_CFG_RSP */
411 struct bfi_msgq_cfg_rsp {
412  struct bfi_mhdr mh;
413  u8 cmd_status;
414  u8 rsvd[3];
415 };
416 
417 /* BFI_MSGQ_H2I_DOORBELL */
418 struct bfi_msgq_h2i_db {
419  struct bfi_mhdr mh;
420  union {
421  u16 cmdq_pi;
422  u16 rspq_ci;
423  } idx;
424 };
425 
426 /* BFI_MSGQ_I2H_DOORBELL */
427 struct bfi_msgq_i2h_db {
428  struct bfi_mhdr mh;
429  union {
430  u16 rspq_pi;
431  u16 cmdq_ci;
432  } idx;
433 };
434 
435 #define BFI_CMD_COPY_SZ 28
436 
437 /* BFI_MSGQ_H2I_CMD_COPY_RSP */
438 struct bfi_msgq_h2i_cmdq_copy_rsp {
439  struct bfi_mhdr mh;
440  u8 data[BFI_CMD_COPY_SZ];
441 };
442 
443 /* BFI_MSGQ_I2H_CMD_COPY_REQ */
444 struct bfi_msgq_i2h_cmdq_copy_req {
445  struct bfi_mhdr mh;
446  u16 offset;
447  u16 len;
448 };
449 
450 /*
451  * FLASH module specific
452  */
453 enum bfi_flash_h2i_msgs {
454  BFI_FLASH_H2I_QUERY_REQ = 1,
455  BFI_FLASH_H2I_ERASE_REQ = 2,
456  BFI_FLASH_H2I_WRITE_REQ = 3,
457  BFI_FLASH_H2I_READ_REQ = 4,
458  BFI_FLASH_H2I_BOOT_VER_REQ = 5,
459 };
460 
461 enum bfi_flash_i2h_msgs {
462  BFI_FLASH_I2H_QUERY_RSP = BFA_I2HM(1),
463  BFI_FLASH_I2H_ERASE_RSP = BFA_I2HM(2),
464  BFI_FLASH_I2H_WRITE_RSP = BFA_I2HM(3),
465  BFI_FLASH_I2H_READ_RSP = BFA_I2HM(4),
466  BFI_FLASH_I2H_BOOT_VER_RSP = BFA_I2HM(5),
467  BFI_FLASH_I2H_EVENT = BFA_I2HM(127),
468 };
469 
470 /*
471  * Flash query request
472  */
473 struct bfi_flash_query_req {
474  struct bfi_mhdr mh; /* Common msg header */
475  struct bfi_alen alen;
476 };
477 
478 /*
479  * Flash write request
480  */
481 struct bfi_flash_write_req {
482  struct bfi_mhdr mh; /* Common msg header */
483  struct bfi_alen alen;
484  u32 type; /* partition type */
485  u8 instance; /* partition instance */
486  u8 last;
487  u8 rsv[2];
488  u32 offset;
489  u32 length;
490 };
491 
492 /*
493  * Flash read request
494  */
495 struct bfi_flash_read_req {
496  struct bfi_mhdr mh; /* Common msg header */
497  u32 type; /* partition type */
498  u8 instance; /* partition instance */
499  u8 rsv[3];
500  u32 offset;
501  u32 length;
502  struct bfi_alen alen;
503 };
504 
505 /*
506  * Flash query response
507  */
508 struct bfi_flash_query_rsp {
509  struct bfi_mhdr mh; /* Common msg header */
510  u32 status;
511 };
512 
513 /*
514  * Flash read response
515  */
516 struct bfi_flash_read_rsp {
517  struct bfi_mhdr mh; /* Common msg header */
518  u32 type; /* partition type */
519  u8 instance; /* partition instance */
520  u8 rsv[3];
521  u32 status;
522  u32 length;
523 };
524 
525 /*
526  * Flash write response
527  */
528 struct bfi_flash_write_rsp {
529  struct bfi_mhdr mh; /* Common msg header */
530  u32 type; /* partition type */
531  u8 instance; /* partition instance */
532  u8 rsv[3];
533  u32 status;
534  u32 length;
535 };
536 
537 #pragma pack()
538 
539 #endif /* __BFI_H__ */
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