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11 #ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H
12 #define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
17 #define SAR_BANK1_OFFSET 0x0000
18 #define SAR_BANK2_OFFSET 0x1000
19 #define SAR_BANK3_OFFSET 0x2000
20 #define SAR_BANK4_OFFSET 0x3000
23 #define SCU_OFFSET0 0xd00
24 #define SCU_OFFSET1 0xd04
25 #define OMAP_TYPE_OFFSET 0xd10
26 #define L2X0_SAVE_OFFSET0 0xd14
27 #define L2X0_SAVE_OFFSET1 0xd18
28 #define L2X0_AUXCTRL_OFFSET 0xd1c
29 #define L2X0_PREFETCH_CTRL_OFFSET 0xd20
32 #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04
33 #define CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xa08
35 #define SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x500)
36 #define SAR_SECURE_RAM_SIZE_OFFSET (SAR_BANK3_OFFSET + 0x504)
37 #define SAR_SECRAM_SAVED_AT_OFFSET (SAR_BANK3_OFFSET + 0x508)
40 #define WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x684)
41 #define WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x694)
42 #define WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x6a4)
43 #define WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x6b4)
44 #define AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x6c4)
45 #define AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x6c8)
46 #define PTMSYNCREQ_MASK_OFFSET (SAR_BANK3_OFFSET + 0x6cc)
47 #define PTMSYNCREQ_EN_OFFSET (SAR_BANK3_OFFSET + 0x6d0)
48 #define SAR_BACKUP_STATUS_WAKEUPGEN 0x10
51 #define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8d4)
52 #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8e8)
53 #define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x8fc)
54 #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x910)
55 #define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x924)
56 #define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x928)
57 #define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0x92c)
58 #define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800)