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oxygen_pcm.c
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1 /*
2  * C-Media CMI8788 driver - PCM code
3  *
4  * Copyright (c) Clemens Ladisch <[email protected]>
5  *
6  *
7  * This driver is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License, version 2.
9  *
10  * This driver is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this driver; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18  */
19 
20 #include <linux/pci.h>
21 #include <sound/control.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include "oxygen.h"
26 
27 /* most DMA channels have a 16-bit counter for 32-bit words */
28 #define BUFFER_BYTES_MAX ((1 << 16) * 4)
29 /* the multichannel DMA channel has a 24-bit counter */
30 #define BUFFER_BYTES_MAX_MULTICH ((1 << 24) * 4)
31 
32 #define PERIOD_BYTES_MIN 64
33 
34 #define DEFAULT_BUFFER_BYTES (BUFFER_BYTES_MAX / 2)
35 #define DEFAULT_BUFFER_BYTES_MULTICH (1024 * 1024)
36 
37 static const struct snd_pcm_hardware oxygen_stereo_hardware = {
38  .info = SNDRV_PCM_INFO_MMAP |
39  SNDRV_PCM_INFO_MMAP_VALID |
40  SNDRV_PCM_INFO_INTERLEAVED |
41  SNDRV_PCM_INFO_PAUSE |
42  SNDRV_PCM_INFO_SYNC_START |
43  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
44  .formats = SNDRV_PCM_FMTBIT_S16_LE |
45  SNDRV_PCM_FMTBIT_S32_LE,
46  .rates = SNDRV_PCM_RATE_32000 |
47  SNDRV_PCM_RATE_44100 |
48  SNDRV_PCM_RATE_48000 |
49  SNDRV_PCM_RATE_64000 |
50  SNDRV_PCM_RATE_88200 |
51  SNDRV_PCM_RATE_96000 |
52  SNDRV_PCM_RATE_176400 |
53  SNDRV_PCM_RATE_192000,
54  .rate_min = 32000,
55  .rate_max = 192000,
56  .channels_min = 2,
57  .channels_max = 2,
58  .buffer_bytes_max = BUFFER_BYTES_MAX,
59  .period_bytes_min = PERIOD_BYTES_MIN,
60  .period_bytes_max = BUFFER_BYTES_MAX,
61  .periods_min = 1,
62  .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
63 };
64 static const struct snd_pcm_hardware oxygen_multichannel_hardware = {
65  .info = SNDRV_PCM_INFO_MMAP |
66  SNDRV_PCM_INFO_MMAP_VALID |
67  SNDRV_PCM_INFO_INTERLEAVED |
68  SNDRV_PCM_INFO_PAUSE |
69  SNDRV_PCM_INFO_SYNC_START |
70  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
71  .formats = SNDRV_PCM_FMTBIT_S16_LE |
72  SNDRV_PCM_FMTBIT_S32_LE,
73  .rates = SNDRV_PCM_RATE_32000 |
74  SNDRV_PCM_RATE_44100 |
75  SNDRV_PCM_RATE_48000 |
76  SNDRV_PCM_RATE_64000 |
77  SNDRV_PCM_RATE_88200 |
78  SNDRV_PCM_RATE_96000 |
79  SNDRV_PCM_RATE_176400 |
80  SNDRV_PCM_RATE_192000,
81  .rate_min = 32000,
82  .rate_max = 192000,
83  .channels_min = 2,
84  .channels_max = 8,
85  .buffer_bytes_max = BUFFER_BYTES_MAX_MULTICH,
86  .period_bytes_min = PERIOD_BYTES_MIN,
87  .period_bytes_max = BUFFER_BYTES_MAX_MULTICH,
88  .periods_min = 1,
89  .periods_max = BUFFER_BYTES_MAX_MULTICH / PERIOD_BYTES_MIN,
90 };
91 static const struct snd_pcm_hardware oxygen_ac97_hardware = {
92  .info = SNDRV_PCM_INFO_MMAP |
93  SNDRV_PCM_INFO_MMAP_VALID |
94  SNDRV_PCM_INFO_INTERLEAVED |
95  SNDRV_PCM_INFO_PAUSE |
96  SNDRV_PCM_INFO_SYNC_START |
97  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
98  .formats = SNDRV_PCM_FMTBIT_S16_LE,
99  .rates = SNDRV_PCM_RATE_48000,
100  .rate_min = 48000,
101  .rate_max = 48000,
102  .channels_min = 2,
103  .channels_max = 2,
104  .buffer_bytes_max = BUFFER_BYTES_MAX,
105  .period_bytes_min = PERIOD_BYTES_MIN,
106  .period_bytes_max = BUFFER_BYTES_MAX,
107  .periods_min = 1,
108  .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
109 };
110 
111 static const struct snd_pcm_hardware *const oxygen_hardware[PCM_COUNT] = {
112  [PCM_A] = &oxygen_stereo_hardware,
113  [PCM_B] = &oxygen_stereo_hardware,
114  [PCM_C] = &oxygen_stereo_hardware,
115  [PCM_SPDIF] = &oxygen_stereo_hardware,
116  [PCM_MULTICH] = &oxygen_multichannel_hardware,
117  [PCM_AC97] = &oxygen_ac97_hardware,
118 };
119 
120 static inline unsigned int
121 oxygen_substream_channel(struct snd_pcm_substream *substream)
122 {
123  return (unsigned int)(uintptr_t)substream->runtime->private_data;
124 }
125 
126 static int oxygen_open(struct snd_pcm_substream *substream,
127  unsigned int channel)
128 {
129  struct oxygen *chip = snd_pcm_substream_chip(substream);
130  struct snd_pcm_runtime *runtime = substream->runtime;
131  int err;
132 
133  runtime->private_data = (void *)(uintptr_t)channel;
134  if (channel == PCM_B && chip->has_ac97_1 &&
135  (chip->model.device_config & CAPTURE_2_FROM_AC97_1))
136  runtime->hw = oxygen_ac97_hardware;
137  else
138  runtime->hw = *oxygen_hardware[channel];
139  switch (channel) {
140  case PCM_C:
141  runtime->hw.rates &= ~(SNDRV_PCM_RATE_32000 |
142  SNDRV_PCM_RATE_64000);
143  runtime->hw.rate_min = 44100;
144  break;
145  case PCM_MULTICH:
146  runtime->hw.channels_max = chip->model.dac_channels_pcm;
147  break;
148  }
149  if (chip->model.pcm_hardware_filter)
150  chip->model.pcm_hardware_filter(channel, &runtime->hw);
151  err = snd_pcm_hw_constraint_step(runtime, 0,
152  SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
153  if (err < 0)
154  return err;
155  err = snd_pcm_hw_constraint_step(runtime, 0,
156  SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
157  if (err < 0)
158  return err;
159  if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) {
160  err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
161  if (err < 0)
162  return err;
163  }
164  if (runtime->hw.channels_max > 2) {
165  err = snd_pcm_hw_constraint_step(runtime, 0,
166  SNDRV_PCM_HW_PARAM_CHANNELS,
167  2);
168  if (err < 0)
169  return err;
170  }
171  snd_pcm_set_sync(substream);
172  chip->streams[channel] = substream;
173 
174  mutex_lock(&chip->mutex);
175  chip->pcm_active |= 1 << channel;
176  if (channel == PCM_SPDIF) {
177  chip->spdif_pcm_bits = chip->spdif_bits;
178  chip->controls[CONTROL_SPDIF_PCM]->vd[0].access &=
179  ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
180  snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
181  SNDRV_CTL_EVENT_MASK_INFO,
182  &chip->controls[CONTROL_SPDIF_PCM]->id);
183  }
184  mutex_unlock(&chip->mutex);
185 
186  return 0;
187 }
188 
189 static int oxygen_rec_a_open(struct snd_pcm_substream *substream)
190 {
191  return oxygen_open(substream, PCM_A);
192 }
193 
194 static int oxygen_rec_b_open(struct snd_pcm_substream *substream)
195 {
196  return oxygen_open(substream, PCM_B);
197 }
198 
199 static int oxygen_rec_c_open(struct snd_pcm_substream *substream)
200 {
201  return oxygen_open(substream, PCM_C);
202 }
203 
204 static int oxygen_spdif_open(struct snd_pcm_substream *substream)
205 {
206  return oxygen_open(substream, PCM_SPDIF);
207 }
208 
209 static int oxygen_multich_open(struct snd_pcm_substream *substream)
210 {
211  return oxygen_open(substream, PCM_MULTICH);
212 }
213 
214 static int oxygen_ac97_open(struct snd_pcm_substream *substream)
215 {
216  return oxygen_open(substream, PCM_AC97);
217 }
218 
219 static int oxygen_close(struct snd_pcm_substream *substream)
220 {
221  struct oxygen *chip = snd_pcm_substream_chip(substream);
222  unsigned int channel = oxygen_substream_channel(substream);
223 
224  mutex_lock(&chip->mutex);
225  chip->pcm_active &= ~(1 << channel);
226  if (channel == PCM_SPDIF) {
227  chip->controls[CONTROL_SPDIF_PCM]->vd[0].access |=
228  SNDRV_CTL_ELEM_ACCESS_INACTIVE;
229  snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
230  SNDRV_CTL_EVENT_MASK_INFO,
231  &chip->controls[CONTROL_SPDIF_PCM]->id);
232  }
233  if (channel == PCM_SPDIF || channel == PCM_MULTICH)
234  oxygen_update_spdif_source(chip);
235  mutex_unlock(&chip->mutex);
236 
237  chip->streams[channel] = NULL;
238  return 0;
239 }
240 
241 static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params)
242 {
243  if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
244  return OXYGEN_FORMAT_24;
245  else
246  return OXYGEN_FORMAT_16;
247 }
248 
249 static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
250 {
251  switch (params_rate(hw_params)) {
252  case 32000:
253  return OXYGEN_RATE_32000;
254  case 44100:
255  return OXYGEN_RATE_44100;
256  default: /* 48000 */
257  return OXYGEN_RATE_48000;
258  case 64000:
259  return OXYGEN_RATE_64000;
260  case 88200:
261  return OXYGEN_RATE_88200;
262  case 96000:
263  return OXYGEN_RATE_96000;
264  case 176400:
265  return OXYGEN_RATE_176400;
266  case 192000:
267  return OXYGEN_RATE_192000;
268  }
269 }
270 
271 static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params)
272 {
273  if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
274  return OXYGEN_I2S_BITS_24;
275  else
276  return OXYGEN_I2S_BITS_16;
277 }
278 
279 static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params)
280 {
281  switch (params_channels(hw_params)) {
282  default: /* 2 */
283  return OXYGEN_PLAY_CHANNELS_2;
284  case 4:
285  return OXYGEN_PLAY_CHANNELS_4;
286  case 6:
287  return OXYGEN_PLAY_CHANNELS_6;
288  case 8:
289  return OXYGEN_PLAY_CHANNELS_8;
290  }
291 }
292 
293 static const unsigned int channel_base_registers[PCM_COUNT] = {
294  [PCM_A] = OXYGEN_DMA_A_ADDRESS,
295  [PCM_B] = OXYGEN_DMA_B_ADDRESS,
296  [PCM_C] = OXYGEN_DMA_C_ADDRESS,
297  [PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS,
298  [PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS,
299  [PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS,
300 };
301 
302 static int oxygen_hw_params(struct snd_pcm_substream *substream,
303  struct snd_pcm_hw_params *hw_params)
304 {
305  struct oxygen *chip = snd_pcm_substream_chip(substream);
306  unsigned int channel = oxygen_substream_channel(substream);
307  int err;
308 
309  err = snd_pcm_lib_malloc_pages(substream,
310  params_buffer_bytes(hw_params));
311  if (err < 0)
312  return err;
313 
314  oxygen_write32(chip, channel_base_registers[channel],
315  (u32)substream->runtime->dma_addr);
316  if (channel == PCM_MULTICH) {
317  oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT,
318  params_buffer_bytes(hw_params) / 4 - 1);
319  oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT,
320  params_period_bytes(hw_params) / 4 - 1);
321  } else {
322  oxygen_write16(chip, channel_base_registers[channel] + 4,
323  params_buffer_bytes(hw_params) / 4 - 1);
324  oxygen_write16(chip, channel_base_registers[channel] + 6,
325  params_period_bytes(hw_params) / 4 - 1);
326  }
327  return 0;
328 }
329 
330 static u16 get_mclk(struct oxygen *chip, unsigned int channel,
331  struct snd_pcm_hw_params *params)
332 {
333  unsigned int mclks, shift;
334 
335  if (channel == PCM_MULTICH)
336  mclks = chip->model.dac_mclks;
337  else
338  mclks = chip->model.adc_mclks;
339 
340  if (params_rate(params) <= 48000)
341  shift = 0;
342  else if (params_rate(params) <= 96000)
343  shift = 2;
344  else
345  shift = 4;
346 
347  return OXYGEN_I2S_MCLK(mclks >> shift);
348 }
349 
350 static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
351  struct snd_pcm_hw_params *hw_params)
352 {
353  struct oxygen *chip = snd_pcm_substream_chip(substream);
354  int err;
355 
356  err = oxygen_hw_params(substream, hw_params);
357  if (err < 0)
358  return err;
359 
360  spin_lock_irq(&chip->reg_lock);
361  oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
362  oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT,
363  OXYGEN_REC_FORMAT_A_MASK);
364  oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT,
365  oxygen_rate(hw_params) |
366  chip->model.adc_i2s_format |
367  get_mclk(chip, PCM_A, hw_params) |
368  oxygen_i2s_bits(hw_params),
369  OXYGEN_I2S_RATE_MASK |
370  OXYGEN_I2S_FORMAT_MASK |
371  OXYGEN_I2S_MCLK_MASK |
372  OXYGEN_I2S_BITS_MASK);
373  spin_unlock_irq(&chip->reg_lock);
374 
375  mutex_lock(&chip->mutex);
376  chip->model.set_adc_params(chip, hw_params);
377  mutex_unlock(&chip->mutex);
378  return 0;
379 }
380 
381 static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
382  struct snd_pcm_hw_params *hw_params)
383 {
384  struct oxygen *chip = snd_pcm_substream_chip(substream);
385  int is_ac97;
386  int err;
387 
388  err = oxygen_hw_params(substream, hw_params);
389  if (err < 0)
390  return err;
391 
392  is_ac97 = chip->has_ac97_1 &&
393  (chip->model.device_config & CAPTURE_2_FROM_AC97_1);
394 
395  spin_lock_irq(&chip->reg_lock);
396  oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
397  oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT,
398  OXYGEN_REC_FORMAT_B_MASK);
399  if (!is_ac97)
400  oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT,
401  oxygen_rate(hw_params) |
402  chip->model.adc_i2s_format |
403  get_mclk(chip, PCM_B, hw_params) |
404  oxygen_i2s_bits(hw_params),
405  OXYGEN_I2S_RATE_MASK |
406  OXYGEN_I2S_FORMAT_MASK |
407  OXYGEN_I2S_MCLK_MASK |
408  OXYGEN_I2S_BITS_MASK);
409  spin_unlock_irq(&chip->reg_lock);
410 
411  if (!is_ac97) {
412  mutex_lock(&chip->mutex);
413  chip->model.set_adc_params(chip, hw_params);
414  mutex_unlock(&chip->mutex);
415  }
416  return 0;
417 }
418 
419 static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream,
420  struct snd_pcm_hw_params *hw_params)
421 {
422  struct oxygen *chip = snd_pcm_substream_chip(substream);
423  int err;
424 
425  err = oxygen_hw_params(substream, hw_params);
426  if (err < 0)
427  return err;
428 
429  spin_lock_irq(&chip->reg_lock);
430  oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
431  oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
432  OXYGEN_REC_FORMAT_C_MASK);
433  spin_unlock_irq(&chip->reg_lock);
434  return 0;
435 }
436 
437 static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream,
438  struct snd_pcm_hw_params *hw_params)
439 {
440  struct oxygen *chip = snd_pcm_substream_chip(substream);
441  int err;
442 
443  err = oxygen_hw_params(substream, hw_params);
444  if (err < 0)
445  return err;
446 
447  mutex_lock(&chip->mutex);
448  spin_lock_irq(&chip->reg_lock);
449  oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
450  OXYGEN_SPDIF_OUT_ENABLE);
451  oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
452  oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT,
453  OXYGEN_SPDIF_FORMAT_MASK);
454  oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
455  oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT,
456  OXYGEN_SPDIF_OUT_RATE_MASK);
457  oxygen_update_spdif_source(chip);
458  spin_unlock_irq(&chip->reg_lock);
459  mutex_unlock(&chip->mutex);
460  return 0;
461 }
462 
463 static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
464  struct snd_pcm_hw_params *hw_params)
465 {
466  struct oxygen *chip = snd_pcm_substream_chip(substream);
467  int err;
468 
469  err = oxygen_hw_params(substream, hw_params);
470  if (err < 0)
471  return err;
472 
473  mutex_lock(&chip->mutex);
474  spin_lock_irq(&chip->reg_lock);
475  oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS,
476  oxygen_play_channels(hw_params),
477  OXYGEN_PLAY_CHANNELS_MASK);
478  oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
479  oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT,
480  OXYGEN_MULTICH_FORMAT_MASK);
481  oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT,
482  oxygen_rate(hw_params) |
483  chip->model.dac_i2s_format |
484  get_mclk(chip, PCM_MULTICH, hw_params) |
485  oxygen_i2s_bits(hw_params),
486  OXYGEN_I2S_RATE_MASK |
487  OXYGEN_I2S_FORMAT_MASK |
488  OXYGEN_I2S_MCLK_MASK |
489  OXYGEN_I2S_BITS_MASK);
490  oxygen_update_spdif_source(chip);
491  spin_unlock_irq(&chip->reg_lock);
492 
493  chip->model.set_dac_params(chip, hw_params);
494  oxygen_update_dac_routing(chip);
495  mutex_unlock(&chip->mutex);
496  return 0;
497 }
498 
499 static int oxygen_hw_free(struct snd_pcm_substream *substream)
500 {
501  struct oxygen *chip = snd_pcm_substream_chip(substream);
502  unsigned int channel = oxygen_substream_channel(substream);
503  unsigned int channel_mask = 1 << channel;
504 
505  spin_lock_irq(&chip->reg_lock);
506  chip->interrupt_mask &= ~channel_mask;
507  oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
508 
509  oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
510  oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
511  spin_unlock_irq(&chip->reg_lock);
512 
513  return snd_pcm_lib_free_pages(substream);
514 }
515 
516 static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream)
517 {
518  struct oxygen *chip = snd_pcm_substream_chip(substream);
519 
520  spin_lock_irq(&chip->reg_lock);
521  oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
522  OXYGEN_SPDIF_OUT_ENABLE);
523  spin_unlock_irq(&chip->reg_lock);
524  return oxygen_hw_free(substream);
525 }
526 
527 static int oxygen_prepare(struct snd_pcm_substream *substream)
528 {
529  struct oxygen *chip = snd_pcm_substream_chip(substream);
530  unsigned int channel = oxygen_substream_channel(substream);
531  unsigned int channel_mask = 1 << channel;
532 
533  spin_lock_irq(&chip->reg_lock);
534  oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
535  oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
536 
537  if (substream->runtime->no_period_wakeup)
538  chip->interrupt_mask &= ~channel_mask;
539  else
540  chip->interrupt_mask |= channel_mask;
541  oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
542  spin_unlock_irq(&chip->reg_lock);
543  return 0;
544 }
545 
546 static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd)
547 {
548  struct oxygen *chip = snd_pcm_substream_chip(substream);
549  struct snd_pcm_substream *s;
550  unsigned int mask = 0;
551  int pausing;
552 
553  switch (cmd) {
554  case SNDRV_PCM_TRIGGER_STOP:
555  case SNDRV_PCM_TRIGGER_START:
556  case SNDRV_PCM_TRIGGER_SUSPEND:
557  pausing = 0;
558  break;
559  case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
560  case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
561  pausing = 1;
562  break;
563  default:
564  return -EINVAL;
565  }
566 
567  snd_pcm_group_for_each_entry(s, substream) {
568  if (snd_pcm_substream_chip(s) == chip) {
569  mask |= 1 << oxygen_substream_channel(s);
570  snd_pcm_trigger_done(s, substream);
571  }
572  }
573 
574  spin_lock(&chip->reg_lock);
575  if (!pausing) {
576  if (cmd == SNDRV_PCM_TRIGGER_START)
577  chip->pcm_running |= mask;
578  else
579  chip->pcm_running &= ~mask;
580  oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running);
581  } else {
582  if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
583  oxygen_set_bits8(chip, OXYGEN_DMA_PAUSE, mask);
584  else
585  oxygen_clear_bits8(chip, OXYGEN_DMA_PAUSE, mask);
586  }
587  spin_unlock(&chip->reg_lock);
588  return 0;
589 }
590 
591 static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream)
592 {
593  struct oxygen *chip = snd_pcm_substream_chip(substream);
594  struct snd_pcm_runtime *runtime = substream->runtime;
595  unsigned int channel = oxygen_substream_channel(substream);
596  u32 curr_addr;
597 
598  /* no spinlock, this read should be atomic */
599  curr_addr = oxygen_read32(chip, channel_base_registers[channel]);
600  return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr);
601 }
602 
603 static struct snd_pcm_ops oxygen_rec_a_ops = {
604  .open = oxygen_rec_a_open,
605  .close = oxygen_close,
606  .ioctl = snd_pcm_lib_ioctl,
607  .hw_params = oxygen_rec_a_hw_params,
608  .hw_free = oxygen_hw_free,
609  .prepare = oxygen_prepare,
610  .trigger = oxygen_trigger,
611  .pointer = oxygen_pointer,
612 };
613 
614 static struct snd_pcm_ops oxygen_rec_b_ops = {
615  .open = oxygen_rec_b_open,
616  .close = oxygen_close,
617  .ioctl = snd_pcm_lib_ioctl,
618  .hw_params = oxygen_rec_b_hw_params,
619  .hw_free = oxygen_hw_free,
620  .prepare = oxygen_prepare,
621  .trigger = oxygen_trigger,
622  .pointer = oxygen_pointer,
623 };
624 
625 static struct snd_pcm_ops oxygen_rec_c_ops = {
626  .open = oxygen_rec_c_open,
627  .close = oxygen_close,
628  .ioctl = snd_pcm_lib_ioctl,
629  .hw_params = oxygen_rec_c_hw_params,
630  .hw_free = oxygen_hw_free,
631  .prepare = oxygen_prepare,
632  .trigger = oxygen_trigger,
633  .pointer = oxygen_pointer,
634 };
635 
636 static struct snd_pcm_ops oxygen_spdif_ops = {
637  .open = oxygen_spdif_open,
638  .close = oxygen_close,
639  .ioctl = snd_pcm_lib_ioctl,
640  .hw_params = oxygen_spdif_hw_params,
641  .hw_free = oxygen_spdif_hw_free,
642  .prepare = oxygen_prepare,
643  .trigger = oxygen_trigger,
644  .pointer = oxygen_pointer,
645 };
646 
647 static struct snd_pcm_ops oxygen_multich_ops = {
648  .open = oxygen_multich_open,
649  .close = oxygen_close,
650  .ioctl = snd_pcm_lib_ioctl,
651  .hw_params = oxygen_multich_hw_params,
652  .hw_free = oxygen_hw_free,
653  .prepare = oxygen_prepare,
654  .trigger = oxygen_trigger,
655  .pointer = oxygen_pointer,
656 };
657 
658 static struct snd_pcm_ops oxygen_ac97_ops = {
659  .open = oxygen_ac97_open,
660  .close = oxygen_close,
661  .ioctl = snd_pcm_lib_ioctl,
662  .hw_params = oxygen_hw_params,
663  .hw_free = oxygen_hw_free,
664  .prepare = oxygen_prepare,
665  .trigger = oxygen_trigger,
666  .pointer = oxygen_pointer,
667 };
668 
669 static void oxygen_pcm_free(struct snd_pcm *pcm)
670 {
671  snd_pcm_lib_preallocate_free_for_all(pcm);
672 }
673 
674 int oxygen_pcm_init(struct oxygen *chip)
675 {
676  struct snd_pcm *pcm;
677  int outs, ins;
678  int err;
679 
680  outs = !!(chip->model.device_config & PLAYBACK_0_TO_I2S);
681  ins = !!(chip->model.device_config & (CAPTURE_0_FROM_I2S_1 |
682  CAPTURE_0_FROM_I2S_2));
683  if (outs | ins) {
684  err = snd_pcm_new(chip->card, "Multichannel",
685  0, outs, ins, &pcm);
686  if (err < 0)
687  return err;
688  if (outs)
689  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
690  &oxygen_multich_ops);
691  if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
692  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
693  &oxygen_rec_a_ops);
694  else if (chip->model.device_config & CAPTURE_0_FROM_I2S_2)
695  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
696  &oxygen_rec_b_ops);
697  pcm->private_data = chip;
698  pcm->private_free = oxygen_pcm_free;
699  strcpy(pcm->name, "Multichannel");
700  if (outs)
701  snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
702  SNDRV_DMA_TYPE_DEV,
703  snd_dma_pci_data(chip->pci),
704  DEFAULT_BUFFER_BYTES_MULTICH,
705  BUFFER_BYTES_MAX_MULTICH);
706  if (ins)
707  snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
708  SNDRV_DMA_TYPE_DEV,
709  snd_dma_pci_data(chip->pci),
710  DEFAULT_BUFFER_BYTES,
711  BUFFER_BYTES_MAX);
712  }
713 
714  outs = !!(chip->model.device_config & PLAYBACK_1_TO_SPDIF);
715  ins = !!(chip->model.device_config & CAPTURE_1_FROM_SPDIF);
716  if (outs | ins) {
717  err = snd_pcm_new(chip->card, "Digital", 1, outs, ins, &pcm);
718  if (err < 0)
719  return err;
720  if (outs)
721  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
722  &oxygen_spdif_ops);
723  if (ins)
724  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
725  &oxygen_rec_c_ops);
726  pcm->private_data = chip;
727  pcm->private_free = oxygen_pcm_free;
728  strcpy(pcm->name, "Digital");
729  snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
730  snd_dma_pci_data(chip->pci),
731  DEFAULT_BUFFER_BYTES,
732  BUFFER_BYTES_MAX);
733  }
734 
735  if (chip->has_ac97_1) {
736  outs = !!(chip->model.device_config & PLAYBACK_2_TO_AC97_1);
737  ins = !!(chip->model.device_config & CAPTURE_2_FROM_AC97_1);
738  } else {
739  outs = 0;
740  ins = !!(chip->model.device_config & CAPTURE_2_FROM_I2S_2);
741  }
742  if (outs | ins) {
743  err = snd_pcm_new(chip->card, outs ? "AC97" : "Analog2",
744  2, outs, ins, &pcm);
745  if (err < 0)
746  return err;
747  if (outs) {
748  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
749  &oxygen_ac97_ops);
750  oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
751  OXYGEN_REC_B_ROUTE_AC97_1,
752  OXYGEN_REC_B_ROUTE_MASK);
753  }
754  if (ins)
755  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
756  &oxygen_rec_b_ops);
757  pcm->private_data = chip;
758  pcm->private_free = oxygen_pcm_free;
759  strcpy(pcm->name, outs ? "Front Panel" : "Analog 2");
760  snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
761  snd_dma_pci_data(chip->pci),
762  DEFAULT_BUFFER_BYTES,
763  BUFFER_BYTES_MAX);
764  }
765  return 0;
766 }
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