Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
pgtable-32.h
Go to the documentation of this file.
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License. See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
7  * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
8  */
9 #ifndef _ASM_PGTABLE_32_H
10 #define _ASM_PGTABLE_32_H
11 
12 #include <asm/addrspace.h>
13 #include <asm/page.h>
14 
15 #include <linux/linkage.h>
16 #include <asm/cachectl.h>
17 #include <asm/fixmap.h>
18 
19 #include <asm-generic/pgtable-nopmd.h>
20 
21 /*
22  * Basically we have the same two-level (which is the logical three level
23  * Linux page table layout folded) page tables as the i386. Some day
24  * when we have proper page coloring support we can have a 1% quicker
25  * tlb refill handling mechanism, but for now it is a bit slower but
26  * works even with the cache aliasing problem the R4k and above have.
27  */
28 
29 /* PGDIR_SHIFT determines what a third-level page table entry can map */
30 #define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
31 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
32 #define PGDIR_MASK (~(PGDIR_SIZE-1))
33 
34 /*
35  * Entries per page directory level: we use two-level, so
36  * we don't really have any PUD/PMD directory physically.
37  */
38 #define __PGD_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
39 #define PGD_ORDER (__PGD_ORDER >= 0 ? __PGD_ORDER : 0)
40 #define PUD_ORDER aieeee_attempt_to_allocate_pud
41 #define PMD_ORDER 1
42 #define PTE_ORDER 0
43 
44 #define PTRS_PER_PGD (USER_PTRS_PER_PGD * 2)
45 #define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
46 
47 #define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
48 #define FIRST_USER_ADDRESS 0
49 
50 #define VMALLOC_START MAP_BASE
51 
52 #define PKMAP_BASE (0xfe000000UL)
53 
54 #ifdef CONFIG_HIGHMEM
55 # define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
56 #else
57 # define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
58 #endif
59 
60 #ifdef CONFIG_64BIT_PHYS_ADDR
61 #define pte_ERROR(e) \
62  printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
63 #else
64 #define pte_ERROR(e) \
65  printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
66 #endif
67 #define pgd_ERROR(e) \
68  printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
69 
70 extern void load_pgd(unsigned long pg_dir);
71 
72 extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
73 
74 /*
75  * Empty pgd/pmd entries point to the invalid_pte_table.
76  */
77 static inline int pmd_none(pmd_t pmd)
78 {
79  return pmd_val(pmd) == (unsigned long) invalid_pte_table;
80 }
81 
82 #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
83 
84 static inline int pmd_present(pmd_t pmd)
85 {
86  return pmd_val(pmd) != (unsigned long) invalid_pte_table;
87 }
88 
89 static inline void pmd_clear(pmd_t *pmdp)
90 {
91  pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
92 }
93 
94 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
95 #define pte_page(x) pfn_to_page(pte_pfn(x))
96 #define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
97 static inline pte_t
98 pfn_pte(unsigned long pfn, pgprot_t prot)
99 {
100  pte_t pte;
101  pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
102  pte.pte_low = pgprot_val(prot);
103  return pte;
104 }
105 
106 #else
107 
108 #define pte_page(x) pfn_to_page(pte_pfn(x))
109 
110 #ifdef CONFIG_CPU_VR41XX
111 #define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
112 #define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
113 #else
114 #define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT))
115 #define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))
116 #endif
117 #endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
118 
119 #define __pgd_offset(address) pgd_index(address)
120 #define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
121 #define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
122 
123 /* to find an entry in a kernel page-table-directory */
124 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
125 
126 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
127 
128 /* to find an entry in a page-table-directory */
129 #define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
130 
131 /* Find an entry in the third-level page table.. */
132 #define __pte_offset(address) \
133  (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
134 #define pte_offset(dir, address) \
135  ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
136 #define pte_offset_kernel(dir, address) \
137  ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
138 
139 #define pte_offset_map(dir, address) \
140  ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
141 #define pte_unmap(pte) ((void)(pte))
142 
143 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
144 
145 /* Swap entries must have VALID bit cleared. */
146 #define __swp_type(x) (((x).val >> 10) & 0x1f)
147 #define __swp_offset(x) ((x).val >> 15)
148 #define __swp_entry(type,offset) \
149  ((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
150 
151 /*
152  * Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range:
153  */
154 #define PTE_FILE_MAX_BITS 28
155 
156 #define pte_to_pgoff(_pte) ((((_pte).pte >> 1 ) & 0x07) | \
157  (((_pte).pte >> 2 ) & 0x38) | \
158  (((_pte).pte >> 10) << 6 ))
159 
160 #define pgoff_to_pte(off) ((pte_t) { (((off) & 0x07) << 1 ) | \
161  (((off) & 0x38) << 2 ) | \
162  (((off) >> 6 ) << 10) | \
163  _PAGE_FILE })
164 
165 #else
166 
167 /* Swap entries must have VALID and GLOBAL bits cleared. */
168 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
169 #define __swp_type(x) (((x).val >> 2) & 0x1f)
170 #define __swp_offset(x) ((x).val >> 7)
171 #define __swp_entry(type,offset) \
172  ((swp_entry_t) { ((type) << 2) | ((offset) << 7) })
173 #else
174 #define __swp_type(x) (((x).val >> 8) & 0x1f)
175 #define __swp_offset(x) ((x).val >> 13)
176 #define __swp_entry(type,offset) \
177  ((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
178 #endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
179 
180 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
181 /*
182  * Bits 0 and 1 of pte_high are taken, use the rest for the page offset...
183  */
184 #define PTE_FILE_MAX_BITS 30
185 
186 #define pte_to_pgoff(_pte) ((_pte).pte_high >> 2)
187 #define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) << 2 })
188 
189 #else
190 /*
191  * Bits 0, 4, 6, and 7 are taken, split up 28 bits of offset into this range:
192  */
193 #define PTE_FILE_MAX_BITS 28
194 
195 #define pte_to_pgoff(_pte) ((((_pte).pte >> 1) & 0x7) | \
196  (((_pte).pte >> 2) & 0x8) | \
197  (((_pte).pte >> 8) << 4))
198 
199 #define pgoff_to_pte(off) ((pte_t) { (((off) & 0x7) << 1) | \
200  (((off) & 0x8) << 2) | \
201  (((off) >> 4) << 8) | \
202  _PAGE_FILE })
203 #endif
204 
205 #endif
206 
207 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
208 #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
209 #define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
210 #else
211 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
212 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
213 #endif
214 
215 #endif /* _ASM_PGTABLE_32_H */
Generated on Thu Jan 10 2013 13:10:50 for Linux Kernel by   doxygen 1.8.2