20 static const u32 frame_struct_rev0[] = {
855 static const u8 frame_lut_rev0[] = {
890 static const u32 tmap_tbl_rev0[] = {
1341 static const u32 tdtrn_tbl_rev0[] = {
2048 static const u32 intlv_tbl_rev0[] = {
2058 static const u16 pilot_tbl_rev0[] = {
2149 static const u32 pltlut_tbl_rev0[] = {
2158 static const u32 tdi_tbl20_ant0_rev0[] = {
2216 static const u32 tdi_tbl20_ant1_rev0[] = {
2274 static const u32 tdi_tbl40_ant0_rev0[] = {
2387 static const u32 tdi_tbl40_ant1_rev0[] = {
2500 static const u16 bdi_tbl_rev0[] = {
2509 static const u32 chanest_tbl_rev0[] = {
2608 static const u8 mcs_tbl_rev0[] = {
2739 static const u32 noise_var_tbl0_rev0[] = {
2998 static const u32 noise_var_tbl1_rev0[] = {
3257 static const u8 est_pwr_lut_core0_rev0[] = {
3324 static const u8 est_pwr_lut_core1_rev0[] = {
3391 static const u8 adj_pwr_lut_core0_rev0[] = {
3522 static const u8 adj_pwr_lut_core1_rev0[] = {
3653 static const u32 gainctrl_lut_core0_rev0[] = {
3784 static const u32 gainctrl_lut_core1_rev0[] = {
3915 static const u32 iq_lut_core0_rev0[] = {
4046 static const u32 iq_lut_core1_rev0[] = {
4177 static const u16 loft_lut_core0_rev0[] = {
4308 static const u16 loft_lut_core1_rev0[] = {
4440 {&bdi_tbl_rev0,
sizeof(bdi_tbl_rev0) /
sizeof(bdi_tbl_rev0[0]), 21, 0,
4443 {&pltlut_tbl_rev0,
sizeof(pltlut_tbl_rev0) /
sizeof(pltlut_tbl_rev0[0]),
4446 {&gainctrl_lut_core0_rev0,
4447 sizeof(gainctrl_lut_core0_rev0) /
sizeof(gainctrl_lut_core0_rev0[0]),
4450 {&gainctrl_lut_core1_rev0,
4451 sizeof(gainctrl_lut_core1_rev0) /
sizeof(gainctrl_lut_core1_rev0[0]),
4455 {&est_pwr_lut_core0_rev0,
4456 sizeof(est_pwr_lut_core0_rev0) /
sizeof(est_pwr_lut_core0_rev0[0]), 26,
4459 {&est_pwr_lut_core1_rev0,
4460 sizeof(est_pwr_lut_core1_rev0) /
sizeof(est_pwr_lut_core1_rev0[0]), 27,
4463 {&adj_pwr_lut_core0_rev0,
4464 sizeof(adj_pwr_lut_core0_rev0) /
sizeof(adj_pwr_lut_core0_rev0[0]), 26,
4467 {&adj_pwr_lut_core1_rev0,
4468 sizeof(adj_pwr_lut_core1_rev0) /
sizeof(adj_pwr_lut_core1_rev0[0]), 27,
4471 {&iq_lut_core0_rev0,
4472 sizeof(iq_lut_core0_rev0) /
sizeof(iq_lut_core0_rev0[0]), 26, 320, 32}
4474 {&iq_lut_core1_rev0,
4475 sizeof(iq_lut_core1_rev0) /
sizeof(iq_lut_core1_rev0[0]), 27, 320, 32}
4477 {&loft_lut_core0_rev0,
4478 sizeof(loft_lut_core0_rev0) /
sizeof(loft_lut_core0_rev0[0]), 26, 448,
4481 {&loft_lut_core1_rev0,
4482 sizeof(loft_lut_core1_rev0) /
sizeof(loft_lut_core1_rev0[0]), 27, 448,
4488 {&frame_struct_rev0,
4489 sizeof(frame_struct_rev0) /
sizeof(frame_struct_rev0[0]), 10, 0, 32}
4491 {&frame_lut_rev0,
sizeof(frame_lut_rev0) /
sizeof(frame_lut_rev0[0]),
4494 {&tmap_tbl_rev0,
sizeof(tmap_tbl_rev0) /
sizeof(tmap_tbl_rev0[0]), 12,
4497 {&tdtrn_tbl_rev0,
sizeof(tdtrn_tbl_rev0) /
sizeof(tdtrn_tbl_rev0[0]),
4500 {&intlv_tbl_rev0,
sizeof(intlv_tbl_rev0) /
sizeof(intlv_tbl_rev0[0]),
4503 {&pilot_tbl_rev0,
sizeof(pilot_tbl_rev0) /
sizeof(pilot_tbl_rev0[0]),
4506 {&tdi_tbl20_ant0_rev0,
4507 sizeof(tdi_tbl20_ant0_rev0) /
sizeof(tdi_tbl20_ant0_rev0[0]), 19, 128,
4510 {&tdi_tbl20_ant1_rev0,
4511 sizeof(tdi_tbl20_ant1_rev0) /
sizeof(tdi_tbl20_ant1_rev0[0]), 19, 256,
4514 {&tdi_tbl40_ant0_rev0,
4515 sizeof(tdi_tbl40_ant0_rev0) /
sizeof(tdi_tbl40_ant0_rev0[0]), 19, 640,
4518 {&tdi_tbl40_ant1_rev0,
4519 sizeof(tdi_tbl40_ant1_rev0) /
sizeof(tdi_tbl40_ant1_rev0[0]), 19, 768,
4523 sizeof(chanest_tbl_rev0) /
sizeof(chanest_tbl_rev0[0]), 22, 0, 32}
4525 {&mcs_tbl_rev0,
sizeof(mcs_tbl_rev0) /
sizeof(mcs_tbl_rev0[0]), 18, 0,
4528 {&noise_var_tbl0_rev0,
4529 sizeof(noise_var_tbl0_rev0) /
sizeof(noise_var_tbl0_rev0[0]), 16, 0,
4532 {&noise_var_tbl1_rev0,
4533 sizeof(noise_var_tbl1_rev0) /
sizeof(noise_var_tbl1_rev0[0]), 16, 128,
4542 sizeof(mimophytbl_info_rev0_volatile[0]);
4544 static const u16 ant_swctrl_tbl_rev3[] = {
4579 static const u16 ant_swctrl_tbl_rev3_1[] = {
4614 static const u16 ant_swctrl_tbl_rev3_2[] = {
4649 static const u16 ant_swctrl_tbl_rev3_3[] = {
4684 static const u32 frame_struct_rev3[] = {
5519 static const u16 pilot_tbl_rev3[] = {
5610 static const u32 tmap_tbl_rev3[] = {
6061 static const u32 intlv_tbl_rev3[] = {
6071 static const u32 tdtrn_tbl_rev3[] = {
7037 static const u16 mcs_tbl_rev3[] = {
7168 static const u32 tdi_tbl20_ant0_rev3[] = {
7226 static const u32 tdi_tbl20_ant1_rev3[] = {
7284 static const u32 tdi_tbl40_ant0_rev3[] = {
7397 static const u32 tdi_tbl40_ant1_rev3[] = {
7510 static const u32 pltlut_tbl_rev3[] = {
7519 static const u32 chanest_tbl_rev3[] = {
7618 static const u8 frame_lut_rev3[] = {
7653 static const u8 est_pwr_lut_core0_rev3[] = {
7720 static const u8 est_pwr_lut_core1_rev3[] = {
7787 static const u8 adj_pwr_lut_core0_rev3[] = {
7918 static const u8 adj_pwr_lut_core1_rev3[] = {
8049 static const u32 gainctrl_lut_core0_rev3[] = {
8180 static const u32 gainctrl_lut_core1_rev3[] = {
8311 static const u32 iq_lut_core0_rev3[] = {
8442 static const u32 iq_lut_core1_rev3[] = {
8573 static const u16 loft_lut_core0_rev3[] = {
8704 static const u16 loft_lut_core1_rev3[] = {
8835 static const u16 papd_comp_rfpwr_tbl_core0_rev3[] = {
8966 static const u16 papd_comp_rfpwr_tbl_core1_rev3[] = {
9097 static const u32 papd_comp_epsilon_tbl_core0_rev3[] = {
9164 static const u32 papd_cal_scalars_tbl_core0_rev3[] = {
9231 static const u32 papd_comp_epsilon_tbl_core1_rev3[] = {
9298 static const u32 papd_cal_scalars_tbl_core1_rev3[] = {
9366 {&ant_swctrl_tbl_rev3,
9367 sizeof(ant_swctrl_tbl_rev3) /
sizeof(ant_swctrl_tbl_rev3[0]), 9, 0, 16}
9372 {&ant_swctrl_tbl_rev3_1,
9373 sizeof(ant_swctrl_tbl_rev3_1) /
sizeof(ant_swctrl_tbl_rev3_1[0]), 9, 0,
9379 {&ant_swctrl_tbl_rev3_2,
9380 sizeof(ant_swctrl_tbl_rev3_2) /
sizeof(ant_swctrl_tbl_rev3_2[0]), 9, 0,
9386 {&ant_swctrl_tbl_rev3_3,
9387 sizeof(ant_swctrl_tbl_rev3_3) /
sizeof(ant_swctrl_tbl_rev3_3[0]), 9, 0,
9393 {&frame_struct_rev3,
9394 sizeof(frame_struct_rev3) /
sizeof(frame_struct_rev3[0]), 10, 0, 32}
9396 {&pilot_tbl_rev3,
sizeof(pilot_tbl_rev3) /
sizeof(pilot_tbl_rev3[0]),
9399 {&tmap_tbl_rev3,
sizeof(tmap_tbl_rev3) /
sizeof(tmap_tbl_rev3[0]), 12,
9402 {&intlv_tbl_rev3,
sizeof(intlv_tbl_rev3) /
sizeof(intlv_tbl_rev3[0]),
9405 {&tdtrn_tbl_rev3,
sizeof(tdtrn_tbl_rev3) /
sizeof(tdtrn_tbl_rev3[0]),
9411 {&mcs_tbl_rev3,
sizeof(mcs_tbl_rev3) /
sizeof(mcs_tbl_rev3[0]), 18, 0,
9414 {&tdi_tbl20_ant0_rev3,
9415 sizeof(tdi_tbl20_ant0_rev3) /
sizeof(tdi_tbl20_ant0_rev3[0]), 19, 128,
9418 {&tdi_tbl20_ant1_rev3,
9419 sizeof(tdi_tbl20_ant1_rev3) /
sizeof(tdi_tbl20_ant1_rev3[0]), 19, 256,
9422 {&tdi_tbl40_ant0_rev3,
9423 sizeof(tdi_tbl40_ant0_rev3) /
sizeof(tdi_tbl40_ant0_rev3[0]), 19, 640,
9426 {&tdi_tbl40_ant1_rev3,
9427 sizeof(tdi_tbl40_ant1_rev3) /
sizeof(tdi_tbl40_ant1_rev3[0]), 19, 768,
9430 {&pltlut_tbl_rev3,
sizeof(pltlut_tbl_rev3) /
sizeof(pltlut_tbl_rev3[0]),
9434 sizeof(chanest_tbl_rev3) /
sizeof(chanest_tbl_rev3[0]), 22, 0, 32}
9436 {&frame_lut_rev3,
sizeof(frame_lut_rev3) /
sizeof(frame_lut_rev3[0]),
9439 {&est_pwr_lut_core0_rev3,
9440 sizeof(est_pwr_lut_core0_rev3) /
sizeof(est_pwr_lut_core0_rev3[0]), 26,
9443 {&est_pwr_lut_core1_rev3,
9444 sizeof(est_pwr_lut_core1_rev3) /
sizeof(est_pwr_lut_core1_rev3[0]), 27,
9447 {&adj_pwr_lut_core0_rev3,
9448 sizeof(adj_pwr_lut_core0_rev3) /
sizeof(adj_pwr_lut_core0_rev3[0]), 26,
9451 {&adj_pwr_lut_core1_rev3,
9452 sizeof(adj_pwr_lut_core1_rev3) /
sizeof(adj_pwr_lut_core1_rev3[0]), 27,
9455 {&gainctrl_lut_core0_rev3,
9456 sizeof(gainctrl_lut_core0_rev3) /
sizeof(gainctrl_lut_core0_rev3[0]),
9459 {&gainctrl_lut_core1_rev3,
9460 sizeof(gainctrl_lut_core1_rev3) /
sizeof(gainctrl_lut_core1_rev3[0]),
9463 {&iq_lut_core0_rev3,
9464 sizeof(iq_lut_core0_rev3) /
sizeof(iq_lut_core0_rev3[0]), 26, 320, 32}
9466 {&iq_lut_core1_rev3,
9467 sizeof(iq_lut_core1_rev3) /
sizeof(iq_lut_core1_rev3[0]), 27, 320, 32}
9469 {&loft_lut_core0_rev3,
9470 sizeof(loft_lut_core0_rev3) /
sizeof(loft_lut_core0_rev3[0]), 26, 448,
9473 {&loft_lut_core1_rev3,
9474 sizeof(loft_lut_core1_rev3) /
sizeof(loft_lut_core1_rev3[0]), 27, 448,
9482 sizeof(mimophytbl_info_rev3_volatile[0]);
9485 sizeof(mimophytbl_info_rev3_volatile1[0]);
9488 sizeof(mimophytbl_info_rev3_volatile2[0]);
9491 sizeof(mimophytbl_info_rev3_volatile3[0]);
9493 static const u32 tmap_tbl_rev7[] = {
10203 static const u32 papd_comp_epsilon_tbl_core0_rev7[] = {
10270 static const u32 papd_cal_scalars_tbl_core0_rev7[] = {
10337 static const u32 papd_comp_epsilon_tbl_core1_rev7[] = {
10404 static const u32 papd_cal_scalars_tbl_core1_rev7[] = {
10472 {&frame_struct_rev3,
10473 sizeof(frame_struct_rev3) /
sizeof(frame_struct_rev3[0]), 10, 0, 32}
10475 {&pilot_tbl_rev3,
sizeof(pilot_tbl_rev3) /
sizeof(pilot_tbl_rev3[0]),
10478 {&tmap_tbl_rev7,
sizeof(tmap_tbl_rev7) /
sizeof(tmap_tbl_rev7[0]), 12,
10481 {&intlv_tbl_rev3,
sizeof(intlv_tbl_rev3) /
sizeof(intlv_tbl_rev3[0]),
10484 {&tdtrn_tbl_rev3,
sizeof(tdtrn_tbl_rev3) /
sizeof(tdtrn_tbl_rev3[0]),
10490 {&mcs_tbl_rev3,
sizeof(mcs_tbl_rev3) /
sizeof(mcs_tbl_rev3[0]), 18, 0,
10493 {&tdi_tbl20_ant0_rev3,
10494 sizeof(tdi_tbl20_ant0_rev3) /
sizeof(tdi_tbl20_ant0_rev3[0]), 19, 128,
10497 {&tdi_tbl20_ant1_rev3,
10498 sizeof(tdi_tbl20_ant1_rev3) /
sizeof(tdi_tbl20_ant1_rev3[0]), 19, 256,
10501 {&tdi_tbl40_ant0_rev3,
10502 sizeof(tdi_tbl40_ant0_rev3) /
sizeof(tdi_tbl40_ant0_rev3[0]), 19, 640,
10505 {&tdi_tbl40_ant1_rev3,
10506 sizeof(tdi_tbl40_ant1_rev3) /
sizeof(tdi_tbl40_ant1_rev3[0]), 19, 768,
10509 {&pltlut_tbl_rev3,
sizeof(pltlut_tbl_rev3) /
sizeof(pltlut_tbl_rev3[0]),
10512 {&chanest_tbl_rev3,
10513 sizeof(chanest_tbl_rev3) /
sizeof(chanest_tbl_rev3[0]), 22, 0, 32}
10515 {&frame_lut_rev3,
sizeof(frame_lut_rev3) /
sizeof(frame_lut_rev3[0]),
10518 {&est_pwr_lut_core0_rev3,
10519 sizeof(est_pwr_lut_core0_rev3) /
sizeof(est_pwr_lut_core0_rev3[0]), 26,
10522 {&est_pwr_lut_core1_rev3,
10523 sizeof(est_pwr_lut_core1_rev3) /
sizeof(est_pwr_lut_core1_rev3[0]), 27,
10526 {&adj_pwr_lut_core0_rev3,
10527 sizeof(adj_pwr_lut_core0_rev3) /
sizeof(adj_pwr_lut_core0_rev3[0]), 26,
10530 {&adj_pwr_lut_core1_rev3,
10531 sizeof(adj_pwr_lut_core1_rev3) /
sizeof(adj_pwr_lut_core1_rev3[0]), 27,
10534 {&gainctrl_lut_core0_rev3,
10535 sizeof(gainctrl_lut_core0_rev3) /
sizeof(gainctrl_lut_core0_rev3[0]),
10538 {&gainctrl_lut_core1_rev3,
10539 sizeof(gainctrl_lut_core1_rev3) /
sizeof(gainctrl_lut_core1_rev3[0]),
10542 {&iq_lut_core0_rev3,
10543 sizeof(iq_lut_core0_rev3) /
sizeof(iq_lut_core0_rev3[0]), 26, 320, 32}
10545 {&iq_lut_core1_rev3,
10546 sizeof(iq_lut_core1_rev3) /
sizeof(iq_lut_core1_rev3[0]), 27, 320, 32}
10548 {&loft_lut_core0_rev3,
10549 sizeof(loft_lut_core0_rev3) /
sizeof(loft_lut_core0_rev3[0]), 26, 448,
10552 {&loft_lut_core1_rev3,
10553 sizeof(loft_lut_core1_rev3) /
sizeof(loft_lut_core1_rev3[0]), 27, 448,
10556 {&papd_comp_rfpwr_tbl_core0_rev3,
10557 sizeof(papd_comp_rfpwr_tbl_core0_rev3) /
10558 sizeof(papd_comp_rfpwr_tbl_core0_rev3[0]), 26, 576, 16}
10560 {&papd_comp_rfpwr_tbl_core1_rev3,
10561 sizeof(papd_comp_rfpwr_tbl_core1_rev3) /
10562 sizeof(papd_comp_rfpwr_tbl_core1_rev3[0]), 27, 576, 16}
10564 {&papd_comp_epsilon_tbl_core0_rev7,
10565 sizeof(papd_comp_epsilon_tbl_core0_rev7) /
10566 sizeof(papd_comp_epsilon_tbl_core0_rev7[0]), 31, 0, 32}
10568 {&papd_cal_scalars_tbl_core0_rev7,
10569 sizeof(papd_cal_scalars_tbl_core0_rev7) /
10570 sizeof(papd_cal_scalars_tbl_core0_rev7[0]), 32, 0, 32}
10572 {&papd_comp_epsilon_tbl_core1_rev7,
10573 sizeof(papd_comp_epsilon_tbl_core1_rev7) /
10574 sizeof(papd_comp_epsilon_tbl_core1_rev7[0]), 33, 0, 32}
10576 {&papd_cal_scalars_tbl_core1_rev7,
10577 sizeof(papd_cal_scalars_tbl_core1_rev7) /
10578 sizeof(papd_cal_scalars_tbl_core1_rev7[0]), 34, 0, 32}
10589 {&est_pwr_lut_core0_rev3,
10590 sizeof(est_pwr_lut_core0_rev3) /
sizeof(est_pwr_lut_core0_rev3[0]), 26,
10593 {&est_pwr_lut_core1_rev3,
10594 sizeof(est_pwr_lut_core1_rev3) /
sizeof(est_pwr_lut_core1_rev3[0]), 27,
10597 {&adj_pwr_lut_core0_rev3,
10598 sizeof(adj_pwr_lut_core0_rev3) /
sizeof(adj_pwr_lut_core0_rev3[0]), 26,
10601 {&adj_pwr_lut_core1_rev3,
10602 sizeof(adj_pwr_lut_core1_rev3) /
sizeof(adj_pwr_lut_core1_rev3[0]), 27,
10605 {&gainctrl_lut_core0_rev3,
10606 sizeof(gainctrl_lut_core0_rev3) /
sizeof(gainctrl_lut_core0_rev3[0]),
10609 {&gainctrl_lut_core1_rev3,
10610 sizeof(gainctrl_lut_core1_rev3) /
sizeof(gainctrl_lut_core1_rev3[0]),
10613 {&iq_lut_core0_rev3,
10614 sizeof(iq_lut_core0_rev3) /
sizeof(iq_lut_core0_rev3[0]), 26, 320, 32}
10616 {&iq_lut_core1_rev3,
10617 sizeof(iq_lut_core1_rev3) /
sizeof(iq_lut_core1_rev3[0]), 27, 320, 32}
10619 {&loft_lut_core0_rev3,
10620 sizeof(loft_lut_core0_rev3) /
sizeof(loft_lut_core0_rev3[0]), 26, 448,
10623 {&loft_lut_core1_rev3,
10624 sizeof(loft_lut_core1_rev3) /
sizeof(loft_lut_core1_rev3[0]), 27, 448,