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pi1.h
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1 /*
2  * pi1.h: Definitions for SGI PI1 parallel port
3  */
4 
5 #ifndef _SGI_PI1_H
6 #define _SGI_PI1_H
7 
8 struct pi1_regs {
9  u8 _data[3];
10  volatile u8 data;
11  u8 _ctrl[3];
12  volatile u8 ctrl;
13 #define PI1_CTRL_STROBE_N 0x01
14 #define PI1_CTRL_AFD_N 0x02
15 #define PI1_CTRL_INIT_N 0x04
16 #define PI1_CTRL_SLIN_N 0x08
17 #define PI1_CTRL_IRQ_ENA 0x10
18 #define PI1_CTRL_DIR 0x20
19 #define PI1_CTRL_SEL 0x40
20  u8 _status[3];
21  volatile u8 status;
22 #define PI1_STAT_DEVID 0x03 /* bits 0-1 */
23 #define PI1_STAT_NOINK 0x04 /* SGI MODE only */
24 #define PI1_STAT_ERROR 0x08
25 #define PI1_STAT_ONLINE 0x10
26 #define PI1_STAT_PE 0x20
27 #define PI1_STAT_ACK 0x40
28 #define PI1_STAT_BUSY 0x80
30  volatile u8 dmactrl;
31 #define PI1_DMACTRL_FIFO_EMPTY 0x01 /* fifo empty R/O */
32 #define PI1_DMACTRL_ABORT 0x02 /* reset DMA and internal fifo W/O */
33 #define PI1_DMACTRL_STDMODE 0x00 /* bits 2-3 */
34 #define PI1_DMACTRL_SGIMODE 0x04 /* bits 2-3 */
35 #define PI1_DMACTRL_RICOHMODE 0x08 /* bits 2-3 */
36 #define PI1_DMACTRL_HPMODE 0x0c /* bits 2-3 */
37 #define PI1_DMACTRL_BLKMODE 0x10 /* block mode */
38 #define PI1_DMACTRL_FIFO_CLEAR 0x20 /* clear fifo W/O */
39 #define PI1_DMACTRL_READ 0x40 /* read */
40 #define PI1_DMACTRL_RUN 0x80 /* pedal to the metal */
42  volatile u8 intstat;
43 #define PI1_INTSTAT_ACK 0x04
44 #define PI1_INTSTAT_FEMPTY 0x08
45 #define PI1_INTSTAT_NOINK 0x10
46 #define PI1_INTSTAT_ONLINE 0x20
47 #define PI1_INTSTAT_ERR 0x40
48 #define PI1_INTSTAT_PE 0x80
50  volatile u8 intmask; /* enabled low, reset high*/
51 #define PI1_INTMASK_ACK 0x04
52 #define PI1_INTMASK_FIFO_EMPTY 0x08
53 #define PI1_INTMASK_NOINK 0x10
54 #define PI1_INTMASK_ONLINE 0x20
55 #define PI1_INTMASK_ERR 0x40
56 #define PI1_INTMASK_PE 0x80
57  u8 _timer1[3];
58  volatile u8 timer1;
59 #define PI1_TIME1 0x27
60  u8 _timer2[3];
61  volatile u8 timer2;
62 #define PI1_TIME2 0x13
63  u8 _timer3[3];
64  volatile u8 timer3;
65 #define PI1_TIME3 0x10
66  u8 _timer4[3];
67  volatile u8 timer4;
68 #define PI1_TIME4 0x00
69 };
70 
71 #endif