Go to the documentation of this file.
15 #define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
50 #ifndef REG_RD_INT_VECT
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
63 #define REG_TYPE_CONV( type, orgtype, val ) \
64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68 #define reg_page_size 8192
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
86 #define REG_RD_ADDR_pio_rw_data 64
87 #define REG_WR_ADDR_pio_rw_data 64
92 unsigned int dummy1 : 24;
94 #define REG_RD_ADDR_pio_rw_io_access0 0
95 #define REG_WR_ADDR_pio_rw_io_access0 0
100 unsigned int dummy1 : 24;
102 #define REG_RD_ADDR_pio_rw_io_access1 4
103 #define REG_WR_ADDR_pio_rw_io_access1 4
108 unsigned int dummy1 : 24;
110 #define REG_RD_ADDR_pio_rw_io_access2 8
111 #define REG_WR_ADDR_pio_rw_io_access2 8
116 unsigned int dummy1 : 24;
118 #define REG_RD_ADDR_pio_rw_io_access3 12
119 #define REG_WR_ADDR_pio_rw_io_access3 12
124 unsigned int dummy1 : 24;
126 #define REG_RD_ADDR_pio_rw_io_access4 16
127 #define REG_WR_ADDR_pio_rw_io_access4 16
132 unsigned int dummy1 : 24;
134 #define REG_RD_ADDR_pio_rw_io_access5 20
135 #define REG_WR_ADDR_pio_rw_io_access5 20
140 unsigned int dummy1 : 24;
142 #define REG_RD_ADDR_pio_rw_io_access6 24
143 #define REG_WR_ADDR_pio_rw_io_access6 24
148 unsigned int dummy1 : 24;
150 #define REG_RD_ADDR_pio_rw_io_access7 28
151 #define REG_WR_ADDR_pio_rw_io_access7 28
156 unsigned int dummy1 : 24;
158 #define REG_RD_ADDR_pio_rw_io_access8 32
159 #define REG_WR_ADDR_pio_rw_io_access8 32
164 unsigned int dummy1 : 24;
166 #define REG_RD_ADDR_pio_rw_io_access9 36
167 #define REG_WR_ADDR_pio_rw_io_access9 36
172 unsigned int dummy1 : 24;
174 #define REG_RD_ADDR_pio_rw_io_access10 40
175 #define REG_WR_ADDR_pio_rw_io_access10 40
180 unsigned int dummy1 : 24;
182 #define REG_RD_ADDR_pio_rw_io_access11 44
183 #define REG_WR_ADDR_pio_rw_io_access11 44
188 unsigned int dummy1 : 24;
190 #define REG_RD_ADDR_pio_rw_io_access12 48
191 #define REG_WR_ADDR_pio_rw_io_access12 48
196 unsigned int dummy1 : 24;
198 #define REG_RD_ADDR_pio_rw_io_access13 52
199 #define REG_WR_ADDR_pio_rw_io_access13 52
204 unsigned int dummy1 : 24;
206 #define REG_RD_ADDR_pio_rw_io_access14 56
207 #define REG_WR_ADDR_pio_rw_io_access14 56
212 unsigned int dummy1 : 24;
214 #define REG_RD_ADDR_pio_rw_io_access15 60
215 #define REG_WR_ADDR_pio_rw_io_access15 60
224 unsigned int dummy1 : 16;
226 #define REG_RD_ADDR_pio_rw_ce0_cfg 68
227 #define REG_WR_ADDR_pio_rw_ce0_cfg 68
236 unsigned int dummy1 : 16;
238 #define REG_RD_ADDR_pio_rw_ce1_cfg 72
239 #define REG_WR_ADDR_pio_rw_ce1_cfg 72
248 unsigned int dummy1 : 16;
250 #define REG_RD_ADDR_pio_rw_ce2_cfg 76
251 #define REG_WR_ADDR_pio_rw_ce2_cfg 76
256 unsigned int rd_n : 1;
257 unsigned int wr_n : 1;
260 unsigned int ce0_n : 1;
261 unsigned int ce1_n : 1;
262 unsigned int ce2_n : 1;
264 unsigned int dummy1 : 16;
266 #define REG_RD_ADDR_pio_rw_dout 80
267 #define REG_WR_ADDR_pio_rw_dout 80
272 unsigned int rd_n : 1;
273 unsigned int wr_n : 1;
276 unsigned int ce0_n : 1;
277 unsigned int ce1_n : 1;
278 unsigned int ce2_n : 1;
280 unsigned int dummy1 : 16;
282 #define REG_RD_ADDR_pio_rw_oe 84
283 #define REG_WR_ADDR_pio_rw_oe 84
288 unsigned int rd_n : 1;
289 unsigned int wr_n : 1;
292 unsigned int ce0_n : 1;
293 unsigned int ce1_n : 1;
294 unsigned int ce2_n : 1;
296 unsigned int dummy1 : 16;
298 #define REG_RD_ADDR_pio_rw_man_ctrl 88
299 #define REG_WR_ADDR_pio_rw_man_ctrl 88
304 unsigned int rd_n : 1;
305 unsigned int wr_n : 1;
308 unsigned int ce0_n : 1;
309 unsigned int ce1_n : 1;
310 unsigned int ce2_n : 1;
312 unsigned int dummy1 : 16;
314 #define REG_RD_ADDR_pio_r_din 92
319 unsigned int dummy1 : 31;
321 #define REG_RD_ADDR_pio_r_stat 96
326 unsigned int dummy1 : 31;
328 #define REG_RD_ADDR_pio_rw_intr_mask 100
329 #define REG_WR_ADDR_pio_rw_intr_mask 100
334 unsigned int dummy1 : 31;
336 #define REG_RD_ADDR_pio_rw_ack_intr 104
337 #define REG_WR_ADDR_pio_rw_ack_intr 104
342 unsigned int dummy1 : 31;
344 #define REG_RD_ADDR_pio_r_intr 108
349 unsigned int dummy1 : 31;
351 #define REG_RD_ADDR_pio_r_masked_intr 112