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cputable.h
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1 #ifndef __ASM_POWERPC_CPUTABLE_H
2 #define __ASM_POWERPC_CPUTABLE_H
3 
4 
5 #include <asm/asm-compat.h>
6 #include <asm/feature-fixups.h>
7 #include <uapi/asm/cputable.h>
8 
9 #ifndef __ASSEMBLY__
10 
11 /* This structure can grow, it's real size is used by head.S code
12  * via the mkdefs mechanism.
13  */
14 struct cpu_spec;
15 
16 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
17 typedef void (*cpu_restore_t)(void);
18 
19 enum powerpc_oprofile_type {
20  PPC_OPROFILE_INVALID = 0,
21  PPC_OPROFILE_RS64 = 1,
22  PPC_OPROFILE_POWER4 = 2,
23  PPC_OPROFILE_G4 = 3,
24  PPC_OPROFILE_FSL_EMB = 4,
25  PPC_OPROFILE_CELL = 5,
26  PPC_OPROFILE_PA6T = 6,
27 };
28 
29 enum powerpc_pmc_type {
30  PPC_PMC_DEFAULT = 0,
31  PPC_PMC_IBM = 1,
32  PPC_PMC_PA6T = 2,
33  PPC_PMC_G4 = 3,
34 };
35 
36 struct pt_regs;
37 
38 extern int machine_check_generic(struct pt_regs *regs);
39 extern int machine_check_4xx(struct pt_regs *regs);
40 extern int machine_check_440A(struct pt_regs *regs);
41 extern int machine_check_e500mc(struct pt_regs *regs);
42 extern int machine_check_e500(struct pt_regs *regs);
43 extern int machine_check_e200(struct pt_regs *regs);
44 extern int machine_check_47x(struct pt_regs *regs);
45 
46 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */
47 struct cpu_spec {
48  /* CPU is matched via (PVR & pvr_mask) == pvr_value */
49  unsigned int pvr_mask;
50  unsigned int pvr_value;
51 
52  char *cpu_name;
53  unsigned long cpu_features; /* Kernel features */
54  unsigned int cpu_user_features; /* Userland features */
55  unsigned int mmu_features; /* MMU features */
56 
57  /* cache line sizes */
58  unsigned int icache_bsize;
59  unsigned int dcache_bsize;
60 
61  /* number of performance monitor counters */
62  unsigned int num_pmcs;
63  enum powerpc_pmc_type pmc_type;
64 
65  /* this is called to initialize various CPU bits like L1 cache,
66  * BHT, SPD, etc... from head.S before branching to identify_machine
67  */
68  cpu_setup_t cpu_setup;
69  /* Used to restore cpu setup on secondary processors and at resume */
70  cpu_restore_t cpu_restore;
71 
72  /* Used by oprofile userspace to select the right counters */
73  char *oprofile_cpu_type;
74 
75  /* Processor specific oprofile operations */
76  enum powerpc_oprofile_type oprofile_type;
77 
78  /* Bit locations inside the mmcra change */
79  unsigned long oprofile_mmcra_sihv;
80  unsigned long oprofile_mmcra_sipr;
81 
82  /* Bits to clear during an oprofile exception */
83  unsigned long oprofile_mmcra_clear;
84 
85  /* Name of processor class, for the ELF AT_PLATFORM entry */
86  char *platform;
87 
88  /* Processor specific machine check handling. Return negative
89  * if the error is fatal, 1 if it was fully recovered and 0 to
90  * pass up (not CPU originated) */
91  int (*machine_check)(struct pt_regs *regs);
92 };
93 
94 extern struct cpu_spec *cur_cpu_spec;
95 
96 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
97 
98 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
99 extern void do_feature_fixups(unsigned long value, void *fixup_start,
100  void *fixup_end);
101 
102 extern const char *powerpc_base_platform;
103 
104 #endif /* __ASSEMBLY__ */
105 
106 /* CPU kernel features */
107 
108 /* Retain the 32b definitions all use bottom half of word */
109 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
110 #define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
111 #define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
112 #define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
113 #define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
114 #define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
115 #define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
116 #define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080)
117 #define CPU_FTR_601 ASM_CONST(0x0000000000000100)
118 #define CPU_FTR_DBELL ASM_CONST(0x0000000000000200)
119 #define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
120 #define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
121 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
122 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
123 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
124 #define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
125 #define CPU_FTR_476_DD2 ASM_CONST(0x0000000000010000)
126 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
127 #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
128 #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x0000000000080000)
129 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
130 #define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
131 #define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
132 #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
133 #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
134 #define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
135 #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
136 #define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000)
137 #define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000010000000)
138 #define CPU_FTR_INDEXED_DCR ASM_CONST(0x0000000020000000)
139 #define CPU_FTR_EMB_HV ASM_CONST(0x0000000040000000)
140 
141 /*
142  * Add the 64-bit processor unique features in the top half of the word;
143  * on 32-bit, make the names available but defined to be 0.
144  */
145 #ifdef __powerpc64__
146 #define LONG_ASM_CONST(x) ASM_CONST(x)
147 #else
148 #define LONG_ASM_CONST(x) 0
149 #endif
150 
151 #define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000200000000)
152 #define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000400000000)
153 #define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000800000000)
154 #define CPU_FTR_CFAR LONG_ASM_CONST(0x0000001000000000)
155 #define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
156 #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
157 #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
158 #define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
159 #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
160 #define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
161 #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
162 #define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
163 #define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
164 #define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
165 #define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
166 #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000)
167 #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0080000000000000)
168 #define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0100000000000000)
169 #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0200000000000000)
170 #define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0400000000000000)
171 #define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0800000000000000)
172 #define CPU_FTR_ICSWX LONG_ASM_CONST(0x1000000000000000)
173 #define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x2000000000000000)
174 
175 #ifndef __ASSEMBLY__
176 
177 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
178 
179 #define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
180  MMU_FTR_16M_PAGE)
181 
182 /* We only set the altivec features if the kernel was compiled with altivec
183  * support
184  */
185 #ifdef CONFIG_ALTIVEC
186 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
187 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
188 #else
189 #define CPU_FTR_ALTIVEC_COMP 0
190 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0
191 #endif
192 
193 /* We only set the VSX features if the kernel was compiled with VSX
194  * support
195  */
196 #ifdef CONFIG_VSX
197 #define CPU_FTR_VSX_COMP CPU_FTR_VSX
198 #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
199 #else
200 #define CPU_FTR_VSX_COMP 0
201 #define PPC_FEATURE_HAS_VSX_COMP 0
202 #endif
203 
204 /* We only set the spe features if the kernel was compiled with spe
205  * support
206  */
207 #ifdef CONFIG_SPE
208 #define CPU_FTR_SPE_COMP CPU_FTR_SPE
209 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
210 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
211 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
212 #else
213 #define CPU_FTR_SPE_COMP 0
214 #define PPC_FEATURE_HAS_SPE_COMP 0
215 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
216 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
217 #endif
218 
219 /* We need to mark all pages as being coherent if we're SMP or we have a
220  * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
221  * require it for PCI "streaming/prefetch" to work properly.
222  * This is also required by 52xx family.
223  */
224 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
225  || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
226  || defined(CONFIG_PPC_MPC52xx)
227 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
228 #else
229 #define CPU_FTR_COMMON 0
230 #endif
231 
232 /* The powersave features NAP & DOZE seems to confuse BDI when
233  debugging. So if a BDI is used, disable theses
234  */
235 #ifndef CONFIG_BDI_SWITCH
236 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
237 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
238 #else
239 #define CPU_FTR_MAYBE_CAN_DOZE 0
240 #define CPU_FTR_MAYBE_CAN_NAP 0
241 #endif
242 
243 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
244  !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
245  !defined(CONFIG_BOOKE))
246 
247 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
248  CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
249 #define CPU_FTRS_603 (CPU_FTR_COMMON | \
250  CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
251  CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
252 #define CPU_FTRS_604 (CPU_FTR_COMMON | \
253  CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
254 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
255  CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
256  CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
257 #define CPU_FTRS_740 (CPU_FTR_COMMON | \
258  CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
259  CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
260  CPU_FTR_PPC_LE)
261 #define CPU_FTRS_750 (CPU_FTR_COMMON | \
262  CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
263  CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
264  CPU_FTR_PPC_LE)
265 #define CPU_FTRS_750CL (CPU_FTRS_750)
266 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
267 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
268 #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
269 #define CPU_FTRS_750GX (CPU_FTRS_750FX)
270 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
271  CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
272  CPU_FTR_ALTIVEC_COMP | \
273  CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
274 #define CPU_FTRS_7400 (CPU_FTR_COMMON | \
275  CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
276  CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
277  CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
278 #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
279  CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
280  CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
281  CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
282 #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
283  CPU_FTR_USE_TB | \
284  CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
285  CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
286  CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
287  CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
288 #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
289  CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
290  CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
291  CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
292  CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
293 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
294  CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
295  CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
296  CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
297 #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
298  CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
299  CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
300  CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
301  CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
302  CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
303 #define CPU_FTRS_7455 (CPU_FTR_COMMON | \
304  CPU_FTR_USE_TB | \
305  CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
306  CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
307  CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
308 #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
309  CPU_FTR_USE_TB | \
310  CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
311  CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
312  CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
313  CPU_FTR_NEED_PAIRED_STWCX)
314 #define CPU_FTRS_7447 (CPU_FTR_COMMON | \
315  CPU_FTR_USE_TB | \
316  CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
317  CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
318  CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
319 #define CPU_FTRS_7447A (CPU_FTR_COMMON | \
320  CPU_FTR_USE_TB | \
321  CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
322  CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
323  CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
324 #define CPU_FTRS_7448 (CPU_FTR_COMMON | \
325  CPU_FTR_USE_TB | \
326  CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
327  CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
328  CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
329 #define CPU_FTRS_82XX (CPU_FTR_COMMON | \
330  CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
331 #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
332  CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
333 #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
334  CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
335  CPU_FTR_COMMON)
336 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
337  CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
338  CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
339 #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
340 #define CPU_FTRS_8XX (CPU_FTR_USE_TB)
341 #define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
342 #define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
343 #define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
344  CPU_FTR_INDEXED_DCR)
345 #define CPU_FTRS_47X (CPU_FTRS_440x6)
346 #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
347  CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
348  CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
349  CPU_FTR_DEBUG_LVL_EXC)
350 #define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
351  CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
352  CPU_FTR_NOEXECUTE)
353 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
354  CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
355  CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
356 #define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
357  CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
358  CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
359 #define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
360  CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
361  CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
362  CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
363 #define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
364  CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
365  CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
366  CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
367 #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
368 
369 /* 64-bit CPUs */
370 #define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
371  CPU_FTR_IABR | CPU_FTR_PPC_LE)
372 #define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
373  CPU_FTR_IABR | \
374  CPU_FTR_MMCRA | CPU_FTR_CTRL)
375 #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
376  CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
377  CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
378  CPU_FTR_STCX_CHECKS_ADDRESS)
379 #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
380  CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
381  CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
382  CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
383  CPU_FTR_HVMODE)
384 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
385  CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
386  CPU_FTR_MMCRA | CPU_FTR_SMT | \
387  CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
388  CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
389 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
390  CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
391  CPU_FTR_MMCRA | CPU_FTR_SMT | \
392  CPU_FTR_COHERENT_ICACHE | \
393  CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
394  CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
395  CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR)
396 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
397  CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
398  CPU_FTR_MMCRA | CPU_FTR_SMT | \
399  CPU_FTR_COHERENT_ICACHE | \
400  CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
401  CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
402  CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
403  CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY)
404 #define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
405  CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
406  CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
407  CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
408  CPU_FTR_UNALIGNED_LD_STD)
409 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
410  CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
411  CPU_FTR_PURR | CPU_FTR_REAL_LE)
412 #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
413 
414 #define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
415  CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
416 
417 #ifdef __powerpc64__
418 #ifdef CONFIG_PPC_BOOK3E
419 #define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500 | CPU_FTRS_A2)
420 #else
421 #define CPU_FTRS_POSSIBLE \
422  (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
423  CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
424  CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
425  CPU_FTR_VSX)
426 #endif
427 #else
428 enum {
429  CPU_FTRS_POSSIBLE =
430 #if CLASSIC_PPC
431  CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
432  CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
433  CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
434  CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
435  CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
436  CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
437  CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
438  CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
439  CPU_FTRS_CLASSIC32 |
440 #else
441  CPU_FTRS_GENERIC_32 |
442 #endif
443 #ifdef CONFIG_8xx
444  CPU_FTRS_8XX |
445 #endif
446 #ifdef CONFIG_40x
447  CPU_FTRS_40X |
448 #endif
449 #ifdef CONFIG_44x
450  CPU_FTRS_44X | CPU_FTRS_440x6 |
451 #endif
452 #ifdef CONFIG_PPC_47x
453  CPU_FTRS_47X | CPU_FTR_476_DD2 |
454 #endif
455 #ifdef CONFIG_E200
456  CPU_FTRS_E200 |
457 #endif
458 #ifdef CONFIG_E500
459  CPU_FTRS_E500 | CPU_FTRS_E500_2 |
460 #endif
461 #ifdef CONFIG_PPC_E500MC
462  CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
463 #endif
464  0,
465 };
466 #endif /* __powerpc64__ */
467 
468 #ifdef __powerpc64__
469 #ifdef CONFIG_PPC_BOOK3E
470 #define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500 & CPU_FTRS_A2)
471 #else
472 #define CPU_FTRS_ALWAYS \
473  (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
474  CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
475  CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
476 #endif
477 #else
478 enum {
479  CPU_FTRS_ALWAYS =
480 #if CLASSIC_PPC
481  CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
482  CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
483  CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
484  CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
485  CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
486  CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
487  CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
488  CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
489  CPU_FTRS_CLASSIC32 &
490 #else
491  CPU_FTRS_GENERIC_32 &
492 #endif
493 #ifdef CONFIG_8xx
494  CPU_FTRS_8XX &
495 #endif
496 #ifdef CONFIG_40x
497  CPU_FTRS_40X &
498 #endif
499 #ifdef CONFIG_44x
500  CPU_FTRS_44X & CPU_FTRS_440x6 &
501 #endif
502 #ifdef CONFIG_E200
503  CPU_FTRS_E200 &
504 #endif
505 #ifdef CONFIG_E500
506  CPU_FTRS_E500 & CPU_FTRS_E500_2 &
507 #endif
508 #ifdef CONFIG_PPC_E500MC
509  CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
510 #endif
511  ~CPU_FTR_EMB_HV & /* can be removed at runtime */
512  CPU_FTRS_POSSIBLE,
513 };
514 #endif /* __powerpc64__ */
515 
516 static inline int cpu_has_feature(unsigned long feature)
517 {
518  return (CPU_FTRS_ALWAYS & feature) ||
519  (CPU_FTRS_POSSIBLE
520  & cur_cpu_spec->cpu_features
521  & feature);
522 }
523 
524 #define HBP_NUM 1
525 
526 #endif /* !__ASSEMBLY__ */
527 
528 #endif /* __ASM_POWERPC_CPUTABLE_H */
Generated on Thu Jan 10 2013 13:03:35 for Linux Kernel by   doxygen 1.8.2