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arch
powerpc
net
bpf_jit.h
Go to the documentation of this file.
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/* bpf_jit.h: BPF JIT compiler for PPC64
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*
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* Copyright 2011 Matt Evans <
[email protected]
>, IBM Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#ifndef _BPF_JIT_H
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#define _BPF_JIT_H
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#define BPF_PPC_STACK_LOCALS 32
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#define BPF_PPC_STACK_BASIC (48+64)
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#define BPF_PPC_STACK_SAVE (18*8)
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#define BPF_PPC_STACKFRAME (BPF_PPC_STACK_BASIC+BPF_PPC_STACK_LOCALS+ \
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BPF_PPC_STACK_SAVE)
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#define BPF_PPC_SLOWPATH_FRAME (48+64)
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/*
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* Generated code register usage:
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*
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* As normal PPC C ABI (e.g. r1=sp, r2=TOC), with:
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*
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* skb r3 (Entry parameter)
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* A register r4
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* X register r5
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* addr param r6
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* r7-r10 scratch
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* skb->data r14
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* skb headlen r15 (skb->len - skb->data_len)
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* m[0] r16
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* m[...] ...
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* m[15] r31
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*/
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#define r_skb 3
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#define r_ret 3
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#define r_A 4
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#define r_X 5
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#define r_addr 6
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#define r_scratch1 7
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#define r_D 14
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#define r_HL 15
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#define r_M 16
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#ifndef __ASSEMBLY__
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/*
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* Assembly helpers from arch/powerpc/net/bpf_jit.S:
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*/
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#define DECLARE_LOAD_FUNC(func) \
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extern u8 func[], func##_negative_offset[], func##_positive_offset[]
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DECLARE_LOAD_FUNC
(sk_load_word);
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DECLARE_LOAD_FUNC
(sk_load_half);
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DECLARE_LOAD_FUNC
(sk_load_byte);
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DECLARE_LOAD_FUNC
(sk_load_byte_msh);
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#define FUNCTION_DESCR_SIZE 24
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/*
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* 16-bit immediate helper macros: HA() is for use with sign-extending instrs
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* (e.g. LD, ADDI). If the bottom 16 bits is "-ve", add another bit into the
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* top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
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*/
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#define IMM_H(i) ((uintptr_t)(i)>>16)
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#define IMM_HA(i) (((uintptr_t)(i)>>16) + \
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(((uintptr_t)(i) & 0x8000) >> 15))
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#define IMM_L(i) ((uintptr_t)(i) & 0xffff)
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#define PLANT_INSTR(d, idx, instr) \
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do { if (d) { (d)[idx] = instr; } idx++; } while (0)
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#define EMIT(instr) PLANT_INSTR(image, ctx->idx, instr)
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#define PPC_NOP() EMIT(PPC_INST_NOP)
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#define PPC_BLR() EMIT(PPC_INST_BLR)
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#define PPC_BLRL() EMIT(PPC_INST_BLRL)
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#define PPC_MTLR(r) EMIT(PPC_INST_MTLR | ___PPC_RT(r))
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#define PPC_ADDI(d, a, i) EMIT(PPC_INST_ADDI | ___PPC_RT(d) | \
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___PPC_RA(a) | IMM_L(i))
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#define PPC_MR(d, a) PPC_OR(d, a, a)
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#define PPC_LI(r, i) PPC_ADDI(r, 0, i)
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#define PPC_ADDIS(d, a, i) EMIT(PPC_INST_ADDIS | \
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___PPC_RS(d) | ___PPC_RA(a) | IMM_L(i))
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#define PPC_LIS(r, i) PPC_ADDIS(r, 0, i)
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#define PPC_STD(r, base, i) EMIT(PPC_INST_STD | ___PPC_RS(r) | \
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___PPC_RA(base) | ((i) & 0xfffc))
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#define PPC_LD(r, base, i) EMIT(PPC_INST_LD | ___PPC_RT(r) | \
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___PPC_RA(base) | IMM_L(i))
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#define PPC_LWZ(r, base, i) EMIT(PPC_INST_LWZ | ___PPC_RT(r) | \
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___PPC_RA(base) | IMM_L(i))
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#define PPC_LHZ(r, base, i) EMIT(PPC_INST_LHZ | ___PPC_RT(r) | \
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___PPC_RA(base) | IMM_L(i))
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/* Convenience helpers for the above with 'far' offsets: */
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#define PPC_LD_OFFS(r, base, i) do { if ((i) < 32768) PPC_LD(r, base, i); \
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else { PPC_ADDIS(r, base, IMM_HA(i)); \
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PPC_LD(r, r, IMM_L(i)); } } while(0)
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#define PPC_LWZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LWZ(r, base, i); \
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else { PPC_ADDIS(r, base, IMM_HA(i)); \
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PPC_LWZ(r, r, IMM_L(i)); } } while(0)
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#define PPC_LHZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LHZ(r, base, i); \
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else { PPC_ADDIS(r, base, IMM_HA(i)); \
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PPC_LHZ(r, r, IMM_L(i)); } } while(0)
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#define PPC_CMPWI(a, i) EMIT(PPC_INST_CMPWI | ___PPC_RA(a) | IMM_L(i))
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#define PPC_CMPDI(a, i) EMIT(PPC_INST_CMPDI | ___PPC_RA(a) | IMM_L(i))
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#define PPC_CMPLWI(a, i) EMIT(PPC_INST_CMPLWI | ___PPC_RA(a) | IMM_L(i))
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#define PPC_CMPLW(a, b) EMIT(PPC_INST_CMPLW | ___PPC_RA(a) | ___PPC_RB(b))
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#define PPC_SUB(d, a, b) EMIT(PPC_INST_SUB | ___PPC_RT(d) | \
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___PPC_RB(a) | ___PPC_RA(b))
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#define PPC_ADD(d, a, b) EMIT(PPC_INST_ADD | ___PPC_RT(d) | \
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___PPC_RA(a) | ___PPC_RB(b))
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#define PPC_MUL(d, a, b) EMIT(PPC_INST_MULLW | ___PPC_RT(d) | \
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___PPC_RA(a) | ___PPC_RB(b))
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#define PPC_MULHWU(d, a, b) EMIT(PPC_INST_MULHWU | ___PPC_RT(d) | \
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___PPC_RA(a) | ___PPC_RB(b))
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#define PPC_MULI(d, a, i) EMIT(PPC_INST_MULLI | ___PPC_RT(d) | \
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___PPC_RA(a) | IMM_L(i))
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#define PPC_DIVWU(d, a, b) EMIT(PPC_INST_DIVWU | ___PPC_RT(d) | \
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___PPC_RA(a) | ___PPC_RB(b))
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#define PPC_AND(d, a, b) EMIT(PPC_INST_AND | ___PPC_RA(d) | \
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___PPC_RS(a) | ___PPC_RB(b))
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#define PPC_ANDI(d, a, i) EMIT(PPC_INST_ANDI | ___PPC_RA(d) | \
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___PPC_RS(a) | IMM_L(i))
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#define PPC_AND_DOT(d, a, b) EMIT(PPC_INST_ANDDOT | ___PPC_RA(d) | \
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___PPC_RS(a) | ___PPC_RB(b))
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#define PPC_OR(d, a, b) EMIT(PPC_INST_OR | ___PPC_RA(d) | \
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___PPC_RS(a) | ___PPC_RB(b))
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#define PPC_ORI(d, a, i) EMIT(PPC_INST_ORI | ___PPC_RA(d) | \
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___PPC_RS(a) | IMM_L(i))
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#define PPC_ORIS(d, a, i) EMIT(PPC_INST_ORIS | ___PPC_RA(d) | \
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___PPC_RS(a) | IMM_L(i))
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#define PPC_SLW(d, a, s) EMIT(PPC_INST_SLW | ___PPC_RA(d) | \
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___PPC_RS(a) | ___PPC_RB(s))
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#define PPC_SRW(d, a, s) EMIT(PPC_INST_SRW | ___PPC_RA(d) | \
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___PPC_RS(a) | ___PPC_RB(s))
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/* slwi = rlwinm Rx, Ry, n, 0, 31-n */
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#define PPC_SLWI(d, a, i) EMIT(PPC_INST_RLWINM | ___PPC_RA(d) | \
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___PPC_RS(a) | __PPC_SH(i) | \
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__PPC_MB(0) | __PPC_ME(31-(i)))
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/* srwi = rlwinm Rx, Ry, 32-n, n, 31 */
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#define PPC_SRWI(d, a, i) EMIT(PPC_INST_RLWINM | ___PPC_RA(d) | \
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___PPC_RS(a) | __PPC_SH(32-(i)) | \
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__PPC_MB(i) | __PPC_ME(31))
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/* sldi = rldicr Rx, Ry, n, 63-n */
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#define PPC_SLDI(d, a, i) EMIT(PPC_INST_RLDICR | ___PPC_RA(d) | \
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___PPC_RS(a) | __PPC_SH(i) | \
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__PPC_MB(63-(i)) | (((i) & 0x20) >> 4))
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#define PPC_NEG(d, a) EMIT(PPC_INST_NEG | ___PPC_RT(d) | ___PPC_RA(a))
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/* Long jump; (unconditional 'branch') */
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#define PPC_JMP(dest) EMIT(PPC_INST_BRANCH | \
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(((dest) - (ctx->idx * 4)) & 0x03fffffc))
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/* "cond" here covers BO:BI fields. */
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#define PPC_BCC_SHORT(cond, dest) EMIT(PPC_INST_BRANCH_COND | \
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(((cond) & 0x3ff) << 16) | \
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(((dest) - (ctx->idx * 4)) & \
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0xfffc))
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#define PPC_LI32(d, i) do { PPC_LI(d, IMM_L(i)); \
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if ((u32)(uintptr_t)(i) >= 32768) { \
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PPC_ADDIS(d, d, IMM_HA(i)); \
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} } while(0)
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#define PPC_LI64(d, i) do { \
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if (!((uintptr_t)(i) & 0xffffffff00000000ULL)) \
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PPC_LI32(d, i); \
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else { \
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PPC_LIS(d, ((uintptr_t)(i) >> 48)); \
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if ((uintptr_t)(i) & 0x0000ffff00000000ULL) \
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PPC_ORI(d, d, \
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((uintptr_t)(i) >> 32) & 0xffff); \
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PPC_SLDI(d, d, 32); \
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if ((uintptr_t)(i) & 0x00000000ffff0000ULL) \
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PPC_ORIS(d, d, \
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((uintptr_t)(i) >> 16) & 0xffff); \
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if ((uintptr_t)(i) & 0x000000000000ffffULL) \
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PPC_ORI(d, d, (uintptr_t)(i) & 0xffff); \
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} } while (0);
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static
inline
bool
is_nearbranch(
int
offset
)
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{
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return
(offset < 32768) && (offset >= -32768);
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}
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/*
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* The fly in the ointment of code size changing from pass to pass is
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* avoided by padding the short branch case with a NOP. If code size differs
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* with different branch reaches we will have the issue of code moving from
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* one pass to the next and will need a few passes to converge on a stable
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* state.
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*/
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#define PPC_BCC(cond, dest) do { \
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if (is_nearbranch((dest) - (ctx->idx * 4))) { \
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PPC_BCC_SHORT(cond, dest); \
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PPC_NOP(); \
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} else { \
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/* Flip the 'T or F' bit to invert comparison */
\
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PPC_BCC_SHORT(cond ^ COND_CMP_TRUE, (ctx->idx+2)*4); \
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PPC_JMP(dest); \
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} } while(0)
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/* To create a branch condition, select a bit of cr0... */
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#define CR0_LT 0
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#define CR0_GT 1
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#define CR0_EQ 2
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/* ...and modify BO[3] */
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#define COND_CMP_TRUE 0x100
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#define COND_CMP_FALSE 0x000
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/* Together, they make all required comparisons: */
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#define COND_GT (CR0_GT | COND_CMP_TRUE)
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#define COND_GE (CR0_LT | COND_CMP_FALSE)
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#define COND_EQ (CR0_EQ | COND_CMP_TRUE)
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#define COND_NE (CR0_EQ | COND_CMP_FALSE)
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#define COND_LT (CR0_LT | COND_CMP_TRUE)
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#define SEEN_DATAREF 0x10000
/* might call external helpers */
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#define SEEN_XREG 0x20000
/* X reg is used */
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#define SEEN_MEM 0x40000
/* SEEN_MEM+(1<<n) = use mem[n] for temporary
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* storage */
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#define SEEN_MEM_MSK 0x0ffff
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struct
codegen_context
{
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unsigned
int
seen
;
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unsigned
int
idx
;
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int
pc_ret0
;
/* bpf index of first RET #0 instruction (if any) */
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};
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#endif
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#endif
Generated on Thu Jan 10 2013 13:14:31 for Linux Kernel by
1.8.2
1.8.2