prph.h

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/******************************************************************************
 *
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 * redistributing this file, you may do so under either license.
 *
 * GPL LICENSE SUMMARY
 *
 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
 * USA
 *
 * The full GNU General Public License is included in this distribution
 * in the file called LICENSE.GPL.
 *
 * Contact Information:
 *  Intel Linux Wireless <[email protected]>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 * BSD LICENSE
 *
 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
 * All rights reserved.
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 * modification, are permitted provided that the following conditions
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 *****************************************************************************/

#ifndef __il_prph_h__
#define __il_prph_h__

/*
 * Registers in this file are internal, not PCI bus memory mapped.
 * Driver accesses these via HBUS_TARG_PRPH_* registers.
 */
#define PRPH_BASE   (0x00000)
#define PRPH_END    (0xFFFFF)

/* APMG (power management) constants */
#define APMG_BASE           (PRPH_BASE + 0x3000)
#define APMG_CLK_CTRL_REG       (APMG_BASE + 0x0000)
#define APMG_CLK_EN_REG         (APMG_BASE + 0x0004)
#define APMG_CLK_DIS_REG        (APMG_BASE + 0x0008)
#define APMG_PS_CTRL_REG        (APMG_BASE + 0x000c)
#define APMG_PCIDEV_STT_REG     (APMG_BASE + 0x0010)
#define APMG_RFKILL_REG         (APMG_BASE + 0x0014)
#define APMG_RTC_INT_STT_REG        (APMG_BASE + 0x001c)
#define APMG_RTC_INT_MSK_REG        (APMG_BASE + 0x0020)
#define APMG_DIGITAL_SVR_REG        (APMG_BASE + 0x0058)
#define APMG_ANALOG_SVR_REG     (APMG_BASE + 0x006C)

#define APMS_CLK_VAL_MRB_FUNC_MODE  (0x00000001)
#define APMG_CLK_VAL_DMA_CLK_RQT    (0x00000200)
#define APMG_CLK_VAL_BSM_CLK_RQT    (0x00000800)

#define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS    (0x00400000)
#define APMG_PS_CTRL_VAL_RESET_REQ      (0x04000000)
#define APMG_PS_CTRL_MSK_PWR_SRC        (0x03000000)
#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN      (0x00000000)
#define APMG_PS_CTRL_VAL_PWR_SRC_MAX        (0x01000000)    /* 3945 only */
#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX       (0x02000000)
#define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0)    /* bit 8:5 */
#define APMG_SVR_DIGITAL_VOLTAGE_1_32       (0x00000060)

#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS      (0x00000800)

/* BSM bit fields */
#define BSM_WR_CTRL_REG_BIT_START     (0x80000000)  /* start boot load now */
#define BSM_WR_CTRL_REG_BIT_START_EN  (0x40000000)  /* enable boot after pwrup */
#define BSM_DRAM_INST_LOAD            (0x80000000)  /* start program load now */

/* BSM addresses */
#define BSM_BASE                     (PRPH_BASE + 0x3400)
#define BSM_END                      (PRPH_BASE + 0x3800)

#define BSM_WR_CTRL_REG              (BSM_BASE + 0x000) /* ctl and status */
#define BSM_WR_MEM_SRC_REG           (BSM_BASE + 0x004) /* source in BSM mem */
#define BSM_WR_MEM_DST_REG           (BSM_BASE + 0x008) /* dest in SRAM mem */
#define BSM_WR_DWCOUNT_REG           (BSM_BASE + 0x00C) /* bytes */
#define BSM_WR_STATUS_REG            (BSM_BASE + 0x010) /* bit 0:  1 == done */

/*
 * Pointers and size regs for bootstrap load and data SRAM save/restore.
 * NOTE:  3945 pointers use bits 31:0 of DRAM address.
 *        4965 pointers use bits 35:4 of DRAM address.
 */
#define BSM_DRAM_INST_PTR_REG        (BSM_BASE + 0x090)
#define BSM_DRAM_INST_BYTECOUNT_REG  (BSM_BASE + 0x094)
#define BSM_DRAM_DATA_PTR_REG        (BSM_BASE + 0x098)
#define BSM_DRAM_DATA_BYTECOUNT_REG  (BSM_BASE + 0x09C)

/*
 * BSM special memory, stays powered on during power-save sleeps.
 * Read/write, address range from LOWER_BOUND to (LOWER_BOUND + SIZE -1)
 */
#define BSM_SRAM_LOWER_BOUND         (PRPH_BASE + 0x3800)
#define BSM_SRAM_SIZE           (1024)  /* bytes */

/* 3945 Tx scheduler registers */
#define ALM_SCD_BASE                        (PRPH_BASE + 0x2E00)
#define ALM_SCD_MODE_REG                    (ALM_SCD_BASE + 0x000)
#define ALM_SCD_ARASTAT_REG                 (ALM_SCD_BASE + 0x004)
#define ALM_SCD_TXFACT_REG                  (ALM_SCD_BASE + 0x010)
#define ALM_SCD_TXF4MF_REG                  (ALM_SCD_BASE + 0x014)
#define ALM_SCD_TXF5MF_REG                  (ALM_SCD_BASE + 0x020)
#define ALM_SCD_SBYP_MODE_1_REG             (ALM_SCD_BASE + 0x02C)
#define ALM_SCD_SBYP_MODE_2_REG             (ALM_SCD_BASE + 0x030)

#define SCD_WIN_SIZE                64
#define SCD_FRAME_LIMIT             64

/* SCD registers are internal, must be accessed via HBUS_TARG_PRPH regs */
#define IL49_SCD_START_OFFSET       0xa02c00

/*
 * 4965 tells driver SRAM address for internal scheduler structs via this reg.
 * Value is valid only after "Alive" response from uCode.
 */
#define IL49_SCD_SRAM_BASE_ADDR           (IL49_SCD_START_OFFSET + 0x0)

/*
 * Driver may need to update queue-empty bits after changing queue's
 * write and read pointers (idxes) during (re-)initialization (i.e. when
 * scheduler is not tracking what's happening).
 * Bit fields:
 * 31-16:  Write mask -- 1: update empty bit, 0: don't change empty bit
 * 15-00:  Empty state, one for each queue -- 1: empty, 0: non-empty
 * NOTE:  This register is not used by Linux driver.
 */
#define IL49_SCD_EMPTY_BITS               (IL49_SCD_START_OFFSET + 0x4)

/*
 * Physical base address of array of byte count (BC) circular buffers (CBs).
 * Each Tx queue has a BC CB in host DRAM to support Scheduler-ACK mode.
 * This register points to BC CB for queue 0, must be on 1024-byte boundary.
 * Others are spaced by 1024 bytes.
 * Each BC CB is 2 bytes * (256 + 64) = 740 bytes, followed by 384 bytes pad.
 * (Index into a queue's BC CB) = (idx into queue's TFD CB) = (SSN & 0xff).
 * Bit fields:
 * 25-00:  Byte Count CB physical address [35:10], must be 1024-byte aligned.
 */
#define IL49_SCD_DRAM_BASE_ADDR           (IL49_SCD_START_OFFSET + 0x10)

/*
 * Enables any/all Tx DMA/FIFO channels.
 * Scheduler generates requests for only the active channels.
 * Set this to 0xff to enable all 8 channels (normal usage).
 * Bit fields:
 *  7- 0:  Enable (1), disable (0), one bit for each channel 0-7
 */
#define IL49_SCD_TXFACT                   (IL49_SCD_START_OFFSET + 0x1c)
/*
 * Queue (x) Write Pointers (idxes, really!), one for each Tx queue.
 * Initialized and updated by driver as new TFDs are added to queue.
 * NOTE:  If using Block Ack, idx must correspond to frame's
 *        Start Sequence Number; idx = (SSN & 0xff)
 * NOTE:  Alternative to HBUS_TARG_WRPTR, which is what Linux driver uses?
 */
#define IL49_SCD_QUEUE_WRPTR(x)  (IL49_SCD_START_OFFSET + 0x24 + (x) * 4)

/*
 * Queue (x) Read Pointers (idxes, really!), one for each Tx queue.
 * For FIFO mode, idx indicates next frame to transmit.
 * For Scheduler-ACK mode, idx indicates first frame in Tx win.
 * Initialized by driver, updated by scheduler.
 */
#define IL49_SCD_QUEUE_RDPTR(x)  (IL49_SCD_START_OFFSET + 0x64 + (x) * 4)

/*
 * Select which queues work in chain mode (1) vs. not (0).
 * Use chain mode to build chains of aggregated frames.
 * Bit fields:
 * 31-16:  Reserved
 * 15-00:  Mode, one bit for each queue -- 1: Chain mode, 0: one-at-a-time
 * NOTE:  If driver sets up queue for chain mode, it should be also set up
 *        Scheduler-ACK mode as well, via SCD_QUEUE_STATUS_BITS(x).
 */
#define IL49_SCD_QUEUECHAIN_SEL  (IL49_SCD_START_OFFSET + 0xd0)

/*
 * Select which queues interrupt driver when scheduler increments
 * a queue's read pointer (idx).
 * Bit fields:
 * 31-16:  Reserved
 * 15-00:  Interrupt enable, one bit for each queue -- 1: enabled, 0: disabled
 * NOTE:  This functionality is apparently a no-op; driver relies on interrupts
 *        from Rx queue to read Tx command responses and update Tx queues.
 */
#define IL49_SCD_INTERRUPT_MASK  (IL49_SCD_START_OFFSET + 0xe4)

/*
 * Queue search status registers.  One for each queue.
 * Sets up queue mode and assigns queue to Tx DMA channel.
 * Bit fields:
 * 19-10: Write mask/enable bits for bits 0-9
 *     9: Driver should init to "0"
 *     8: Scheduler-ACK mode (1), non-Scheduler-ACK (i.e. FIFO) mode (0).
 *        Driver should init to "1" for aggregation mode, or "0" otherwise.
 *   7-6: Driver should init to "0"
 *     5: Window Size Left; indicates whether scheduler can request
 *        another TFD, based on win size, etc.  Driver should init
 *        this bit to "1" for aggregation mode, or "0" for non-agg.
 *   4-1: Tx FIFO to use (range 0-7).
 *     0: Queue is active (1), not active (0).
 * Other bits should be written as "0"
 *
 * NOTE:  If enabling Scheduler-ACK mode, chain mode should also be enabled
 *        via SCD_QUEUECHAIN_SEL.
 */
#define IL49_SCD_QUEUE_STATUS_BITS(x)\
    (IL49_SCD_START_OFFSET + 0x104 + (x) * 4)

/* Bit field positions */
#define IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE  (0)
#define IL49_SCD_QUEUE_STTS_REG_POS_TXF (1)
#define IL49_SCD_QUEUE_STTS_REG_POS_WSL (5)
#define IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK (8)

/* Write masks */
#define IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN  (10)
#define IL49_SCD_QUEUE_STTS_REG_MSK     (0x0007FC00)

/*
 * Queue context.  One 8-byte entry for each of 16 queues.
 *
 * Driver should clear this entire area (size 0x80) to 0 after receiving
 * "Alive" notification from uCode.  Additionally, driver should init
 * each queue's entry as follows:
 *
 * LS Dword bit fields:
 *  0-06:  Max Tx win size for Scheduler-ACK.  Driver should init to 64.
 *
 * MS Dword bit fields:
 * 16-22:  Frame limit.  Driver should init to 10 (0xa).
 *
 * Driver should init all other bits to 0.
 *
 * Init must be done after driver receives "Alive" response from 4965 uCode,
 * and when setting up queue for aggregation.
 */
#define IL49_SCD_CONTEXT_DATA_OFFSET            0x380
#define IL49_SCD_CONTEXT_QUEUE_OFFSET(x) \
            (IL49_SCD_CONTEXT_DATA_OFFSET + ((x) * 8))

#define IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS        (0)
#define IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK        (0x0000007F)
#define IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
#define IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)

/*
 * Tx Status Bitmap
 *
 * Driver should clear this entire area (size 0x100) to 0 after receiving
 * "Alive" notification from uCode.  Area is used only by device itself;
 * no other support (besides clearing) is required from driver.
 */
#define IL49_SCD_TX_STTS_BITMAP_OFFSET      0x400

/*
 * RAxTID to queue translation mapping.
 *
 * When queue is in Scheduler-ACK mode, frames placed in a that queue must be
 * for only one combination of receiver address (RA) and traffic ID (TID), i.e.
 * one QOS priority level destined for one station (for this wireless link,
 * not final destination).  The SCD_TRANSLATE_TBL area provides 16 16-bit
 * mappings, one for each of the 16 queues.  If queue is not in Scheduler-ACK
 * mode, the device ignores the mapping value.
 *
 * Bit fields, for each 16-bit map:
 * 15-9:  Reserved, set to 0
 *  8-4:  Index into device's station table for recipient station
 *  3-0:  Traffic ID (tid), range 0-15
 *
 * Driver should clear this entire area (size 32 bytes) to 0 after receiving
 * "Alive" notification from uCode.  To update a 16-bit map value, driver
 * must read a dword-aligned value from device SRAM, replace the 16-bit map
 * value of interest, and write the dword value back into device SRAM.
 */
#define IL49_SCD_TRANSLATE_TBL_OFFSET       0x500

/* Find translation table dword to read/write for given queue */
#define IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
    ((IL49_SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc)

#define IL_SCD_TXFIFO_POS_TID           (0)
#define IL_SCD_TXFIFO_POS_RA            (4)
#define IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK   (0x01FF)

/*********************** END TX SCHEDULER *************************************/

#endif /* __il_prph_h__ */