20 #ifndef _ASM_POWERPC_PS3GPU_H
21 #define _ASM_POWERPC_PS3GPU_H
28 #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC 0x101
29 #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP 0x102
31 #define L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP 0x600
32 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601
33 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT_SYNC 0x602
34 #define L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE 0x603
36 #define L1GPU_FB_BLIT_WAIT_FOR_COMPLETION (1ULL << 32)
38 #define L1GPU_DISPLAY_SYNC_HSYNC 1
39 #define L1GPU_DISPLAY_SYNC_VSYNC 2
46 static inline int lv1_gpu_display_sync(
u64 context_handle,
u64 head,
49 return lv1_gpu_context_attribute(context_handle,
51 head, ddr_offset, 0, 0);
54 static inline int lv1_gpu_display_flip(
u64 context_handle,
u64 head,
57 return lv1_gpu_context_attribute(context_handle,
59 head, ddr_offset, 0, 0);
62 static inline int lv1_gpu_fb_setup(
u64 context_handle,
u64 xdr_lpar,
63 u64 xdr_size,
u64 ioif_offset)
65 return lv1_gpu_context_attribute(context_handle,
67 xdr_lpar, xdr_size, ioif_offset, 0);
70 static inline int lv1_gpu_fb_blit(
u64 context_handle,
u64 ddr_offset,
71 u64 ioif_offset,
u64 sync_width,
u64 pitch)
73 return lv1_gpu_context_attribute(context_handle,
75 ddr_offset, ioif_offset, sync_width,
79 static inline int lv1_gpu_fb_close(
u64 context_handle)
81 return lv1_gpu_context_attribute(context_handle,