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13 #ifndef __ASM_ARCH_PXA3XX_REGS_H
14 #define __ASM_ARCH_PXA3XX_REGS_H
16 #include <mach/hardware.h>
21 #define OSCC __REG(0x41350000)
23 #define OSCC_PEN (1 << 11)
29 #define PMCR __REG(0x40F50000)
30 #define PSR __REG(0x40F50004)
31 #define PSPR __REG(0x40F50008)
32 #define PCFR __REG(0x40F5000C)
33 #define PWER __REG(0x40F50010)
34 #define PWSR __REG(0x40F50014)
35 #define PECR __REG(0x40F50018)
36 #define DCDCSR __REG(0x40F50080)
37 #define PVCR __REG(0x40F50100)
38 #define PCMD(x) __REG(0x40F50110 + ((x) << 2))
43 #define ASCR __REG(0x40f40000)
44 #define ARSR __REG(0x40f40004)
45 #define AD3ER __REG(0x40f40008)
46 #define AD3SR __REG(0x40f4000c)
47 #define AD2D0ER __REG(0x40f40010)
48 #define AD2D0SR __REG(0x40f40014)
49 #define AD2D1ER __REG(0x40f40018)
50 #define AD2D1SR __REG(0x40f4001c)
51 #define AD1D0ER __REG(0x40f40020)
52 #define AD1D0SR __REG(0x40f40024)
53 #define AGENP __REG(0x40f4002c)
54 #define AD3R __REG(0x40f40030)
55 #define AD2R __REG(0x40f40034)
56 #define AD1R __REG(0x40f40038)
61 #define ASCR_RDH (1 << 31)
62 #define ASCR_D1S (1 << 2)
63 #define ASCR_D2S (1 << 1)
64 #define ASCR_D3S (1 << 0)
69 #define ARSR_GPR (1 << 3)
70 #define ARSR_LPMR (1 << 2)
71 #define ARSR_WDT (1 << 1)
72 #define ARSR_HWR (1 << 0)
77 #define ADXER_WRTC (1 << 31)
78 #define ADXER_WOST (1 << 30)
79 #define ADXER_WTSI (1 << 29)
80 #define ADXER_WUSBH (1 << 28)
81 #define ADXER_WUSB2 (1 << 26)
82 #define ADXER_WMSL0 (1 << 24)
83 #define ADXER_WDMUX3 (1 << 23)
84 #define ADXER_WDMUX2 (1 << 22)
85 #define ADXER_WKP (1 << 21)
86 #define ADXER_WUSIM1 (1 << 20)
87 #define ADXER_WUSIM0 (1 << 19)
88 #define ADXER_WOTG (1 << 16)
89 #define ADXER_MFP_WFLASH (1 << 15)
90 #define ADXER_MFP_GEN12 (1 << 14)
91 #define ADXER_MFP_WMMC2 (1 << 13)
92 #define ADXER_MFP_WMMC1 (1 << 12)
93 #define ADXER_MFP_WI2C (1 << 11)
94 #define ADXER_MFP_WSSP4 (1 << 10)
95 #define ADXER_MFP_WSSP3 (1 << 9)
96 #define ADXER_MFP_WMAXTRIX (1 << 8)
97 #define ADXER_MFP_WUART3 (1 << 7)
98 #define ADXER_MFP_WUART2 (1 << 6)
99 #define ADXER_MFP_WUART1 (1 << 5)
100 #define ADXER_MFP_WSSP2 (1 << 4)
101 #define ADXER_MFP_WSSP1 (1 << 3)
102 #define ADXER_MFP_WAC97 (1 << 2)
103 #define ADXER_WEXTWAKE1 (1 << 1)
104 #define ADXER_WEXTWAKE0 (1 << 0)
109 #define ADXR_L2 (1 << 8)
110 #define ADXR_R5 (1 << 5)
111 #define ADXR_R4 (1 << 4)
112 #define ADXR_R3 (1 << 3)
113 #define ADXR_R2 (1 << 2)
114 #define ADXR_R1 (1 << 1)
115 #define ADXR_R0 (1 << 0)
120 #define PXA3xx_PM_S3D4C4 0x07
121 #define PXA3xx_PM_S2D3C4 0x06
122 #define PXA3xx_PM_S0D2C2 0x03
123 #define PXA3xx_PM_S0D1C2 0x02
124 #define PXA3xx_PM_S0D0C1 0x01
129 #define ACCR __REG(0x41340000)
130 #define ACSR __REG(0x41340004)
131 #define AICSR __REG(0x41340008)
132 #define CKENA __REG(0x4134000C)
133 #define CKENB __REG(0x41340010)
134 #define CKENC __REG(0x41340024)
135 #define AC97_DIV __REG(0x41340014)
137 #define ACCR_XPDIS (1 << 31)
138 #define ACCR_SPDIS (1 << 30)
139 #define ACCR_D0CS (1 << 26)
140 #define ACCR_PCCE (1 << 11)
141 #define ACCR_DDR_D0CS (1 << 7)
143 #define ACCR_SMCFS_MASK (0x7 << 23)
144 #define ACCR_SFLFS_MASK (0x3 << 18)
145 #define ACCR_XSPCLK_MASK (0x3 << 16)
146 #define ACCR_HSS_MASK (0x3 << 14)
147 #define ACCR_DMCFS_MASK (0x3 << 12)
148 #define ACCR_XN_MASK (0x7 << 8)
149 #define ACCR_XL_MASK (0x1f)
151 #define ACCR_SMCFS(x) (((x) & 0x7) << 23)
152 #define ACCR_SFLFS(x) (((x) & 0x3) << 18)
153 #define ACCR_XSPCLK(x) (((x) & 0x3) << 16)
154 #define ACCR_HSS(x) (((x) & 0x3) << 14)
155 #define ACCR_DMCFS(x) (((x) & 0x3) << 12)
156 #define ACCR_XN(x) (((x) & 0x7) << 8)
157 #define ACCR_XL(x) ((x) & 0x1f)
164 #define CKEN_CAMERA 3
173 #define CKEN_KEYPAD 14
175 #define CKEN_USIM0 17
176 #define CKEN_USIM1 18
179 #define CKEN_BTUART 21
180 #define CKEN_FFUART 22
181 #define CKEN_STUART 23
183 #define CKEN_TOUCH 25
194 #define CKEN_1WIRE 40
195 #define CKEN_HSIO2 41
196 #define CKEN_MINI_IM 48
197 #define CKEN_MINI_LCD 49
203 #define CKEN_PXA300_GCU 42
204 #define CKEN_PXA320_GCU 7