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12 #define q40_master_addr 0xff000000
16 #define KEYCODE_REG 0x1c
17 #define DISPLAY_CONTROL_REG 0x18
18 #define FRAME_CLEAR_REG 0x24
21 #define Q40_LED_ON() master_outb(1,LED_REG)
22 #define Q40_LED_OFF() master_outb(0,LED_REG)
24 #define INTERRUPT_REG IIRQ_REG
25 #define KEY_IRQ_ENABLE_REG 0x08
26 #define KEYBOARD_UNLOCK_REG 0x20
28 #define SAMPLE_ENABLE_REG 0x14
29 #define SAMPLE_RATE_REG 0x2c
30 #define SAMPLE_CLEAR_REG 0x28
31 #define SAMPLE_LOW 0x00
32 #define SAMPLE_HIGH 0x01
34 #define FRAME_RATE_REG 0x38
37 #define SER_ENABLE_REG 0x0c
39 #define EXT_ENABLE_REG 0x10
42 #define master_inb(_reg_) in_8((unsigned char *)q40_master_addr+_reg_)
43 #define master_outb(_b_,_reg_) out_8((unsigned char *)q40_master_addr+_reg_,_b_)
47 #define Q40_RTC_BASE (0xff021ffc)
49 #define Q40_RTC_YEAR (*(volatile unsigned char *)(Q40_RTC_BASE+0))
50 #define Q40_RTC_MNTH (*(volatile unsigned char *)(Q40_RTC_BASE-4))
51 #define Q40_RTC_DATE (*(volatile unsigned char *)(Q40_RTC_BASE-8))
52 #define Q40_RTC_DOW (*(volatile unsigned char *)(Q40_RTC_BASE-12))
53 #define Q40_RTC_HOUR (*(volatile unsigned char *)(Q40_RTC_BASE-16))
54 #define Q40_RTC_MINS (*(volatile unsigned char *)(Q40_RTC_BASE-20))
55 #define Q40_RTC_SECS (*(volatile unsigned char *)(Q40_RTC_BASE-24))
56 #define Q40_RTC_CTRL (*(volatile unsigned char *)(Q40_RTC_BASE-28))
59 #define Q40_RTC_READ 64
60 #define Q40_RTC_WRITE 128
66 #define DAC_LEFT ((unsigned char *)0xff008000)
67 #define DAC_RIGHT ((unsigned char *)0xff008004)