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8 #ifndef __QETH_CORE_MPC_H__
9 #define __QETH_CORE_MPC_H__
13 #define IPA_PDU_HEADER_SIZE 0x40
14 #define QETH_IPA_PDU_LEN_TOTAL(buffer) (buffer + 0x0e)
15 #define QETH_IPA_PDU_LEN_PDU1(buffer) (buffer + 0x26)
16 #define QETH_IPA_PDU_LEN_PDU2(buffer) (buffer + 0x29)
17 #define QETH_IPA_PDU_LEN_PDU3(buffer) (buffer + 0x3a)
20 #define QETH_IPA_CMD_DEST_ADDR(buffer) (buffer + 0x2c)
22 #define IPA_CMD_LENGTH (IPA_PDU_HEADER_SIZE + sizeof(struct qeth_ipa_cmd))
24 #define QETH_SEQ_NO_LENGTH 4
25 #define QETH_MPC_TOKEN_LENGTH 4
26 #define QETH_MCL_LENGTH 4
27 #define OSA_ADDR_LEN 6
29 #define QETH_TIMEOUT (10 * HZ)
30 #define QETH_IPA_TIMEOUT (45 * HZ)
31 #define QETH_IDX_COMMAND_SEQNO 0xffff0000
32 #define SR_INFO_LEN 16
34 #define QETH_CLEAR_CHANNEL_PARM -10
35 #define QETH_HALT_CHANNEL_PARM -11
36 #define QETH_RCD_PARM -12
41 #define IPA_CMD_INITIATOR_HOST 0x00
42 #define IPA_CMD_INITIATOR_OSA 0x01
43 #define IPA_CMD_INITIATOR_HOST_REPLY 0x80
44 #define IPA_CMD_INITIATOR_OSA_REPLY 0x81
45 #define IPA_CMD_PRIM_VERSION_NO 0x01
56 #define QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE 0x18
74 #define RESET_ROUTING_FLAG 0x10
185 #define IPA_RC_IP_ADDRESS_NOT_DEFINED IPA_RC_PRIMARY_ALREADY_DEFINED
187 #define IPA_RC_INVALID_SUBCMD IPA_RC_IP_TABLE_FULL
188 #define IPA_RC_HARDWARE_AUTH_ERROR IPA_RC_UNKNOWN_ERROR
521 #define QETH_SETASS_BASE_LEN (sizeof(struct qeth_ipacmd_hdr) + \
522 sizeof(struct qeth_ipacmd_setassparms_hdr))
523 #define QETH_IPA_ARP_DATA_POS(buffer) (buffer + IPA_PDU_HEADER_SIZE + \
524 QETH_SETASS_BASE_LEN)
525 #define QETH_SETADP_BASE_LEN (sizeof(struct qeth_ipacmd_hdr) + \
526 sizeof(struct qeth_ipacmd_setadpparms_hdr))
527 #define QETH_SNMP_SETADP_CMDLENGTH 16
529 #define QETH_ARP_DATA_SIZE 3968
530 #define QETH_ARP_CMD_LEN (QETH_ARP_DATA_SIZE + 8)
532 #define IS_IPA_REPLY(cmd) ((cmd->hdr.initiator == IPA_CMD_INITIATOR_HOST) || \
533 (cmd->hdr.initiator == IPA_CMD_INITIATOR_OSA_REPLY))
544 #define CM_ENABLE_SIZE 0x63
545 #define QETH_CM_ENABLE_ISSUER_RM_TOKEN(buffer) (buffer + 0x2c)
546 #define QETH_CM_ENABLE_FILTER_TOKEN(buffer) (buffer + 0x53)
547 #define QETH_CM_ENABLE_USER_DATA(buffer) (buffer + 0x5b)
549 #define QETH_CM_ENABLE_RESP_FILTER_TOKEN(buffer) \
550 (PDU_ENCAPSULATION(buffer) + 0x13)
554 #define CM_SETUP_SIZE 0x64
555 #define QETH_CM_SETUP_DEST_ADDR(buffer) (buffer + 0x2c)
556 #define QETH_CM_SETUP_CONNECTION_TOKEN(buffer) (buffer + 0x51)
557 #define QETH_CM_SETUP_FILTER_TOKEN(buffer) (buffer + 0x5a)
559 #define QETH_CM_SETUP_RESP_DEST_ADDR(buffer) \
560 (PDU_ENCAPSULATION(buffer) + 0x1a)
563 #define ULP_ENABLE_SIZE 0x6b
564 #define QETH_ULP_ENABLE_LINKNUM(buffer) (buffer + 0x61)
565 #define QETH_ULP_ENABLE_DEST_ADDR(buffer) (buffer + 0x2c)
566 #define QETH_ULP_ENABLE_FILTER_TOKEN(buffer) (buffer + 0x53)
567 #define QETH_ULP_ENABLE_PORTNAME_AND_LL(buffer) (buffer + 0x62)
568 #define QETH_ULP_ENABLE_RESP_FILTER_TOKEN(buffer) \
569 (PDU_ENCAPSULATION(buffer) + 0x13)
570 #define QETH_ULP_ENABLE_RESP_MAX_MTU(buffer) \
571 (PDU_ENCAPSULATION(buffer) + 0x1f)
572 #define QETH_ULP_ENABLE_RESP_DIFINFO_LEN(buffer) \
573 (PDU_ENCAPSULATION(buffer) + 0x17)
574 #define QETH_ULP_ENABLE_RESP_LINK_TYPE(buffer) \
575 (PDU_ENCAPSULATION(buffer) + 0x2b)
577 #define QETH_PROT_LAYER2 0x08
578 #define QETH_PROT_TCPIP 0x03
579 #define QETH_PROT_OSN2 0x0a
580 #define QETH_ULP_ENABLE_PROT_TYPE(buffer) (buffer + 0x50)
581 #define QETH_IPA_CMD_PROT_TYPE(buffer) (buffer + 0x19)
584 #define ULP_SETUP_SIZE 0x6c
585 #define QETH_ULP_SETUP_DEST_ADDR(buffer) (buffer + 0x2c)
586 #define QETH_ULP_SETUP_CONNECTION_TOKEN(buffer) (buffer + 0x51)
587 #define QETH_ULP_SETUP_FILTER_TOKEN(buffer) (buffer + 0x5a)
588 #define QETH_ULP_SETUP_CUA(buffer) (buffer + 0x68)
589 #define QETH_ULP_SETUP_REAL_DEVADDR(buffer) (buffer + 0x6a)
591 #define QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(buffer) \
592 (PDU_ENCAPSULATION(buffer) + 0x1a)
595 extern unsigned char DM_ACT[];
596 #define DM_ACT_SIZE 0x55
597 #define QETH_DM_ACT_DEST_ADDR(buffer) (buffer + 0x2c)
598 #define QETH_DM_ACT_CONNECTION_TOKEN(buffer) (buffer + 0x51)
602 #define QETH_TRANSPORT_HEADER_SEQ_NO(buffer) (buffer + 4)
603 #define QETH_PDU_HEADER_SEQ_NO(buffer) (buffer + 0x1c)
604 #define QETH_PDU_HEADER_ACK_SEQ_NO(buffer) (buffer + 0x20)
609 #define IDX_ACTIVATE_SIZE 0x22
610 #define QETH_IDX_ACT_PNO(buffer) (buffer+0x0b)
611 #define QETH_IDX_ACT_ISSUER_RM_TOKEN(buffer) (buffer + 0x0c)
612 #define QETH_IDX_NO_PORTNAME_REQUIRED(buffer) ((buffer)[0x0b] & 0x80)
613 #define QETH_IDX_ACT_FUNC_LEVEL(buffer) (buffer + 0x10)
614 #define QETH_IDX_ACT_DATASET_NAME(buffer) (buffer + 0x16)
615 #define QETH_IDX_ACT_QDIO_DEV_CUA(buffer) (buffer + 0x1e)
616 #define QETH_IDX_ACT_QDIO_DEV_REALADDR(buffer) (buffer + 0x20)
617 #define QETH_IS_IDX_ACT_POS_REPLY(buffer) (((buffer)[0x08] & 3) == 2)
618 #define QETH_IDX_REPLY_LEVEL(buffer) (buffer + 0x12)
619 #define QETH_IDX_ACT_CAUSE_CODE(buffer) (buffer)[0x09]
620 #define QETH_IDX_ACT_ERR_EXCL 0x19
621 #define QETH_IDX_ACT_ERR_AUTH 0x1E
622 #define QETH_IDX_ACT_ERR_AUTH_USER 0x20
624 #define PDU_ENCAPSULATION(buffer) \
625 (buffer + *(buffer + (*(buffer + 0x0b)) + \
626 *(buffer + *(buffer + 0x0b) + 0x11) + 0x07))
628 #define IS_IPA(buffer) \
630 (*(buffer + ((*(buffer + 0x0b)) + 4)) == 0xc1))
632 #define ADDR_FRAME_TYPE_DIX 1
633 #define ADDR_FRAME_TYPE_802_3 2
634 #define ADDR_FRAME_TYPE_TR_WITHOUT_SR 0x10
635 #define ADDR_FRAME_TYPE_TR_WITH_SR 0x20