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qla_bsg.h
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1 /*
2  * QLogic Fibre Channel HBA Driver
3  * Copyright (c) 2003-2012 QLogic Corporation
4  *
5  * See LICENSE.qla2xxx for copyright and licensing details.
6  */
7 #ifndef __QLA_BSG_H
8 #define __QLA_BSG_H
9 
10 /* BSG Vendor specific commands */
11 #define QL_VND_LOOPBACK 0x01
12 #define QL_VND_A84_RESET 0x02
13 #define QL_VND_A84_UPDATE_FW 0x03
14 #define QL_VND_A84_MGMT_CMD 0x04
15 #define QL_VND_IIDMA 0x05
16 #define QL_VND_FCP_PRIO_CFG_CMD 0x06
17 #define QL_VND_READ_FLASH 0x07
18 #define QL_VND_UPDATE_FLASH 0x08
19 #define QL_VND_SET_FRU_VERSION 0x0B
20 #define QL_VND_READ_FRU_STATUS 0x0C
21 #define QL_VND_WRITE_FRU_STATUS 0x0D
22 #define QL_VND_DIAG_IO_CMD 0x0A
23 #define QL_VND_WRITE_I2C 0x10
24 #define QL_VND_READ_I2C 0x11
25 
26 /* BSG Vendor specific subcode returns */
27 #define EXT_STATUS_OK 0
28 #define EXT_STATUS_ERR 1
29 #define EXT_STATUS_BUSY 2
30 #define EXT_STATUS_INVALID_PARAM 6
31 #define EXT_STATUS_DATA_OVERRUN 7
32 #define EXT_STATUS_DATA_UNDERRUN 8
33 #define EXT_STATUS_MAILBOX 11
34 #define EXT_STATUS_NO_MEMORY 17
35 #define EXT_STATUS_DEVICE_OFFLINE 22
36 
37 /*
38  * To support bidirectional iocb
39  * BSG Vendor specific returns
40  */
41 #define EXT_STATUS_NOT_SUPPORTED 27
42 #define EXT_STATUS_INVALID_CFG 28
43 #define EXT_STATUS_DMA_ERR 29
44 #define EXT_STATUS_TIMEOUT 30
45 #define EXT_STATUS_THREAD_FAILED 31
46 #define EXT_STATUS_DATA_CMP_FAILED 32
47 
48 /* BSG definations for interpreting CommandSent field */
49 #define INT_DEF_LB_LOOPBACK_CMD 0
50 #define INT_DEF_LB_ECHO_CMD 1
51 
52 /* Loopback related definations */
53 #define INTERNAL_LOOPBACK 0xF1
54 #define EXTERNAL_LOOPBACK 0xF2
55 #define ENABLE_INTERNAL_LOOPBACK 0x02
56 #define ENABLE_EXTERNAL_LOOPBACK 0x04
57 #define INTERNAL_LOOPBACK_MASK 0x000E
58 #define MAX_ELS_FRAME_PAYLOAD 252
59 #define ELS_OPCODE_BYTE 0x10
60 
61 /* BSG Vendor specific definations */
62 #define A84_ISSUE_WRITE_TYPE_CMD 0
63 #define A84_ISSUE_READ_TYPE_CMD 1
64 #define A84_CLEANUP_CMD 2
65 #define A84_ISSUE_RESET_OP_FW 3
66 #define A84_ISSUE_RESET_DIAG_FW 4
67 #define A84_ISSUE_UPDATE_OPFW_CMD 5
68 #define A84_ISSUE_UPDATE_DIAGFW_CMD 6
69 
71  union {
72  struct {
74  } mem; /* for QLA84_MGMT_READ/WRITE_MEM */
75  struct {
77 #define QLA84_MGMT_CONFIG_ID_UIF 1
78 #define QLA84_MGMT_CONFIG_ID_FCOE_COS 2
79 #define QLA84_MGMT_CONFIG_ID_PAUSE 3
80 #define QLA84_MGMT_CONFIG_ID_TIMEOUTS 4
81 
84  } config; /* for QLA84_MGMT_CHNG_CONFIG */
85 
86  struct {
88 #define QLA84_MGMT_INFO_CONFIG_LOG_DATA 1 /* Get Config Log Data */
89 #define QLA84_MGMT_INFO_LOG_DATA 2 /* Get Log Data */
90 #define QLA84_MGMT_INFO_PORT_STAT 3 /* Get Port Statistics */
91 #define QLA84_MGMT_INFO_LIF_STAT 4 /* Get LIF Statistics */
92 #define QLA84_MGMT_INFO_ASIC_STAT 5 /* Get ASIC Statistics */
93 #define QLA84_MGMT_INFO_CONFIG_PARAMS 6 /* Get Config Parameters */
94 #define QLA84_MGMT_INFO_PANIC_LOG 7 /* Get Panic Log */
95 
97 /*
98 * context definitions for QLA84_MGMT_INFO_CONFIG_LOG_DATA
99 */
100 #define IC_LOG_DATA_LOG_ID_DEBUG_LOG 0
101 #define IC_LOG_DATA_LOG_ID_LEARN_LOG 1
102 #define IC_LOG_DATA_LOG_ID_FC_ACL_INGRESS_LOG 2
103 #define IC_LOG_DATA_LOG_ID_FC_ACL_EGRESS_LOG 3
104 #define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_INGRESS_LOG 4
105 #define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_EGRESS_LOG 5
106 #define IC_LOG_DATA_LOG_ID_MESSAGE_TRANSMIT_LOG 6
107 #define IC_LOG_DATA_LOG_ID_MESSAGE_RECEIVE_LOG 7
108 #define IC_LOG_DATA_LOG_ID_LINK_EVENT_LOG 8
109 #define IC_LOG_DATA_LOG_ID_DCX_LOG 9
110 
111 /*
112 * context definitions for QLA84_MGMT_INFO_PORT_STAT
113 */
114 #define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT0 0
115 #define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT1 1
116 #define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT0 2
117 #define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT1 3
118 #define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT0 4
119 #define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT1 5
120 
121 
122 /*
123 * context definitions for QLA84_MGMT_INFO_LIF_STAT
124 */
125 #define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT0 0
126 #define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT1 1
127 #define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT0 2
128 #define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT1 3
129 #define IC_LIF_STATISTICS_LIF_NUMBER_CPU 6
130 
131  } info; /* for QLA84_MGMT_GET_INFO */
132  } u;
133 };
134 
137 #define QLA84_MGMT_READ_MEM 0x00
138 #define QLA84_MGMT_WRITE_MEM 0x01
139 #define QLA84_MGMT_CHNG_CONFIG 0x02
140 #define QLA84_MGMT_GET_INFO 0x03
142  struct qla84_mgmt_param mgmtp;/* parameters for cmd */
143  uint32_t len; /* bytes in payload following this struct */
144  uint8_t payload[0]; /* payload for cmd */
145 };
146 
149 } __attribute__ ((packed));
154 } __attribute__ ((packed));
157  union {
160  uint8_t id[4];
162  } dest_addr;
164 #define EXT_DEF_TYPE_WWPN 2
167 } __attribute__ ((packed));
168 
173 } __attribute__ ((packed));
176 /* FRU VPD */
178 #define MAX_FRU_SIZE 36
179 
184 } __packed;
185 
188 } __packed;
189 
193 } __packed;
194 
198 } __packed;
199 
204 } __packed;
205 
212 } __packed;
213 
214 #endif