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regs-dsc.h
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1 /* arch/arm/mach-s3c2410/include/mach/regs-dsc.h
2  *
3  * Copyright (c) 2004 Simtec Electronics <[email protected]>
4  * http://www.simtec.co.uk/products/SWLINUX/
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * S3C2440/S3C2412 Signal Drive Strength Control
11 */
12 
13 
14 #ifndef __ASM_ARCH_REGS_DSC_H
15 #define __ASM_ARCH_REGS_DSC_H "2440-dsc"
16 
17 #if defined(CONFIG_CPU_S3C2412)
18 #define S3C2412_DSC0 S3C2410_GPIOREG(0xdc)
19 #define S3C2412_DSC1 S3C2410_GPIOREG(0xe0)
20 #endif
21 
22 #if defined(CONFIG_CPU_S3C2416)
23 #define S3C2416_DSC0 S3C2410_GPIOREG(0xc0)
24 #define S3C2416_DSC1 S3C2410_GPIOREG(0xc4)
25 #define S3C2416_DSC2 S3C2410_GPIOREG(0xc8)
26 #define S3C2416_DSC3 S3C2410_GPIOREG(0x110)
27 
28 #define S3C2416_SELECT_DSC0 (0 << 30)
29 #define S3C2416_SELECT_DSC1 (1 << 30)
30 #define S3C2416_SELECT_DSC2 (2 << 30)
31 #define S3C2416_SELECT_DSC3 (3 << 30)
32 
33 #define S3C2416_DSC_GETSHIFT(x) (x & 30)
34 
35 #define S3C2416_DSC0_CF (S3C2416_SELECT_DSC0 | 28)
36 #define S3C2416_DSC0_CF_5mA (0 << 28)
37 #define S3C2416_DSC0_CF_10mA (1 << 28)
38 #define S3C2416_DSC0_CF_15mA (2 << 28)
39 #define S3C2416_DSC0_CF_21mA (3 << 28)
40 #define S3C2416_DSC0_CF_MASK (3 << 28)
41 
42 #define S3C2416_DSC0_nRBE (S3C2416_SELECT_DSC0 | 26)
43 #define S3C2416_DSC0_nRBE_5mA (0 << 26)
44 #define S3C2416_DSC0_nRBE_10mA (1 << 26)
45 #define S3C2416_DSC0_nRBE_15mA (2 << 26)
46 #define S3C2416_DSC0_nRBE_21mA (3 << 26)
47 #define S3C2416_DSC0_nRBE_MASK (3 << 26)
48 
49 #define S3C2416_DSC0_nROE (S3C2416_SELECT_DSC0 | 24)
50 #define S3C2416_DSC0_nROE_5mA (0 << 24)
51 #define S3C2416_DSC0_nROE_10mA (1 << 24)
52 #define S3C2416_DSC0_nROE_15mA (2 << 24)
53 #define S3C2416_DSC0_nROE_21mA (3 << 24)
54 #define S3C2416_DSC0_nROE_MASK (3 << 24)
55 
56 #endif
57 
58 #if defined(CONFIG_CPU_S3C244X)
59 
60 #define S3C2440_DSC0 S3C2410_GPIOREG(0xc4)
61 #define S3C2440_DSC1 S3C2410_GPIOREG(0xc8)
62 
63 #define S3C2440_SELECT_DSC0 (0)
64 #define S3C2440_SELECT_DSC1 (1<<31)
65 
66 #define S3C2440_DSC_GETSHIFT(x) ((x) & 31)
67 
68 #define S3C2440_DSC0_DISABLE (1<<31)
69 
70 #define S3C2440_DSC0_ADDR (S3C2440_SELECT_DSC0 | 8)
71 #define S3C2440_DSC0_ADDR_12mA (0<<8)
72 #define S3C2440_DSC0_ADDR_10mA (1<<8)
73 #define S3C2440_DSC0_ADDR_8mA (2<<8)
74 #define S3C2440_DSC0_ADDR_6mA (3<<8)
75 #define S3C2440_DSC0_ADDR_MASK (3<<8)
76 
77 /* D24..D31 */
78 #define S3C2440_DSC0_DATA3 (S3C2440_SELECT_DSC0 | 6)
79 #define S3C2440_DSC0_DATA3_12mA (0<<6)
80 #define S3C2440_DSC0_DATA3_10mA (1<<6)
81 #define S3C2440_DSC0_DATA3_8mA (2<<6)
82 #define S3C2440_DSC0_DATA3_6mA (3<<6)
83 #define S3C2440_DSC0_DATA3_MASK (3<<6)
84 
85 /* D16..D23 */
86 #define S3C2440_DSC0_DATA2 (S3C2440_SELECT_DSC0 | 4)
87 #define S3C2440_DSC0_DATA2_12mA (0<<4)
88 #define S3C2440_DSC0_DATA2_10mA (1<<4)
89 #define S3C2440_DSC0_DATA2_8mA (2<<4)
90 #define S3C2440_DSC0_DATA2_6mA (3<<4)
91 #define S3C2440_DSC0_DATA2_MASK (3<<4)
92 
93 /* D8..D15 */
94 #define S3C2440_DSC0_DATA1 (S3C2440_SELECT_DSC0 | 2)
95 #define S3C2440_DSC0_DATA1_12mA (0<<2)
96 #define S3C2440_DSC0_DATA1_10mA (1<<2)
97 #define S3C2440_DSC0_DATA1_8mA (2<<2)
98 #define S3C2440_DSC0_DATA1_6mA (3<<2)
99 #define S3C2440_DSC0_DATA1_MASK (3<<2)
100 
101 /* D0..D7 */
102 #define S3C2440_DSC0_DATA0 (S3C2440_SELECT_DSC0 | 0)
103 #define S3C2440_DSC0_DATA0_12mA (0<<0)
104 #define S3C2440_DSC0_DATA0_10mA (1<<0)
105 #define S3C2440_DSC0_DATA0_8mA (2<<0)
106 #define S3C2440_DSC0_DATA0_6mA (3<<0)
107 #define S3C2440_DSC0_DATA0_MASK (3<<0)
108 
109 #define S3C2440_DSC1_SCK1 (S3C2440_SELECT_DSC1 | 28)
110 #define S3C2440_DSC1_SCK1_12mA (0<<28)
111 #define S3C2440_DSC1_SCK1_10mA (1<<28)
112 #define S3C2440_DSC1_SCK1_8mA (2<<28)
113 #define S3C2440_DSC1_SCK1_6mA (3<<28)
114 #define S3C2440_DSC1_SCK1_MASK (3<<28)
115 
116 #define S3C2440_DSC1_SCK0 (S3C2440_SELECT_DSC1 | 26)
117 #define S3C2440_DSC1_SCK0_12mA (0<<26)
118 #define S3C2440_DSC1_SCK0_10mA (1<<26)
119 #define S3C2440_DSC1_SCK0_8mA (2<<26)
120 #define S3C2440_DSC1_SCK0_6mA (3<<26)
121 #define S3C2440_DSC1_SCK0_MASK (3<<26)
122 
123 #define S3C2440_DSC1_SCKE (S3C2440_SELECT_DSC1 | 24)
124 #define S3C2440_DSC1_SCKE_10mA (0<<24)
125 #define S3C2440_DSC1_SCKE_8mA (1<<24)
126 #define S3C2440_DSC1_SCKE_6mA (2<<24)
127 #define S3C2440_DSC1_SCKE_4mA (3<<24)
128 #define S3C2440_DSC1_SCKE_MASK (3<<24)
129 
130 /* SDRAM nRAS/nCAS */
131 #define S3C2440_DSC1_SDR (S3C2440_SELECT_DSC1 | 22)
132 #define S3C2440_DSC1_SDR_10mA (0<<22)
133 #define S3C2440_DSC1_SDR_8mA (1<<22)
134 #define S3C2440_DSC1_SDR_6mA (2<<22)
135 #define S3C2440_DSC1_SDR_4mA (3<<22)
136 #define S3C2440_DSC1_SDR_MASK (3<<22)
137 
138 /* NAND Flash Controller */
139 #define S3C2440_DSC1_NFC (S3C2440_SELECT_DSC1 | 20)
140 #define S3C2440_DSC1_NFC_10mA (0<<20)
141 #define S3C2440_DSC1_NFC_8mA (1<<20)
142 #define S3C2440_DSC1_NFC_6mA (2<<20)
143 #define S3C2440_DSC1_NFC_4mA (3<<20)
144 #define S3C2440_DSC1_NFC_MASK (3<<20)
145 
146 /* nBE[0..3] */
147 #define S3C2440_DSC1_nBE (S3C2440_SELECT_DSC1 | 18)
148 #define S3C2440_DSC1_nBE_10mA (0<<18)
149 #define S3C2440_DSC1_nBE_8mA (1<<18)
150 #define S3C2440_DSC1_nBE_6mA (2<<18)
151 #define S3C2440_DSC1_nBE_4mA (3<<18)
152 #define S3C2440_DSC1_nBE_MASK (3<<18)
153 
154 #define S3C2440_DSC1_WOE (S3C2440_SELECT_DSC1 | 16)
155 #define S3C2440_DSC1_WOE_10mA (0<<16)
156 #define S3C2440_DSC1_WOE_8mA (1<<16)
157 #define S3C2440_DSC1_WOE_6mA (2<<16)
158 #define S3C2440_DSC1_WOE_4mA (3<<16)
159 #define S3C2440_DSC1_WOE_MASK (3<<16)
160 
161 #define S3C2440_DSC1_CS7 (S3C2440_SELECT_DSC1 | 14)
162 #define S3C2440_DSC1_CS7_10mA (0<<14)
163 #define S3C2440_DSC1_CS7_8mA (1<<14)
164 #define S3C2440_DSC1_CS7_6mA (2<<14)
165 #define S3C2440_DSC1_CS7_4mA (3<<14)
166 #define S3C2440_DSC1_CS7_MASK (3<<14)
167 
168 #define S3C2440_DSC1_CS6 (S3C2440_SELECT_DSC1 | 12)
169 #define S3C2440_DSC1_CS6_10mA (0<<12)
170 #define S3C2440_DSC1_CS6_8mA (1<<12)
171 #define S3C2440_DSC1_CS6_6mA (2<<12)
172 #define S3C2440_DSC1_CS6_4mA (3<<12)
173 #define S3C2440_DSC1_CS6_MASK (3<<12)
174 
175 #define S3C2440_DSC1_CS5 (S3C2440_SELECT_DSC1 | 10)
176 #define S3C2440_DSC1_CS5_10mA (0<<10)
177 #define S3C2440_DSC1_CS5_8mA (1<<10)
178 #define S3C2440_DSC1_CS5_6mA (2<<10)
179 #define S3C2440_DSC1_CS5_4mA (3<<10)
180 #define S3C2440_DSC1_CS5_MASK (3<<10)
181 
182 #define S3C2440_DSC1_CS4 (S3C2440_SELECT_DSC1 | 8)
183 #define S3C2440_DSC1_CS4_10mA (0<<8)
184 #define S3C2440_DSC1_CS4_8mA (1<<8)
185 #define S3C2440_DSC1_CS4_6mA (2<<8)
186 #define S3C2440_DSC1_CS4_4mA (3<<8)
187 #define S3C2440_DSC1_CS4_MASK (3<<8)
188 
189 #define S3C2440_DSC1_CS3 (S3C2440_SELECT_DSC1 | 6)
190 #define S3C2440_DSC1_CS3_10mA (0<<6)
191 #define S3C2440_DSC1_CS3_8mA (1<<6)
192 #define S3C2440_DSC1_CS3_6mA (2<<6)
193 #define S3C2440_DSC1_CS3_4mA (3<<6)
194 #define S3C2440_DSC1_CS3_MASK (3<<6)
195 
196 #define S3C2440_DSC1_CS2 (S3C2440_SELECT_DSC1 | 4)
197 #define S3C2440_DSC1_CS2_10mA (0<<4)
198 #define S3C2440_DSC1_CS2_8mA (1<<4)
199 #define S3C2440_DSC1_CS2_6mA (2<<4)
200 #define S3C2440_DSC1_CS2_4mA (3<<4)
201 #define S3C2440_DSC1_CS2_MASK (3<<4)
202 
203 #define S3C2440_DSC1_CS1 (S3C2440_SELECT_DSC1 | 2)
204 #define S3C2440_DSC1_CS1_10mA (0<<2)
205 #define S3C2440_DSC1_CS1_8mA (1<<2)
206 #define S3C2440_DSC1_CS1_6mA (2<<2)
207 #define S3C2440_DSC1_CS1_4mA (3<<2)
208 #define S3C2440_DSC1_CS1_MASK (3<<2)
209 
210 #define S3C2440_DSC1_CS0 (S3C2440_SELECT_DSC1 | 0)
211 #define S3C2440_DSC1_CS0_10mA (0<<0)
212 #define S3C2440_DSC1_CS0_8mA (1<<0)
213 #define S3C2440_DSC1_CS0_6mA (2<<0)
214 #define S3C2440_DSC1_CS0_4mA (3<<0)
215 #define S3C2440_DSC1_CS0_MASK (3<<0)
216 
217 #endif /* CONFIG_CPU_S3C2440 */
218 
219 #endif /* __ASM_ARCH_REGS_DSC_H */
220