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rt2800.h
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1 /*
2  Copyright (C) 2004 - 2010 Ivo van Doorn <[email protected]>
3  Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
4  Copyright (C) 2009 Alban Browaeys <[email protected]>
5  Copyright (C) 2009 Felix Fietkau <[email protected]>
6  Copyright (C) 2009 Luis Correia <[email protected]>
7  Copyright (C) 2009 Mattias Nissler <[email protected]>
8  Copyright (C) 2009 Mark Asselstine <[email protected]>
9  Copyright (C) 2009 Xose Vazquez Perez <[email protected]>
10  Copyright (C) 2009 Bart Zolnierkiewicz <[email protected]>
11  <http://rt2x00.serialmonkey.com>
12 
13  This program is free software; you can redistribute it and/or modify
14  it under the terms of the GNU General Public License as published by
15  the Free Software Foundation; either version 2 of the License, or
16  (at your option) any later version.
17 
18  This program is distributed in the hope that it will be useful,
19  but WITHOUT ANY WARRANTY; without even the implied warranty of
20  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  GNU General Public License for more details.
22 
23  You should have received a copy of the GNU General Public License
24  along with this program; if not, write to the
25  Free Software Foundation, Inc.,
26  59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27  */
28 
29 /*
30  Module: rt2800
31  Abstract: Data structures and registers for the rt2800 modules.
32  Supported chipsets: RT2800E, RT2800ED & RT2800U.
33  */
34 
35 #ifndef RT2800_H
36 #define RT2800_H
37 
38 /*
39  * RF chip defines.
40  *
41  * RF2820 2.4G 2T3R
42  * RF2850 2.4G/5G 2T3R
43  * RF2720 2.4G 1T2R
44  * RF2750 2.4G/5G 1T2R
45  * RF3020 2.4G 1T1R
46  * RF2020 2.4G B/G
47  * RF3021 2.4G 1T2R
48  * RF3022 2.4G 2T2R
49  * RF3052 2.4G/5G 2T2R
50  * RF2853 2.4G/5G 3T3R
51  * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
52  * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
53  * RF3053 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
54  * RF5360 2.4G 1T1R
55  * RF5370 2.4G 1T1R
56  * RF5390 2.4G 1T1R
57  */
58 #define RF2820 0x0001
59 #define RF2850 0x0002
60 #define RF2720 0x0003
61 #define RF2750 0x0004
62 #define RF3020 0x0005
63 #define RF2020 0x0006
64 #define RF3021 0x0007
65 #define RF3022 0x0008
66 #define RF3052 0x0009
67 #define RF2853 0x000a
68 #define RF3320 0x000b
69 #define RF3322 0x000c
70 #define RF3053 0x000d
71 #define RF3290 0x3290
72 #define RF5360 0x5360
73 #define RF5370 0x5370
74 #define RF5372 0x5372
75 #define RF5390 0x5390
76 #define RF5392 0x5392
77 
78 /*
79  * Chipset revisions.
80  */
81 #define REV_RT2860C 0x0100
82 #define REV_RT2860D 0x0101
83 #define REV_RT2872E 0x0200
84 #define REV_RT3070E 0x0200
85 #define REV_RT3070F 0x0201
86 #define REV_RT3071E 0x0211
87 #define REV_RT3090E 0x0211
88 #define REV_RT3390E 0x0211
89 #define REV_RT5390F 0x0502
90 #define REV_RT5390R 0x1502
91 
92 /*
93  * Signal information.
94  * Default offset is required for RSSI <-> dBm conversion.
95  */
96 #define DEFAULT_RSSI_OFFSET 120
97 
98 /*
99  * Register layout information.
100  */
101 #define CSR_REG_BASE 0x1000
102 #define CSR_REG_SIZE 0x0800
103 #define EEPROM_BASE 0x0000
104 #define EEPROM_SIZE 0x0110
105 #define BBP_BASE 0x0000
106 #define BBP_SIZE 0x00ff
107 #define RF_BASE 0x0004
108 #define RF_SIZE 0x0010
109 #define RFCSR_BASE 0x0000
110 #define RFCSR_SIZE 0x0040
111 
112 /*
113  * Number of TX queues.
114  */
115 #define NUM_TX_QUEUES 4
116 
117 /*
118  * Registers.
119  */
120 
121 
122 /*
123  * MAC_CSR0_3290: MAC_CSR0 for RT3290 to identity MAC version number.
124  */
125 #define MAC_CSR0_3290 0x0000
126 
127 /*
128  * E2PROM_CSR: PCI EEPROM control register.
129  * RELOAD: Write 1 to reload eeprom content.
130  * TYPE: 0: 93c46, 1:93c66.
131  * LOAD_STATUS: 1:loading, 0:done.
132  */
133 #define E2PROM_CSR 0x0004
134 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
135 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
136 #define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
137 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
138 #define E2PROM_CSR_TYPE FIELD32(0x00000030)
139 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
140 #define E2PROM_CSR_RELOAD FIELD32(0x00000080)
141 
142 /*
143  * CMB_CTRL_CFG
144  */
145 #define CMB_CTRL 0x0020
146 #define AUX_OPT_BIT0 FIELD32(0x00000001)
147 #define AUX_OPT_BIT1 FIELD32(0x00000002)
148 #define AUX_OPT_BIT2 FIELD32(0x00000004)
149 #define AUX_OPT_BIT3 FIELD32(0x00000008)
150 #define AUX_OPT_BIT4 FIELD32(0x00000010)
151 #define AUX_OPT_BIT5 FIELD32(0x00000020)
152 #define AUX_OPT_BIT6 FIELD32(0x00000040)
153 #define AUX_OPT_BIT7 FIELD32(0x00000080)
154 #define AUX_OPT_BIT8 FIELD32(0x00000100)
155 #define AUX_OPT_BIT9 FIELD32(0x00000200)
156 #define AUX_OPT_BIT10 FIELD32(0x00000400)
157 #define AUX_OPT_BIT11 FIELD32(0x00000800)
158 #define AUX_OPT_BIT12 FIELD32(0x00001000)
159 #define AUX_OPT_BIT13 FIELD32(0x00002000)
160 #define AUX_OPT_BIT14 FIELD32(0x00004000)
161 #define AUX_OPT_BIT15 FIELD32(0x00008000)
162 #define LDO25_LEVEL FIELD32(0x00030000)
163 #define LDO25_LARGEA FIELD32(0x00040000)
164 #define LDO25_FRC_ON FIELD32(0x00080000)
165 #define CMB_RSV FIELD32(0x00300000)
166 #define XTAL_RDY FIELD32(0x00400000)
167 #define PLL_LD FIELD32(0x00800000)
168 #define LDO_CORE_LEVEL FIELD32(0x0F000000)
169 #define LDO_BGSEL FIELD32(0x30000000)
170 #define LDO3_EN FIELD32(0x40000000)
171 #define LDO0_EN FIELD32(0x80000000)
172 
173 /*
174  * EFUSE_CSR_3290: RT3290 EEPROM
175  */
176 #define EFUSE_CTRL_3290 0x0024
177 
178 /*
179  * EFUSE_DATA3 of 3290
180  */
181 #define EFUSE_DATA3_3290 0x0028
182 
183 /*
184  * EFUSE_DATA2 of 3290
185  */
186 #define EFUSE_DATA2_3290 0x002c
187 
188 /*
189  * EFUSE_DATA1 of 3290
190  */
191 #define EFUSE_DATA1_3290 0x0030
192 
193 /*
194  * EFUSE_DATA0 of 3290
195  */
196 #define EFUSE_DATA0_3290 0x0034
197 
198 /*
199  * OSC_CTRL_CFG
200  * Ring oscillator configuration
201  */
202 #define OSC_CTRL 0x0038
203 #define OSC_REF_CYCLE FIELD32(0x00001fff)
204 #define OSC_RSV FIELD32(0x0000e000)
205 #define OSC_CAL_CNT FIELD32(0x0fff0000)
206 #define OSC_CAL_ACK FIELD32(0x10000000)
207 #define OSC_CLK_32K_VLD FIELD32(0x20000000)
208 #define OSC_CAL_REQ FIELD32(0x40000000)
209 #define OSC_ROSC_EN FIELD32(0x80000000)
210 
211 /*
212  * COEX_CFG_0
213  */
214 #define COEX_CFG0 0x0040
215 #define COEX_CFG_ANT FIELD32(0xff000000)
216 /*
217  * COEX_CFG_1
218  */
219 #define COEX_CFG1 0x0044
220 
221 /*
222  * COEX_CFG_2
223  */
224 #define COEX_CFG2 0x0048
225 #define BT_COEX_CFG1 FIELD32(0xff000000)
226 #define BT_COEX_CFG0 FIELD32(0x00ff0000)
227 #define WL_COEX_CFG1 FIELD32(0x0000ff00)
228 #define WL_COEX_CFG0 FIELD32(0x000000ff)
229 /*
230  * PLL_CTRL_CFG
231  * PLL configuration register
232  */
233 #define PLL_CTRL 0x0050
234 #define PLL_RESERVED_INPUT1 FIELD32(0x000000ff)
235 #define PLL_RESERVED_INPUT2 FIELD32(0x0000ff00)
236 #define PLL_CONTROL FIELD32(0x00070000)
237 #define PLL_LPF_R1 FIELD32(0x00080000)
238 #define PLL_LPF_C1_CTRL FIELD32(0x00300000)
239 #define PLL_LPF_C2_CTRL FIELD32(0x00c00000)
240 #define PLL_CP_CURRENT_CTRL FIELD32(0x03000000)
241 #define PLL_PFD_DELAY_CTRL FIELD32(0x0c000000)
242 #define PLL_LOCK_CTRL FIELD32(0x70000000)
243 #define PLL_VBGBK_EN FIELD32(0x80000000)
244 
245 
246 /*
247  * WLAN_CTRL_CFG
248  * RT3290 wlan configuration
249  */
250 #define WLAN_FUN_CTRL 0x0080
251 #define WLAN_EN FIELD32(0x00000001)
252 #define WLAN_CLK_EN FIELD32(0x00000002)
253 #define WLAN_RSV1 FIELD32(0x00000004)
254 #define WLAN_RESET FIELD32(0x00000008)
255 #define PCIE_APP0_CLK_REQ FIELD32(0x00000010)
256 #define FRC_WL_ANT_SET FIELD32(0x00000020)
257 #define INV_TR_SW0 FIELD32(0x00000040)
258 #define WLAN_GPIO_IN_BIT0 FIELD32(0x00000100)
259 #define WLAN_GPIO_IN_BIT1 FIELD32(0x00000200)
260 #define WLAN_GPIO_IN_BIT2 FIELD32(0x00000400)
261 #define WLAN_GPIO_IN_BIT3 FIELD32(0x00000800)
262 #define WLAN_GPIO_IN_BIT4 FIELD32(0x00001000)
263 #define WLAN_GPIO_IN_BIT5 FIELD32(0x00002000)
264 #define WLAN_GPIO_IN_BIT6 FIELD32(0x00004000)
265 #define WLAN_GPIO_IN_BIT7 FIELD32(0x00008000)
266 #define WLAN_GPIO_IN_BIT_ALL FIELD32(0x0000ff00)
267 #define WLAN_GPIO_OUT_BIT0 FIELD32(0x00010000)
268 #define WLAN_GPIO_OUT_BIT1 FIELD32(0x00020000)
269 #define WLAN_GPIO_OUT_BIT2 FIELD32(0x00040000)
270 #define WLAN_GPIO_OUT_BIT3 FIELD32(0x00050000)
271 #define WLAN_GPIO_OUT_BIT4 FIELD32(0x00100000)
272 #define WLAN_GPIO_OUT_BIT5 FIELD32(0x00200000)
273 #define WLAN_GPIO_OUT_BIT6 FIELD32(0x00400000)
274 #define WLAN_GPIO_OUT_BIT7 FIELD32(0x00800000)
275 #define WLAN_GPIO_OUT_BIT_ALL FIELD32(0x00ff0000)
276 #define WLAN_GPIO_OUT_OE_BIT0 FIELD32(0x01000000)
277 #define WLAN_GPIO_OUT_OE_BIT1 FIELD32(0x02000000)
278 #define WLAN_GPIO_OUT_OE_BIT2 FIELD32(0x04000000)
279 #define WLAN_GPIO_OUT_OE_BIT3 FIELD32(0x08000000)
280 #define WLAN_GPIO_OUT_OE_BIT4 FIELD32(0x10000000)
281 #define WLAN_GPIO_OUT_OE_BIT5 FIELD32(0x20000000)
282 #define WLAN_GPIO_OUT_OE_BIT6 FIELD32(0x40000000)
283 #define WLAN_GPIO_OUT_OE_BIT7 FIELD32(0x80000000)
284 #define WLAN_GPIO_OUT_OE_BIT_ALL FIELD32(0xff000000)
285 
286 /*
287  * AUX_CTRL: Aux/PCI-E related configuration
288  */
289 #define AUX_CTRL 0x10c
290 #define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002)
291 #define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400)
292 
293 /*
294  * OPT_14: Unknown register used by rt3xxx devices.
295  */
296 #define OPT_14_CSR 0x0114
297 #define OPT_14_CSR_BIT0 FIELD32(0x00000001)
298 
299 /*
300  * INT_SOURCE_CSR: Interrupt source register.
301  * Write one to clear corresponding bit.
302  * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
303  */
304 #define INT_SOURCE_CSR 0x0200
305 #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
306 #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
307 #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
308 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
309 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
310 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
311 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
312 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
313 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
314 #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
315 #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
316 #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
317 #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
318 #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
319 #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
320 #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
321 #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
322 #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
323 
324 /*
325  * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
326  */
327 #define INT_MASK_CSR 0x0204
328 #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
329 #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
330 #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
331 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
332 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
333 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
334 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
335 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
336 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
337 #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
338 #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
339 #define INT_MASK_CSR_TBTT FIELD32(0x00000800)
340 #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
341 #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
342 #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
343 #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
344 #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
345 #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
346 
347 /*
348  * WPDMA_GLO_CFG
349  */
350 #define WPDMA_GLO_CFG 0x0208
351 #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
352 #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
353 #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
354 #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
355 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
356 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
357 #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
358 #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
359 #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
360 
361 /*
362  * WPDMA_RST_IDX
363  */
364 #define WPDMA_RST_IDX 0x020c
365 #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
366 #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
367 #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
368 #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
369 #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
370 #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
371 #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
372 
373 /*
374  * DELAY_INT_CFG
375  */
376 #define DELAY_INT_CFG 0x0210
377 #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
378 #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
379 #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
380 #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
381 #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
382 #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
383 
384 /*
385  * WMM_AIFSN_CFG: Aifsn for each EDCA AC
386  * AIFSN0: AC_VO
387  * AIFSN1: AC_VI
388  * AIFSN2: AC_BE
389  * AIFSN3: AC_BK
390  */
391 #define WMM_AIFSN_CFG 0x0214
392 #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
393 #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
394 #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
395 #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
396 
397 /*
398  * WMM_CWMIN_CSR: CWmin for each EDCA AC
399  * CWMIN0: AC_VO
400  * CWMIN1: AC_VI
401  * CWMIN2: AC_BE
402  * CWMIN3: AC_BK
403  */
404 #define WMM_CWMIN_CFG 0x0218
405 #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
406 #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
407 #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
408 #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
409 
410 /*
411  * WMM_CWMAX_CSR: CWmax for each EDCA AC
412  * CWMAX0: AC_VO
413  * CWMAX1: AC_VI
414  * CWMAX2: AC_BE
415  * CWMAX3: AC_BK
416  */
417 #define WMM_CWMAX_CFG 0x021c
418 #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
419 #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
420 #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
421 #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
422 
423 /*
424  * AC_TXOP0: AC_VO/AC_VI TXOP register
425  * AC0TXOP: AC_VO in unit of 32us
426  * AC1TXOP: AC_VI in unit of 32us
427  */
428 #define WMM_TXOP0_CFG 0x0220
429 #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
430 #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
431 
432 /*
433  * AC_TXOP1: AC_BE/AC_BK TXOP register
434  * AC2TXOP: AC_BE in unit of 32us
435  * AC3TXOP: AC_BK in unit of 32us
436  */
437 #define WMM_TXOP1_CFG 0x0224
438 #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
439 #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
440 
441 /*
442  * GPIO_CTRL:
443  * GPIO_CTRL_VALx: GPIO value
444  * GPIO_CTRL_DIRx: GPIO direction: 0 = output; 1 = input
445  */
446 #define GPIO_CTRL 0x0228
447 #define GPIO_CTRL_VAL0 FIELD32(0x00000001)
448 #define GPIO_CTRL_VAL1 FIELD32(0x00000002)
449 #define GPIO_CTRL_VAL2 FIELD32(0x00000004)
450 #define GPIO_CTRL_VAL3 FIELD32(0x00000008)
451 #define GPIO_CTRL_VAL4 FIELD32(0x00000010)
452 #define GPIO_CTRL_VAL5 FIELD32(0x00000020)
453 #define GPIO_CTRL_VAL6 FIELD32(0x00000040)
454 #define GPIO_CTRL_VAL7 FIELD32(0x00000080)
455 #define GPIO_CTRL_DIR0 FIELD32(0x00000100)
456 #define GPIO_CTRL_DIR1 FIELD32(0x00000200)
457 #define GPIO_CTRL_DIR2 FIELD32(0x00000400)
458 #define GPIO_CTRL_DIR3 FIELD32(0x00000800)
459 #define GPIO_CTRL_DIR4 FIELD32(0x00001000)
460 #define GPIO_CTRL_DIR5 FIELD32(0x00002000)
461 #define GPIO_CTRL_DIR6 FIELD32(0x00004000)
462 #define GPIO_CTRL_DIR7 FIELD32(0x00008000)
463 #define GPIO_CTRL_VAL8 FIELD32(0x00010000)
464 #define GPIO_CTRL_VAL9 FIELD32(0x00020000)
465 #define GPIO_CTRL_VAL10 FIELD32(0x00040000)
466 #define GPIO_CTRL_DIR8 FIELD32(0x01000000)
467 #define GPIO_CTRL_DIR9 FIELD32(0x02000000)
468 #define GPIO_CTRL_DIR10 FIELD32(0x04000000)
469 
470 /*
471  * MCU_CMD_CFG
472  */
473 #define MCU_CMD_CFG 0x022c
474 
475 /*
476  * AC_VO register offsets
477  */
478 #define TX_BASE_PTR0 0x0230
479 #define TX_MAX_CNT0 0x0234
480 #define TX_CTX_IDX0 0x0238
481 #define TX_DTX_IDX0 0x023c
482 
483 /*
484  * AC_VI register offsets
485  */
486 #define TX_BASE_PTR1 0x0240
487 #define TX_MAX_CNT1 0x0244
488 #define TX_CTX_IDX1 0x0248
489 #define TX_DTX_IDX1 0x024c
490 
491 /*
492  * AC_BE register offsets
493  */
494 #define TX_BASE_PTR2 0x0250
495 #define TX_MAX_CNT2 0x0254
496 #define TX_CTX_IDX2 0x0258
497 #define TX_DTX_IDX2 0x025c
498 
499 /*
500  * AC_BK register offsets
501  */
502 #define TX_BASE_PTR3 0x0260
503 #define TX_MAX_CNT3 0x0264
504 #define TX_CTX_IDX3 0x0268
505 #define TX_DTX_IDX3 0x026c
506 
507 /*
508  * HCCA register offsets
509  */
510 #define TX_BASE_PTR4 0x0270
511 #define TX_MAX_CNT4 0x0274
512 #define TX_CTX_IDX4 0x0278
513 #define TX_DTX_IDX4 0x027c
514 
515 /*
516  * MGMT register offsets
517  */
518 #define TX_BASE_PTR5 0x0280
519 #define TX_MAX_CNT5 0x0284
520 #define TX_CTX_IDX5 0x0288
521 #define TX_DTX_IDX5 0x028c
522 
523 /*
524  * RX register offsets
525  */
526 #define RX_BASE_PTR 0x0290
527 #define RX_MAX_CNT 0x0294
528 #define RX_CRX_IDX 0x0298
529 #define RX_DRX_IDX 0x029c
530 
531 /*
532  * USB_DMA_CFG
533  * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
534  * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
535  * PHY_CLEAR: phy watch dog enable.
536  * TX_CLEAR: Clear USB DMA TX path.
537  * TXOP_HALT: Halt TXOP count down when TX buffer is full.
538  * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
539  * RX_BULK_EN: Enable USB DMA Rx.
540  * TX_BULK_EN: Enable USB DMA Tx.
541  * EP_OUT_VALID: OUT endpoint data valid.
542  * RX_BUSY: USB DMA RX FSM busy.
543  * TX_BUSY: USB DMA TX FSM busy.
544  */
545 #define USB_DMA_CFG 0x02a0
546 #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
547 #define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
548 #define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
549 #define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
550 #define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
551 #define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
552 #define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
553 #define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
554 #define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
555 #define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
556 #define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
557 
558 /*
559  * US_CYC_CNT
560  * BT_MODE_EN: Bluetooth mode enable
561  * CLOCK CYCLE: Clock cycle count in 1us.
562  * PCI:0x21, PCIE:0x7d, USB:0x1e
563  */
564 #define US_CYC_CNT 0x02a4
565 #define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100)
566 #define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
567 
568 /*
569  * PBF_SYS_CTRL
570  * HOST_RAM_WRITE: enable Host program ram write selection
571  */
572 #define PBF_SYS_CTRL 0x0400
573 #define PBF_SYS_CTRL_READY FIELD32(0x00000080)
574 #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
575 
576 /*
577  * HOST-MCU shared memory
578  */
579 #define HOST_CMD_CSR 0x0404
580 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
581 
582 /*
583  * PBF registers
584  * Most are for debug. Driver doesn't touch PBF register.
585  */
586 #define PBF_CFG 0x0408
587 #define PBF_MAX_PCNT 0x040c
588 #define PBF_CTRL 0x0410
589 #define PBF_INT_STA 0x0414
590 #define PBF_INT_ENA 0x0418
591 
592 /*
593  * BCN_OFFSET0:
594  */
595 #define BCN_OFFSET0 0x042c
596 #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
597 #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
598 #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
599 #define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
600 
601 /*
602  * BCN_OFFSET1:
603  */
604 #define BCN_OFFSET1 0x0430
605 #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
606 #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
607 #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
608 #define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
609 
610 /*
611  * TXRXQ_PCNT: PBF register
612  * PCNT_TX0Q: Page count for TX hardware queue 0
613  * PCNT_TX1Q: Page count for TX hardware queue 1
614  * PCNT_TX2Q: Page count for TX hardware queue 2
615  * PCNT_RX0Q: Page count for RX hardware queue
616  */
617 #define TXRXQ_PCNT 0x0438
618 #define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff)
619 #define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00)
620 #define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000)
621 #define TXRXQ_PCNT_RX0Q FIELD32(0xff000000)
622 
623 /*
624  * PBF register
625  * Debug. Driver doesn't touch PBF register.
626  */
627 #define PBF_DBG 0x043c
628 
629 /*
630  * RF registers
631  */
632 #define RF_CSR_CFG 0x0500
633 #define RF_CSR_CFG_DATA FIELD32(0x000000ff)
634 #define RF_CSR_CFG_REGNUM FIELD32(0x00003f00)
635 #define RF_CSR_CFG_WRITE FIELD32(0x00010000)
636 #define RF_CSR_CFG_BUSY FIELD32(0x00020000)
637 
638 /*
639  * EFUSE_CSR: RT30x0 EEPROM
640  */
641 #define EFUSE_CTRL 0x0580
642 #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
643 #define EFUSE_CTRL_MODE FIELD32(0x000000c0)
644 #define EFUSE_CTRL_KICK FIELD32(0x40000000)
645 #define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
646 
647 /*
648  * EFUSE_DATA0
649  */
650 #define EFUSE_DATA0 0x0590
651 
652 /*
653  * EFUSE_DATA1
654  */
655 #define EFUSE_DATA1 0x0594
656 
657 /*
658  * EFUSE_DATA2
659  */
660 #define EFUSE_DATA2 0x0598
661 
662 /*
663  * EFUSE_DATA3
664  */
665 #define EFUSE_DATA3 0x059c
666 
667 /*
668  * LDO_CFG0
669  */
670 #define LDO_CFG0 0x05d4
671 #define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
672 #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
673 #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
674 #define LDO_CFG0_BGSEL FIELD32(0x03000000)
675 #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
676 #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
677 #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
678 
679 /*
680  * GPIO_SWITCH
681  */
682 #define GPIO_SWITCH 0x05dc
683 #define GPIO_SWITCH_0 FIELD32(0x00000001)
684 #define GPIO_SWITCH_1 FIELD32(0x00000002)
685 #define GPIO_SWITCH_2 FIELD32(0x00000004)
686 #define GPIO_SWITCH_3 FIELD32(0x00000008)
687 #define GPIO_SWITCH_4 FIELD32(0x00000010)
688 #define GPIO_SWITCH_5 FIELD32(0x00000020)
689 #define GPIO_SWITCH_6 FIELD32(0x00000040)
690 #define GPIO_SWITCH_7 FIELD32(0x00000080)
691 
692 /*
693  * MAC Control/Status Registers(CSR).
694  * Some values are set in TU, whereas 1 TU == 1024 us.
695  */
696 
697 /*
698  * MAC_CSR0: ASIC revision number.
699  * ASIC_REV: 0
700  * ASIC_VER: 2860 or 2870
701  */
702 #define MAC_CSR0 0x1000
703 #define MAC_CSR0_REVISION FIELD32(0x0000ffff)
704 #define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
705 
706 /*
707  * MAC_SYS_CTRL:
708  */
709 #define MAC_SYS_CTRL 0x1004
710 #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
711 #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
712 #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
713 #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
714 #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
715 #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
716 #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
717 #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
718 
719 /*
720  * MAC_ADDR_DW0: STA MAC register 0
721  */
722 #define MAC_ADDR_DW0 0x1008
723 #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
724 #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
725 #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
726 #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
727 
728 /*
729  * MAC_ADDR_DW1: STA MAC register 1
730  * UNICAST_TO_ME_MASK:
731  * Used to mask off bits from byte 5 of the MAC address
732  * to determine the UNICAST_TO_ME bit for RX frames.
733  * The full mask is complemented by BSS_ID_MASK:
734  * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
735  */
736 #define MAC_ADDR_DW1 0x100c
737 #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
738 #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
739 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
740 
741 /*
742  * MAC_BSSID_DW0: BSSID register 0
743  */
744 #define MAC_BSSID_DW0 0x1010
745 #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
746 #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
747 #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
748 #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
749 
750 /*
751  * MAC_BSSID_DW1: BSSID register 1
752  * BSS_ID_MASK:
753  * 0: 1-BSSID mode (BSS index = 0)
754  * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
755  * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
756  * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
757  * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
758  * BSSID. This will make sure that those bits will be ignored
759  * when determining the MY_BSS of RX frames.
760  */
761 #define MAC_BSSID_DW1 0x1014
762 #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
763 #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
764 #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
765 #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
766 
767 /*
768  * MAX_LEN_CFG: Maximum frame length register.
769  * MAX_MPDU: rt2860b max 16k bytes
770  * MAX_PSDU: Maximum PSDU length
771  * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
772  */
773 #define MAX_LEN_CFG 0x1018
774 #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
775 #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
776 #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
777 #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
778 
779 /*
780  * BBP_CSR_CFG: BBP serial control register
781  * VALUE: Register value to program into BBP
782  * REG_NUM: Selected BBP register
783  * READ_CONTROL: 0 write BBP, 1 read BBP
784  * BUSY: ASIC is busy executing BBP commands
785  * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
786  * BBP_RW_MODE: 0 serial, 1 parallel
787  */
788 #define BBP_CSR_CFG 0x101c
789 #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
790 #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
791 #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
792 #define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
793 #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
794 #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
795 
796 /*
797  * RF_CSR_CFG0: RF control register
798  * REGID_AND_VALUE: Register value to program into RF
799  * BITWIDTH: Selected RF register
800  * STANDBYMODE: 0 high when standby, 1 low when standby
801  * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
802  * BUSY: ASIC is busy executing RF commands
803  */
804 #define RF_CSR_CFG0 0x1020
805 #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
806 #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
807 #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
808 #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
809 #define RF_CSR_CFG0_SEL FIELD32(0x40000000)
810 #define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
811 
812 /*
813  * RF_CSR_CFG1: RF control register
814  * REGID_AND_VALUE: Register value to program into RF
815  * RFGAP: Gap between BB_CONTROL_RF and RF_LE
816  * 0: 3 system clock cycle (37.5usec)
817  * 1: 5 system clock cycle (62.5usec)
818  */
819 #define RF_CSR_CFG1 0x1024
820 #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
821 #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
822 
823 /*
824  * RF_CSR_CFG2: RF control register
825  * VALUE: Register value to program into RF
826  */
827 #define RF_CSR_CFG2 0x1028
828 #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
829 
830 /*
831  * LED_CFG: LED control
832  * ON_PERIOD: LED active time (ms) during TX (only used for LED mode 1)
833  * OFF_PERIOD: LED inactive time (ms) during TX (only used for LED mode 1)
834  * SLOW_BLINK_PERIOD: LED blink interval in seconds (only used for LED mode 2)
835  * color LED's:
836  * 0: off
837  * 1: blinking upon TX2
838  * 2: periodic slow blinking
839  * 3: always on
840  * LED polarity:
841  * 0: active low
842  * 1: active high
843  */
844 #define LED_CFG 0x102c
845 #define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
846 #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
847 #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
848 #define LED_CFG_R_LED_MODE FIELD32(0x03000000)
849 #define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
850 #define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
851 #define LED_CFG_LED_POLAR FIELD32(0x40000000)
852 
853 /*
854  * AMPDU_BA_WINSIZE: Force BlockAck window size
855  * FORCE_WINSIZE_ENABLE:
856  * 0: Disable forcing of BlockAck window size
857  * 1: Enable forcing of BlockAck window size, overwrites values BlockAck
858  * window size values in the TXWI
859  * FORCE_WINSIZE: BlockAck window size
860  */
861 #define AMPDU_BA_WINSIZE 0x1040
862 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
863 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f)
864 
865 /*
866  * XIFS_TIME_CFG: MAC timing
867  * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
868  * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
869  * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
870  * when MAC doesn't reference BBP signal BBRXEND
871  * EIFS: unit 1us
872  * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
873  *
874  */
875 #define XIFS_TIME_CFG 0x1100
876 #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
877 #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
878 #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
879 #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
880 #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
881 
882 /*
883  * BKOFF_SLOT_CFG:
884  */
885 #define BKOFF_SLOT_CFG 0x1104
886 #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
887 #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
888 
889 /*
890  * NAV_TIME_CFG:
891  */
892 #define NAV_TIME_CFG 0x1108
893 #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
894 #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
895 #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
896 #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
897 
898 /*
899  * CH_TIME_CFG: count as channel busy
900  * EIFS_BUSY: Count EIFS as channel busy
901  * NAV_BUSY: Count NAS as channel busy
902  * RX_BUSY: Count RX as channel busy
903  * TX_BUSY: Count TX as channel busy
904  * TMR_EN: Enable channel statistics timer
905  */
906 #define CH_TIME_CFG 0x110c
907 #define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010)
908 #define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008)
909 #define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004)
910 #define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002)
911 #define CH_TIME_CFG_TMR_EN FIELD32(0x00000001)
912 
913 /*
914  * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
915  */
916 #define PBF_LIFE_TIMER 0x1110
917 
918 /*
919  * BCN_TIME_CFG:
920  * BEACON_INTERVAL: in unit of 1/16 TU
921  * TSF_TICKING: Enable TSF auto counting
922  * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
923  * BEACON_GEN: Enable beacon generator
924  */
925 #define BCN_TIME_CFG 0x1114
926 #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
927 #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
928 #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
929 #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
930 #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
931 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
932 
933 /*
934  * TBTT_SYNC_CFG:
935  * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots
936  * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots
937  */
938 #define TBTT_SYNC_CFG 0x1118
939 #define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff)
940 #define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00)
941 #define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000)
942 #define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000)
943 
944 /*
945  * TSF_TIMER_DW0: Local lsb TSF timer, read-only
946  */
947 #define TSF_TIMER_DW0 0x111c
948 #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
949 
950 /*
951  * TSF_TIMER_DW1: Local msb TSF timer, read-only
952  */
953 #define TSF_TIMER_DW1 0x1120
954 #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
955 
956 /*
957  * TBTT_TIMER: TImer remains till next TBTT, read-only
958  */
959 #define TBTT_TIMER 0x1124
960 
961 /*
962  * INT_TIMER_CFG: timer configuration
963  * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU
964  * GP_TIMER: period of general purpose timer in units of 1/16 TU
965  */
966 #define INT_TIMER_CFG 0x1128
967 #define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff)
968 #define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000)
969 
970 /*
971  * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
972  */
973 #define INT_TIMER_EN 0x112c
974 #define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001)
975 #define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002)
976 
977 /*
978  * CH_IDLE_STA: channel idle time (in us)
979  */
980 #define CH_IDLE_STA 0x1130
981 
982 /*
983  * CH_BUSY_STA: channel busy time on primary channel (in us)
984  */
985 #define CH_BUSY_STA 0x1134
986 
987 /*
988  * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us)
989  */
990 #define CH_BUSY_STA_SEC 0x1138
991 
992 /*
993  * MAC_STATUS_CFG:
994  * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
995  * if 1 or higher one of the 2 registers is busy.
996  */
997 #define MAC_STATUS_CFG 0x1200
998 #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
999 
1000 /*
1001  * PWR_PIN_CFG:
1002  */
1003 #define PWR_PIN_CFG 0x1204
1004 
1005 /*
1006  * AUTOWAKEUP_CFG: Manual power control / status register
1007  * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
1008  * AUTOWAKE: 0:sleep, 1:awake
1009  */
1010 #define AUTOWAKEUP_CFG 0x1208
1011 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
1012 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
1013 #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
1014 
1015 /*
1016  * EDCA_AC0_CFG:
1017  */
1018 #define EDCA_AC0_CFG 0x1300
1019 #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
1020 #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
1021 #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
1022 #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
1023 
1024 /*
1025  * EDCA_AC1_CFG:
1026  */
1027 #define EDCA_AC1_CFG 0x1304
1028 #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
1029 #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
1030 #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
1031 #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
1032 
1033 /*
1034  * EDCA_AC2_CFG:
1035  */
1036 #define EDCA_AC2_CFG 0x1308
1037 #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
1038 #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
1039 #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
1040 #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
1041 
1042 /*
1043  * EDCA_AC3_CFG:
1044  */
1045 #define EDCA_AC3_CFG 0x130c
1046 #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
1047 #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
1048 #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
1049 #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
1050 
1051 /*
1052  * EDCA_TID_AC_MAP:
1053  */
1054 #define EDCA_TID_AC_MAP 0x1310
1055 
1056 /*
1057  * TX_PWR_CFG:
1058  */
1059 #define TX_PWR_CFG_RATE0 FIELD32(0x0000000f)
1060 #define TX_PWR_CFG_RATE1 FIELD32(0x000000f0)
1061 #define TX_PWR_CFG_RATE2 FIELD32(0x00000f00)
1062 #define TX_PWR_CFG_RATE3 FIELD32(0x0000f000)
1063 #define TX_PWR_CFG_RATE4 FIELD32(0x000f0000)
1064 #define TX_PWR_CFG_RATE5 FIELD32(0x00f00000)
1065 #define TX_PWR_CFG_RATE6 FIELD32(0x0f000000)
1066 #define TX_PWR_CFG_RATE7 FIELD32(0xf0000000)
1067 
1068 /*
1069  * TX_PWR_CFG_0:
1070  */
1071 #define TX_PWR_CFG_0 0x1314
1072 #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
1073 #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
1074 #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
1075 #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
1076 #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
1077 #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
1078 #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
1079 #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
1080 
1081 /*
1082  * TX_PWR_CFG_1:
1083  */
1084 #define TX_PWR_CFG_1 0x1318
1085 #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
1086 #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
1087 #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
1088 #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
1089 #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
1090 #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
1091 #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
1092 #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
1093 
1094 /*
1095  * TX_PWR_CFG_2:
1096  */
1097 #define TX_PWR_CFG_2 0x131c
1098 #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
1099 #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
1100 #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
1101 #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
1102 #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
1103 #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
1104 #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
1105 #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
1106 
1107 /*
1108  * TX_PWR_CFG_3:
1109  */
1110 #define TX_PWR_CFG_3 0x1320
1111 #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
1112 #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
1113 #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
1114 #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
1115 #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
1116 #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
1117 #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
1118 #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
1119 
1120 /*
1121  * TX_PWR_CFG_4:
1122  */
1123 #define TX_PWR_CFG_4 0x1324
1124 #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
1125 #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
1126 #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
1127 #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
1128 
1129 /*
1130  * TX_PIN_CFG:
1131  */
1132 #define TX_PIN_CFG 0x1328
1133 #define TX_PIN_CFG_PA_PE_DISABLE 0xfcfffff0
1134 #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
1135 #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
1136 #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
1137 #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
1138 #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
1139 #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
1140 #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
1141 #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
1142 #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
1143 #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
1144 #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
1145 #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
1146 #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
1147 #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
1148 #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
1149 #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
1150 #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
1151 #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
1152 #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
1153 #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
1154 #define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000)
1155 #define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000)
1156 #define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000)
1157 #define TX_PIN_CFG_PA_PE_G2_POL FIELD32(0x08000000)
1158 #define TX_PIN_CFG_LNA_PE_A2_EN FIELD32(0x10000000)
1159 #define TX_PIN_CFG_LNA_PE_G2_EN FIELD32(0x20000000)
1160 #define TX_PIN_CFG_LNA_PE_A2_POL FIELD32(0x40000000)
1161 #define TX_PIN_CFG_LNA_PE_G2_POL FIELD32(0x80000000)
1162 
1163 /*
1164  * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
1165  */
1166 #define TX_BAND_CFG 0x132c
1167 #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
1168 #define TX_BAND_CFG_A FIELD32(0x00000002)
1169 #define TX_BAND_CFG_BG FIELD32(0x00000004)
1170 
1171 /*
1172  * TX_SW_CFG0:
1173  */
1174 #define TX_SW_CFG0 0x1330
1175 
1176 /*
1177  * TX_SW_CFG1:
1178  */
1179 #define TX_SW_CFG1 0x1334
1180 
1181 /*
1182  * TX_SW_CFG2:
1183  */
1184 #define TX_SW_CFG2 0x1338
1185 
1186 /*
1187  * TXOP_THRES_CFG:
1188  */
1189 #define TXOP_THRES_CFG 0x133c
1190 
1191 /*
1192  * TXOP_CTRL_CFG:
1193  * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation
1194  * AC_TRUN_EN: Enable/Disable truncation for AC change
1195  * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change
1196  * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode
1197  * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS
1198  * RESERVED_TRUN_EN: Reserved
1199  * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection
1200  * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz
1201  * transmissions if extension CCA is clear).
1202  * EXT_CCA_DLY: Extension CCA signal delay time (unit: us)
1203  * EXT_CWMIN: CwMin for extension channel backoff
1204  * 0: Disabled
1205  *
1206  */
1207 #define TXOP_CTRL_CFG 0x1340
1208 #define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001)
1209 #define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002)
1210 #define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
1211 #define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
1212 #define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010)
1213 #define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020)
1214 #define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040)
1215 #define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080)
1216 #define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00)
1217 #define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000)
1218 
1219 /*
1220  * TX_RTS_CFG:
1221  * RTS_THRES: unit:byte
1222  * RTS_FBK_EN: enable rts rate fallback
1223  */
1224 #define TX_RTS_CFG 0x1344
1225 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
1226 #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
1227 #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
1228 
1229 /*
1230  * TX_TIMEOUT_CFG:
1231  * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
1232  * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
1233  * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
1234  * it is recommended that:
1235  * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
1236  */
1237 #define TX_TIMEOUT_CFG 0x1348
1238 #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
1239 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
1240 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
1241 
1242 /*
1243  * TX_RTY_CFG:
1244  * SHORT_RTY_LIMIT: short retry limit
1245  * LONG_RTY_LIMIT: long retry limit
1246  * LONG_RTY_THRE: Long retry threshoold
1247  * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
1248  * 0:expired by retry limit, 1: expired by mpdu life timer
1249  * AGG_RTY_MODE: Aggregate MPDU retry mode
1250  * 0:expired by retry limit, 1: expired by mpdu life timer
1251  * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
1252  */
1253 #define TX_RTY_CFG 0x134c
1254 #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
1255 #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
1256 #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
1257 #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
1258 #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
1259 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
1260 
1261 /*
1262  * TX_LINK_CFG:
1263  * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
1264  * MFB_ENABLE: TX apply remote MFB 1:enable
1265  * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
1266  * 0: not apply remote remote unsolicit (MFS=7)
1267  * TX_MRQ_EN: MCS request TX enable
1268  * TX_RDG_EN: RDG TX enable
1269  * TX_CF_ACK_EN: Piggyback CF-ACK enable
1270  * REMOTE_MFB: remote MCS feedback
1271  * REMOTE_MFS: remote MCS feedback sequence number
1272  */
1273 #define TX_LINK_CFG 0x1350
1274 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
1275 #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
1276 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
1277 #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
1278 #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
1279 #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
1280 #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
1281 #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
1282 
1283 /*
1284  * HT_FBK_CFG0:
1285  */
1286 #define HT_FBK_CFG0 0x1354
1287 #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
1288 #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
1289 #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
1290 #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
1291 #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
1292 #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
1293 #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
1294 #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
1295 
1296 /*
1297  * HT_FBK_CFG1:
1298  */
1299 #define HT_FBK_CFG1 0x1358
1300 #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
1301 #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
1302 #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
1303 #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
1304 #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
1305 #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
1306 #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
1307 #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
1308 
1309 /*
1310  * LG_FBK_CFG0:
1311  */
1312 #define LG_FBK_CFG0 0x135c
1313 #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
1314 #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
1315 #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
1316 #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
1317 #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
1318 #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
1319 #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
1320 #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
1321 
1322 /*
1323  * LG_FBK_CFG1:
1324  */
1325 #define LG_FBK_CFG1 0x1360
1326 #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
1327 #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
1328 #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
1329 #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
1330 
1331 /*
1332  * CCK_PROT_CFG: CCK Protection
1333  * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
1334  * PROTECT_CTRL: Protection control frame type for CCK TX
1335  * 0:none, 1:RTS/CTS, 2:CTS-to-self
1336  * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV
1337  * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV
1338  * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
1339  * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
1340  * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
1341  * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
1342  * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
1343  * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
1344  * RTS_TH_EN: RTS threshold enable on CCK TX
1345  */
1346 #define CCK_PROT_CFG 0x1364
1347 #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1348 #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1349 #define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1350 #define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1351 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1352 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1353 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1354 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1355 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1356 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1357 #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1358 
1359 /*
1360  * OFDM_PROT_CFG: OFDM Protection
1361  */
1362 #define OFDM_PROT_CFG 0x1368
1363 #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1364 #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1365 #define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1366 #define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1367 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1368 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1369 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1370 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1371 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1372 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1373 #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1374 
1375 /*
1376  * MM20_PROT_CFG: MM20 Protection
1377  */
1378 #define MM20_PROT_CFG 0x136c
1379 #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1380 #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1381 #define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1382 #define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1383 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1384 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1385 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1386 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1387 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1388 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1389 #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1390 
1391 /*
1392  * MM40_PROT_CFG: MM40 Protection
1393  */
1394 #define MM40_PROT_CFG 0x1370
1395 #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1396 #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1397 #define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1398 #define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1399 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1400 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1401 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1402 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1403 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1404 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1405 #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1406 
1407 /*
1408  * GF20_PROT_CFG: GF20 Protection
1409  */
1410 #define GF20_PROT_CFG 0x1374
1411 #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1412 #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1413 #define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1414 #define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1415 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1416 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1417 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1418 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1419 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1420 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1421 #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1422 
1423 /*
1424  * GF40_PROT_CFG: GF40 Protection
1425  */
1426 #define GF40_PROT_CFG 0x1378
1427 #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1428 #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1429 #define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1430 #define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1431 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1432 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1433 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1434 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1435 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1436 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1437 #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1438 
1439 /*
1440  * EXP_CTS_TIME:
1441  */
1442 #define EXP_CTS_TIME 0x137c
1443 
1444 /*
1445  * EXP_ACK_TIME:
1446  */
1447 #define EXP_ACK_TIME 0x1380
1448 
1449 /*
1450  * RX_FILTER_CFG: RX configuration register.
1451  */
1452 #define RX_FILTER_CFG 0x1400
1453 #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1454 #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1455 #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1456 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1457 #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1458 #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1459 #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1460 #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1461 #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1462 #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1463 #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1464 #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1465 #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1466 #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1467 #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1468 #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1469 #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1470 
1471 /*
1472  * AUTO_RSP_CFG:
1473  * AUTORESPONDER: 0: disable, 1: enable
1474  * BAC_ACK_POLICY: 0:long, 1:short preamble
1475  * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1476  * CTS_40_MREF: Response CTS 40MHz duplicate mode
1477  * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1478  * DUAL_CTS_EN: Power bit value in control frame
1479  * ACK_CTS_PSM_BIT:Power bit value in control frame
1480  */
1481 #define AUTO_RSP_CFG 0x1404
1482 #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1483 #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1484 #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1485 #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1486 #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1487 #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1488 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1489 
1490 /*
1491  * LEGACY_BASIC_RATE:
1492  */
1493 #define LEGACY_BASIC_RATE 0x1408
1494 
1495 /*
1496  * HT_BASIC_RATE:
1497  */
1498 #define HT_BASIC_RATE 0x140c
1499 
1500 /*
1501  * HT_CTRL_CFG:
1502  */
1503 #define HT_CTRL_CFG 0x1410
1504 
1505 /*
1506  * SIFS_COST_CFG:
1507  */
1508 #define SIFS_COST_CFG 0x1414
1509 
1510 /*
1511  * RX_PARSER_CFG:
1512  * Set NAV for all received frames
1513  */
1514 #define RX_PARSER_CFG 0x1418
1515 
1516 /*
1517  * TX_SEC_CNT0:
1518  */
1519 #define TX_SEC_CNT0 0x1500
1520 
1521 /*
1522  * RX_SEC_CNT0:
1523  */
1524 #define RX_SEC_CNT0 0x1504
1525 
1526 /*
1527  * CCMP_FC_MUTE:
1528  */
1529 #define CCMP_FC_MUTE 0x1508
1530 
1531 /*
1532  * TXOP_HLDR_ADDR0:
1533  */
1534 #define TXOP_HLDR_ADDR0 0x1600
1535 
1536 /*
1537  * TXOP_HLDR_ADDR1:
1538  */
1539 #define TXOP_HLDR_ADDR1 0x1604
1540 
1541 /*
1542  * TXOP_HLDR_ET:
1543  */
1544 #define TXOP_HLDR_ET 0x1608
1545 
1546 /*
1547  * QOS_CFPOLL_RA_DW0:
1548  */
1549 #define QOS_CFPOLL_RA_DW0 0x160c
1550 
1551 /*
1552  * QOS_CFPOLL_RA_DW1:
1553  */
1554 #define QOS_CFPOLL_RA_DW1 0x1610
1555 
1556 /*
1557  * QOS_CFPOLL_QC:
1558  */
1559 #define QOS_CFPOLL_QC 0x1614
1560 
1561 /*
1562  * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1563  */
1564 #define RX_STA_CNT0 0x1700
1565 #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1566 #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1567 
1568 /*
1569  * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1570  */
1571 #define RX_STA_CNT1 0x1704
1572 #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1573 #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1574 
1575 /*
1576  * RX_STA_CNT2:
1577  */
1578 #define RX_STA_CNT2 0x1708
1579 #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1580 #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1581 
1582 /*
1583  * TX_STA_CNT0: TX Beacon count
1584  */
1585 #define TX_STA_CNT0 0x170c
1586 #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1587 #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1588 
1589 /*
1590  * TX_STA_CNT1: TX tx count
1591  */
1592 #define TX_STA_CNT1 0x1710
1593 #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1594 #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1595 
1596 /*
1597  * TX_STA_CNT2: TX tx count
1598  */
1599 #define TX_STA_CNT2 0x1714
1600 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1601 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1602 
1603 /*
1604  * TX_STA_FIFO: TX Result for specific PID status fifo register.
1605  *
1606  * This register is implemented as FIFO with 16 entries in the HW. Each
1607  * register read fetches the next tx result. If the FIFO is full because
1608  * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS)
1609  * triggered, the hw seems to simply drop further tx results.
1610  *
1611  * VALID: 1: this tx result is valid
1612  * 0: no valid tx result -> driver should stop reading
1613  * PID_TYPE: The PID latched from the PID field in the TXWI, can be used
1614  * to match a frame with its tx result (even though the PID is
1615  * only 4 bits wide).
1616  * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3)
1617  * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3)
1618  * This identification number is calculated by ((idx % 3) + 1).
1619  * TX_SUCCESS: Indicates tx success (1) or failure (0)
1620  * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0)
1621  * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0)
1622  * WCID: The wireless client ID.
1623  * MCS: The tx rate used during the last transmission of this frame, be it
1624  * successful or not.
1625  * PHYMODE: The phymode used for the transmission.
1626  */
1627 #define TX_STA_FIFO 0x1718
1628 #define TX_STA_FIFO_VALID FIELD32(0x00000001)
1629 #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1630 #define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006)
1631 #define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018)
1632 #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1633 #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1634 #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1635 #define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1636 #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1637 #define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1638 #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1639 
1640 /*
1641  * TX_AGG_CNT: Debug counter
1642  */
1643 #define TX_AGG_CNT 0x171c
1644 #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1645 #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1646 
1647 /*
1648  * TX_AGG_CNT0:
1649  */
1650 #define TX_AGG_CNT0 0x1720
1651 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1652 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1653 
1654 /*
1655  * TX_AGG_CNT1:
1656  */
1657 #define TX_AGG_CNT1 0x1724
1658 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1659 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1660 
1661 /*
1662  * TX_AGG_CNT2:
1663  */
1664 #define TX_AGG_CNT2 0x1728
1665 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1666 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1667 
1668 /*
1669  * TX_AGG_CNT3:
1670  */
1671 #define TX_AGG_CNT3 0x172c
1672 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1673 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1674 
1675 /*
1676  * TX_AGG_CNT4:
1677  */
1678 #define TX_AGG_CNT4 0x1730
1679 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1680 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1681 
1682 /*
1683  * TX_AGG_CNT5:
1684  */
1685 #define TX_AGG_CNT5 0x1734
1686 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1687 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1688 
1689 /*
1690  * TX_AGG_CNT6:
1691  */
1692 #define TX_AGG_CNT6 0x1738
1693 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1694 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1695 
1696 /*
1697  * TX_AGG_CNT7:
1698  */
1699 #define TX_AGG_CNT7 0x173c
1700 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1701 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1702 
1703 /*
1704  * MPDU_DENSITY_CNT:
1705  * TX_ZERO_DEL: TX zero length delimiter count
1706  * RX_ZERO_DEL: RX zero length delimiter count
1707  */
1708 #define MPDU_DENSITY_CNT 0x1740
1709 #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1710 #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1711 
1712 /*
1713  * Security key table memory.
1714  *
1715  * The pairwise key table shares some memory with the beacon frame
1716  * buffers 6 and 7. That basically means that when beacon 6 & 7
1717  * are used we should only use the reduced pairwise key table which
1718  * has a maximum of 222 entries.
1719  *
1720  * ---------------------------------------------
1721  * |0x4000 | Pairwise Key | Reduced Pairwise |
1722  * | | Table | Key Table |
1723  * | | Size: 256 * 32 | Size: 222 * 32 |
1724  * |0x5BC0 | |-------------------
1725  * | | | Beacon 6 |
1726  * |0x5DC0 | |-------------------
1727  * | | | Beacon 7 |
1728  * |0x5FC0 | |-------------------
1729  * |0x5FFF | |
1730  * --------------------------
1731  *
1732  * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1733  * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1734  * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1735  * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1736  * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1737  * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1738  */
1739 #define MAC_WCID_BASE 0x1800
1740 #define PAIRWISE_KEY_TABLE_BASE 0x4000
1741 #define MAC_IVEIV_TABLE_BASE 0x6000
1742 #define MAC_WCID_ATTRIBUTE_BASE 0x6800
1743 #define SHARED_KEY_TABLE_BASE 0x6c00
1744 #define SHARED_KEY_MODE_BASE 0x7000
1745 
1746 #define MAC_WCID_ENTRY(__idx) \
1747  (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)))
1748 #define PAIRWISE_KEY_ENTRY(__idx) \
1749  (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1750 #define MAC_IVEIV_ENTRY(__idx) \
1751  (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)))
1752 #define MAC_WCID_ATTR_ENTRY(__idx) \
1753  (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)))
1754 #define SHARED_KEY_ENTRY(__idx) \
1755  (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1756 #define SHARED_KEY_MODE_ENTRY(__idx) \
1757  (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)))
1758 
1759 struct mac_wcid_entry {
1760  u8 mac[6];
1761  u8 reserved[2];
1762 } __packed;
1763 
1764 struct hw_key_entry {
1765  u8 key[16];
1766  u8 tx_mic[8];
1767  u8 rx_mic[8];
1768 } __packed;
1769 
1770 struct mac_iveiv_entry {
1771  u8 iv[8];
1772 } __packed;
1773 
1774 /*
1775  * MAC_WCID_ATTRIBUTE:
1776  */
1777 #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1778 #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1779 #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1780 #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1781 #define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400)
1782 #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800)
1783 #define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000)
1784 #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
1785 
1786 /*
1787  * SHARED_KEY_MODE:
1788  */
1789 #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1790 #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1791 #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1792 #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1793 #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1794 #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1795 #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1796 #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1797 
1798 /*
1799  * HOST-MCU communication
1800  */
1801 
1802 /*
1803  * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1804  * CMD_TOKEN: Command id, 0xff disable status reporting.
1805  */
1806 #define H2M_MAILBOX_CSR 0x7010
1807 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1808 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1809 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1810 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1811 
1812 /*
1813  * H2M_MAILBOX_CID:
1814  * Free slots contain 0xff. MCU will store command's token to lowest free slot.
1815  * If all slots are occupied status will be dropped.
1816  */
1817 #define H2M_MAILBOX_CID 0x7014
1818 #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1819 #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1820 #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1821 #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1822 
1823 /*
1824  * H2M_MAILBOX_STATUS:
1825  * Command status will be saved to same slot as command id.
1826  */
1827 #define H2M_MAILBOX_STATUS 0x701c
1828 
1829 /*
1830  * H2M_INT_SRC:
1831  */
1832 #define H2M_INT_SRC 0x7024
1833 
1834 /*
1835  * H2M_BBP_AGENT:
1836  */
1837 #define H2M_BBP_AGENT 0x7028
1838 
1839 /*
1840  * MCU_LEDCS: LED control for MCU Mailbox.
1841  */
1842 #define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1843 #define MCU_LEDCS_POLARITY FIELD8(0x01)
1844 
1845 /*
1846  * HW_CS_CTS_BASE:
1847  * Carrier-sense CTS frame base address.
1848  * It's where mac stores carrier-sense frame for carrier-sense function.
1849  */
1850 #define HW_CS_CTS_BASE 0x7700
1851 
1852 /*
1853  * HW_DFS_CTS_BASE:
1854  * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1855  */
1856 #define HW_DFS_CTS_BASE 0x7780
1857 
1858 /*
1859  * TXRX control registers - base address 0x3000
1860  */
1861 
1862 /*
1863  * TXRX_CSR1:
1864  * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1865  */
1866 #define TXRX_CSR1 0x77d0
1867 
1868 /*
1869  * HW_DEBUG_SETTING_BASE:
1870  * since NULL frame won't be that long (256 byte)
1871  * We steal 16 tail bytes to save debugging settings
1872  */
1873 #define HW_DEBUG_SETTING_BASE 0x77f0
1874 #define HW_DEBUG_SETTING_BASE2 0x7770
1875 
1876 /*
1877  * HW_BEACON_BASE
1878  * In order to support maximum 8 MBSS and its maximum length
1879  * is 512 bytes for each beacon
1880  * Three section discontinue memory segments will be used.
1881  * 1. The original region for BCN 0~3
1882  * 2. Extract memory from FCE table for BCN 4~5
1883  * 3. Extract memory from Pair-wise key table for BCN 6~7
1884  * It occupied those memory of wcid 238~253 for BCN 6
1885  * and wcid 222~237 for BCN 7 (see Security key table memory
1886  * for more info).
1887  *
1888  * IMPORTANT NOTE: Not sure why legacy driver does this,
1889  * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1890  */
1891 #define HW_BEACON_BASE0 0x7800
1892 #define HW_BEACON_BASE1 0x7a00
1893 #define HW_BEACON_BASE2 0x7c00
1894 #define HW_BEACON_BASE3 0x7e00
1895 #define HW_BEACON_BASE4 0x7200
1896 #define HW_BEACON_BASE5 0x7400
1897 #define HW_BEACON_BASE6 0x5dc0
1898 #define HW_BEACON_BASE7 0x5bc0
1899 
1900 #define HW_BEACON_OFFSET(__index) \
1901  (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \
1902  (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
1903  (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
1904 
1905 /*
1906  * BBP registers.
1907  * The wordsize of the BBP is 8 bits.
1908  */
1909 
1910 /*
1911  * BBP 1: TX Antenna & Power Control
1912  * POWER_CTRL:
1913  * 0 - normal,
1914  * 1 - drop tx power by 6dBm,
1915  * 2 - drop tx power by 12dBm,
1916  * 3 - increase tx power by 6dBm
1917  */
1918 #define BBP1_TX_POWER_CTRL FIELD8(0x07)
1919 #define BBP1_TX_ANTENNA FIELD8(0x18)
1920 
1921 /*
1922  * BBP 3: RX Antenna
1923  */
1924 #define BBP3_RX_ADC FIELD8(0x03)
1925 #define BBP3_RX_ANTENNA FIELD8(0x18)
1926 #define BBP3_HT40_MINUS FIELD8(0x20)
1927 #define BBP3_ADC_MODE_SWITCH FIELD8(0x40)
1928 #define BBP3_ADC_INIT_MODE FIELD8(0x80)
1929 
1930 /*
1931  * BBP 4: Bandwidth
1932  */
1933 #define BBP4_TX_BF FIELD8(0x01)
1934 #define BBP4_BANDWIDTH FIELD8(0x18)
1935 #define BBP4_MAC_IF_CTRL FIELD8(0x40)
1936 
1937 /*
1938  * BBP 47: Bandwidth
1939  */
1940 #define BBP47_TSSI_REPORT_SEL FIELD8(0x03)
1941 #define BBP47_TSSI_UPDATE_REQ FIELD8(0x04)
1942 #define BBP47_TSSI_TSSI_MODE FIELD8(0x18)
1943 #define BBP47_TSSI_ADC6 FIELD8(0x80)
1944 
1945 /*
1946  * BBP 49
1947  */
1948 #define BBP49_UPDATE_FLAG FIELD8(0x01)
1949 
1950 /*
1951  * BBP 109
1952  */
1953 #define BBP109_TX0_POWER FIELD8(0x0f)
1954 #define BBP109_TX1_POWER FIELD8(0xf0)
1955 
1956 /*
1957  * BBP 138: Unknown
1958  */
1959 #define BBP138_RX_ADC1 FIELD8(0x02)
1960 #define BBP138_RX_ADC2 FIELD8(0x04)
1961 #define BBP138_TX_DAC1 FIELD8(0x20)
1962 #define BBP138_TX_DAC2 FIELD8(0x40)
1963 
1964 /*
1965  * BBP 152: Rx Ant
1966  */
1967 #define BBP152_RX_DEFAULT_ANT FIELD8(0x80)
1968 
1969 /*
1970  * RFCSR registers
1971  * The wordsize of the RFCSR is 8 bits.
1972  */
1973 
1974 /*
1975  * RFCSR 1:
1976  */
1977 #define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
1978 #define RFCSR1_PLL_PD FIELD8(0x02)
1979 #define RFCSR1_RX0_PD FIELD8(0x04)
1980 #define RFCSR1_TX0_PD FIELD8(0x08)
1981 #define RFCSR1_RX1_PD FIELD8(0x10)
1982 #define RFCSR1_TX1_PD FIELD8(0x20)
1983 #define RFCSR1_RX2_PD FIELD8(0x40)
1984 #define RFCSR1_TX2_PD FIELD8(0x80)
1985 
1986 /*
1987  * RFCSR 2:
1988  */
1989 #define RFCSR2_RESCAL_EN FIELD8(0x80)
1990 
1991 /*
1992  * RFCSR 3:
1993  */
1994 #define RFCSR3_K FIELD8(0x0f)
1995 /* Bits [7-4] for RF3320 (RT3370/RT3390), on other chipsets reserved */
1996 #define RFCSR3_PA1_BIAS_CCK FIELD8(0x70);
1997 #define RFCSR3_PA2_CASCODE_BIAS_CCKK FIELD8(0x80);
1998 
1999 /*
2000  * FRCSR 5:
2001  */
2002 #define RFCSR5_R1 FIELD8(0x0c)
2003 
2004 /*
2005  * RFCSR 6:
2006  */
2007 #define RFCSR6_R1 FIELD8(0x03)
2008 #define RFCSR6_R2 FIELD8(0x40)
2009 #define RFCSR6_TXDIV FIELD8(0x0c)
2010 
2011 /*
2012  * RFCSR 7:
2013  */
2014 #define RFCSR7_RF_TUNING FIELD8(0x01)
2015 #define RFCSR7_BIT1 FIELD8(0x02)
2016 #define RFCSR7_BIT2 FIELD8(0x04)
2017 #define RFCSR7_BIT3 FIELD8(0x08)
2018 #define RFCSR7_BIT4 FIELD8(0x10)
2019 #define RFCSR7_BIT5 FIELD8(0x20)
2020 #define RFCSR7_BITS67 FIELD8(0xc0)
2021 
2022 /*
2023  * RFCSR 11:
2024  */
2025 #define RFCSR11_R FIELD8(0x03)
2026 
2027 /*
2028  * RFCSR 12:
2029  */
2030 #define RFCSR12_TX_POWER FIELD8(0x1f)
2031 #define RFCSR12_DR0 FIELD8(0xe0)
2032 
2033 /*
2034  * RFCSR 13:
2035  */
2036 #define RFCSR13_TX_POWER FIELD8(0x1f)
2037 #define RFCSR13_DR0 FIELD8(0xe0)
2038 
2039 /*
2040  * RFCSR 15:
2041  */
2042 #define RFCSR15_TX_LO2_EN FIELD8(0x08)
2043 
2044 /*
2045  * RFCSR 16:
2046  */
2047 #define RFCSR16_TXMIXER_GAIN FIELD8(0x07)
2048 
2049 /*
2050  * RFCSR 17:
2051  */
2052 #define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
2053 #define RFCSR17_TX_LO1_EN FIELD8(0x08)
2054 #define RFCSR17_R FIELD8(0x20)
2055 #define RFCSR17_CODE FIELD8(0x7f)
2056 
2057 /*
2058  * RFCSR 20:
2059  */
2060 #define RFCSR20_RX_LO1_EN FIELD8(0x08)
2061 
2062 /*
2063  * RFCSR 21:
2064  */
2065 #define RFCSR21_RX_LO2_EN FIELD8(0x08)
2066 
2067 /*
2068  * RFCSR 22:
2069  */
2070 #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
2071 
2072 /*
2073  * RFCSR 23:
2074  */
2075 #define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
2076 
2077 /*
2078  * RFCSR 24:
2079  */
2080 #define RFCSR24_TX_AGC_FC FIELD8(0x1f)
2081 #define RFCSR24_TX_H20M FIELD8(0x20)
2082 #define RFCSR24_TX_CALIB FIELD8(0x7f)
2083 
2084 /*
2085  * RFCSR 27:
2086  */
2087 #define RFCSR27_R1 FIELD8(0x03)
2088 #define RFCSR27_R2 FIELD8(0x04)
2089 #define RFCSR27_R3 FIELD8(0x30)
2090 #define RFCSR27_R4 FIELD8(0x40)
2091 
2092 /*
2093  * RFCSR 29:
2094  */
2095 #define RFCSR29_ADC6_TEST FIELD8(0x01)
2096 #define RFCSR29_ADC6_INT_TEST FIELD8(0x02)
2097 #define RFCSR29_RSSI_RESET FIELD8(0x04)
2098 #define RFCSR29_RSSI_ON FIELD8(0x08)
2099 #define RFCSR29_RSSI_RIP_CTRL FIELD8(0x30)
2100 #define RFCSR29_RSSI_GAIN FIELD8(0xc0)
2101 
2102 /*
2103  * RFCSR 30:
2104  */
2105 #define RFCSR30_TX_H20M FIELD8(0x02)
2106 #define RFCSR30_RX_H20M FIELD8(0x04)
2107 #define RFCSR30_RX_VCM FIELD8(0x18)
2108 #define RFCSR30_RF_CALIBRATION FIELD8(0x80)
2109 
2110 /*
2111  * RFCSR 31:
2112  */
2113 #define RFCSR31_RX_AGC_FC FIELD8(0x1f)
2114 #define RFCSR31_RX_H20M FIELD8(0x20)
2115 #define RFCSR31_RX_CALIB FIELD8(0x7f)
2116 
2117 /*
2118  * RFCSR 38:
2119  */
2120 #define RFCSR38_RX_LO1_EN FIELD8(0x20)
2121 
2122 /*
2123  * RFCSR 39:
2124  */
2125 #define RFCSR39_RX_LO2_EN FIELD8(0x80)
2126 
2127 /*
2128  * RFCSR 49:
2129  */
2130 #define RFCSR49_TX FIELD8(0x3f)
2131 
2132 /*
2133  * RFCSR 50:
2134  */
2135 #define RFCSR50_TX FIELD8(0x3f)
2136 
2137 /*
2138  * RF registers
2139  */
2140 
2141 /*
2142  * RF 2
2143  */
2144 #define RF2_ANTENNA_RX2 FIELD32(0x00000040)
2145 #define RF2_ANTENNA_TX1 FIELD32(0x00004000)
2146 #define RF2_ANTENNA_RX1 FIELD32(0x00020000)
2147 
2148 /*
2149  * RF 3
2150  */
2151 #define RF3_TXPOWER_G FIELD32(0x00003e00)
2152 #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
2153 #define RF3_TXPOWER_A FIELD32(0x00003c00)
2154 
2155 /*
2156  * RF 4
2157  */
2158 #define RF4_TXPOWER_G FIELD32(0x000007c0)
2159 #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
2160 #define RF4_TXPOWER_A FIELD32(0x00000780)
2161 #define RF4_FREQ_OFFSET FIELD32(0x001f8000)
2162 #define RF4_HT40 FIELD32(0x00200000)
2163 
2164 /*
2165  * EEPROM content.
2166  * The wordsize of the EEPROM is 16 bits.
2167  */
2168 
2169 /*
2170  * Chip ID
2171  */
2172 #define EEPROM_CHIP_ID 0x0000
2173 
2174 /*
2175  * EEPROM Version
2176  */
2177 #define EEPROM_VERSION 0x0001
2178 #define EEPROM_VERSION_FAE FIELD16(0x00ff)
2179 #define EEPROM_VERSION_VERSION FIELD16(0xff00)
2180 
2181 /*
2182  * HW MAC address.
2183  */
2184 #define EEPROM_MAC_ADDR_0 0x0002
2185 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
2186 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
2187 #define EEPROM_MAC_ADDR_1 0x0003
2188 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
2189 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
2190 #define EEPROM_MAC_ADDR_2 0x0004
2191 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
2192 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
2193 
2194 /*
2195  * EEPROM NIC Configuration 0
2196  * RXPATH: 1: 1R, 2: 2R, 3: 3R
2197  * TXPATH: 1: 1T, 2: 2T, 3: 3T
2198  * RF_TYPE: RFIC type
2199  */
2200 #define EEPROM_NIC_CONF0 0x001a
2201 #define EEPROM_NIC_CONF0_RXPATH FIELD16(0x000f)
2202 #define EEPROM_NIC_CONF0_TXPATH FIELD16(0x00f0)
2203 #define EEPROM_NIC_CONF0_RF_TYPE FIELD16(0x0f00)
2204 
2205 /*
2206  * EEPROM NIC Configuration 1
2207  * HW_RADIO: 0: disable, 1: enable
2208  * EXTERNAL_TX_ALC: 0: disable, 1: enable
2209  * EXTERNAL_LNA_2G: 0: disable, 1: enable
2210  * EXTERNAL_LNA_5G: 0: disable, 1: enable
2211  * CARDBUS_ACCEL: 0: enable, 1: disable
2212  * BW40M_SB_2G: 0: disable, 1: enable
2213  * BW40M_SB_5G: 0: disable, 1: enable
2214  * WPS_PBC: 0: disable, 1: enable
2215  * BW40M_2G: 0: enable, 1: disable
2216  * BW40M_5G: 0: enable, 1: disable
2217  * BROADBAND_EXT_LNA: 0: disable, 1: enable
2218  * ANT_DIVERSITY: 00: Disable, 01: Diversity,
2219  * 10: Main antenna, 11: Aux antenna
2220  * INTERNAL_TX_ALC: 0: disable, 1: enable
2221  * BT_COEXIST: 0: disable, 1: enable
2222  * DAC_TEST: 0: disable, 1: enable
2223  */
2224 #define EEPROM_NIC_CONF1 0x001b
2225 #define EEPROM_NIC_CONF1_HW_RADIO FIELD16(0x0001)
2226 #define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC FIELD16(0x0002)
2227 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G FIELD16(0x0004)
2228 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G FIELD16(0x0008)
2229 #define EEPROM_NIC_CONF1_CARDBUS_ACCEL FIELD16(0x0010)
2230 #define EEPROM_NIC_CONF1_BW40M_SB_2G FIELD16(0x0020)
2231 #define EEPROM_NIC_CONF1_BW40M_SB_5G FIELD16(0x0040)
2232 #define EEPROM_NIC_CONF1_WPS_PBC FIELD16(0x0080)
2233 #define EEPROM_NIC_CONF1_BW40M_2G FIELD16(0x0100)
2234 #define EEPROM_NIC_CONF1_BW40M_5G FIELD16(0x0200)
2235 #define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA FIELD16(0x400)
2236 #define EEPROM_NIC_CONF1_ANT_DIVERSITY FIELD16(0x1800)
2237 #define EEPROM_NIC_CONF1_INTERNAL_TX_ALC FIELD16(0x2000)
2238 #define EEPROM_NIC_CONF1_BT_COEXIST FIELD16(0x4000)
2239 #define EEPROM_NIC_CONF1_DAC_TEST FIELD16(0x8000)
2240 
2241 /*
2242  * EEPROM frequency
2243  */
2244 #define EEPROM_FREQ 0x001d
2245 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
2246 #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
2247 #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
2248 
2249 /*
2250  * EEPROM LED
2251  * POLARITY_RDY_G: Polarity RDY_G setting.
2252  * POLARITY_RDY_A: Polarity RDY_A setting.
2253  * POLARITY_ACT: Polarity ACT setting.
2254  * POLARITY_GPIO_0: Polarity GPIO0 setting.
2255  * POLARITY_GPIO_1: Polarity GPIO1 setting.
2256  * POLARITY_GPIO_2: Polarity GPIO2 setting.
2257  * POLARITY_GPIO_3: Polarity GPIO3 setting.
2258  * POLARITY_GPIO_4: Polarity GPIO4 setting.
2259  * LED_MODE: Led mode.
2260  */
2261 #define EEPROM_LED_AG_CONF 0x001e
2262 #define EEPROM_LED_ACT_CONF 0x001f
2263 #define EEPROM_LED_POLARITY 0x0020
2264 #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
2265 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
2266 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
2267 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
2268 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
2269 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
2270 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
2271 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
2272 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
2273 
2274 /*
2275  * EEPROM NIC Configuration 2
2276  * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2277  * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2278  * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved
2279  */
2280 #define EEPROM_NIC_CONF2 0x0021
2281 #define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f)
2282 #define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0)
2283 #define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600)
2284 
2285 /*
2286  * EEPROM LNA
2287  */
2288 #define EEPROM_LNA 0x0022
2289 #define EEPROM_LNA_BG FIELD16(0x00ff)
2290 #define EEPROM_LNA_A0 FIELD16(0xff00)
2291 
2292 /*
2293  * EEPROM RSSI BG offset
2294  */
2295 #define EEPROM_RSSI_BG 0x0023
2296 #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
2297 #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
2298 
2299 /*
2300  * EEPROM RSSI BG2 offset
2301  */
2302 #define EEPROM_RSSI_BG2 0x0024
2303 #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
2304 #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
2305 
2306 /*
2307  * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
2308  */
2309 #define EEPROM_TXMIXER_GAIN_BG 0x0024
2310 #define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007)
2311 
2312 /*
2313  * EEPROM RSSI A offset
2314  */
2315 #define EEPROM_RSSI_A 0x0025
2316 #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
2317 #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
2318 
2319 /*
2320  * EEPROM RSSI A2 offset
2321  */
2322 #define EEPROM_RSSI_A2 0x0026
2323 #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
2324 #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
2325 
2326 /*
2327  * EEPROM TXMIXER GAIN A offset (note overlaps with EEPROM RSSI A2).
2328  */
2329 #define EEPROM_TXMIXER_GAIN_A 0x0026
2330 #define EEPROM_TXMIXER_GAIN_A_VAL FIELD16(0x0007)
2331 
2332 /*
2333  * EEPROM EIRP Maximum TX power values(unit: dbm)
2334  */
2335 #define EEPROM_EIRP_MAX_TX_POWER 0x0027
2336 #define EEPROM_EIRP_MAX_TX_POWER_2GHZ FIELD16(0x00ff)
2337 #define EEPROM_EIRP_MAX_TX_POWER_5GHZ FIELD16(0xff00)
2338 
2339 /*
2340  * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
2341  * This is delta in 40MHZ.
2342  * VALUE: Tx Power dalta value, MAX=4(unit: dbm)
2343  * TYPE: 1: Plus the delta value, 0: minus the delta value
2344  * ENABLE: enable tx power compensation for 40BW
2345  */
2346 #define EEPROM_TXPOWER_DELTA 0x0028
2347 #define EEPROM_TXPOWER_DELTA_VALUE_2G FIELD16(0x003f)
2348 #define EEPROM_TXPOWER_DELTA_TYPE_2G FIELD16(0x0040)
2349 #define EEPROM_TXPOWER_DELTA_ENABLE_2G FIELD16(0x0080)
2350 #define EEPROM_TXPOWER_DELTA_VALUE_5G FIELD16(0x3f00)
2351 #define EEPROM_TXPOWER_DELTA_TYPE_5G FIELD16(0x4000)
2352 #define EEPROM_TXPOWER_DELTA_ENABLE_5G FIELD16(0x8000)
2353 
2354 /*
2355  * EEPROM TXPOWER 802.11BG
2356  */
2357 #define EEPROM_TXPOWER_BG1 0x0029
2358 #define EEPROM_TXPOWER_BG2 0x0030
2359 #define EEPROM_TXPOWER_BG_SIZE 7
2360 #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
2361 #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
2362 
2363 /*
2364  * EEPROM temperature compensation boundaries 802.11BG
2365  * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2366  * reduced by (agc_step * -4)
2367  * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2368  * reduced by (agc_step * -3)
2369  */
2370 #define EEPROM_TSSI_BOUND_BG1 0x0037
2371 #define EEPROM_TSSI_BOUND_BG1_MINUS4 FIELD16(0x00ff)
2372 #define EEPROM_TSSI_BOUND_BG1_MINUS3 FIELD16(0xff00)
2373 
2374 /*
2375  * EEPROM temperature compensation boundaries 802.11BG
2376  * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2377  * reduced by (agc_step * -2)
2378  * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2379  * reduced by (agc_step * -1)
2380  */
2381 #define EEPROM_TSSI_BOUND_BG2 0x0038
2382 #define EEPROM_TSSI_BOUND_BG2_MINUS2 FIELD16(0x00ff)
2383 #define EEPROM_TSSI_BOUND_BG2_MINUS1 FIELD16(0xff00)
2384 
2385 /*
2386  * EEPROM temperature compensation boundaries 802.11BG
2387  * REF: Reference TSSI value, no tx power changes needed
2388  * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2389  * increased by (agc_step * 1)
2390  */
2391 #define EEPROM_TSSI_BOUND_BG3 0x0039
2392 #define EEPROM_TSSI_BOUND_BG3_REF FIELD16(0x00ff)
2393 #define EEPROM_TSSI_BOUND_BG3_PLUS1 FIELD16(0xff00)
2394 
2395 /*
2396  * EEPROM temperature compensation boundaries 802.11BG
2397  * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2398  * increased by (agc_step * 2)
2399  * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2400  * increased by (agc_step * 3)
2401  */
2402 #define EEPROM_TSSI_BOUND_BG4 0x003a
2403 #define EEPROM_TSSI_BOUND_BG4_PLUS2 FIELD16(0x00ff)
2404 #define EEPROM_TSSI_BOUND_BG4_PLUS3 FIELD16(0xff00)
2405 
2406 /*
2407  * EEPROM temperature compensation boundaries 802.11BG
2408  * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2409  * increased by (agc_step * 4)
2410  * AGC_STEP: Temperature compensation step.
2411  */
2412 #define EEPROM_TSSI_BOUND_BG5 0x003b
2413 #define EEPROM_TSSI_BOUND_BG5_PLUS4 FIELD16(0x00ff)
2414 #define EEPROM_TSSI_BOUND_BG5_AGC_STEP FIELD16(0xff00)
2415 
2416 /*
2417  * EEPROM TXPOWER 802.11A
2418  */
2419 #define EEPROM_TXPOWER_A1 0x003c
2420 #define EEPROM_TXPOWER_A2 0x0053
2421 #define EEPROM_TXPOWER_A_SIZE 6
2422 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
2423 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
2424 
2425 /*
2426  * EEPROM temperature compensation boundaries 802.11A
2427  * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2428  * reduced by (agc_step * -4)
2429  * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2430  * reduced by (agc_step * -3)
2431  */
2432 #define EEPROM_TSSI_BOUND_A1 0x006a
2433 #define EEPROM_TSSI_BOUND_A1_MINUS4 FIELD16(0x00ff)
2434 #define EEPROM_TSSI_BOUND_A1_MINUS3 FIELD16(0xff00)
2435 
2436 /*
2437  * EEPROM temperature compensation boundaries 802.11A
2438  * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2439  * reduced by (agc_step * -2)
2440  * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2441  * reduced by (agc_step * -1)
2442  */
2443 #define EEPROM_TSSI_BOUND_A2 0x006b
2444 #define EEPROM_TSSI_BOUND_A2_MINUS2 FIELD16(0x00ff)
2445 #define EEPROM_TSSI_BOUND_A2_MINUS1 FIELD16(0xff00)
2446 
2447 /*
2448  * EEPROM temperature compensation boundaries 802.11A
2449  * REF: Reference TSSI value, no tx power changes needed
2450  * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2451  * increased by (agc_step * 1)
2452  */
2453 #define EEPROM_TSSI_BOUND_A3 0x006c
2454 #define EEPROM_TSSI_BOUND_A3_REF FIELD16(0x00ff)
2455 #define EEPROM_TSSI_BOUND_A3_PLUS1 FIELD16(0xff00)
2456 
2457 /*
2458  * EEPROM temperature compensation boundaries 802.11A
2459  * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2460  * increased by (agc_step * 2)
2461  * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2462  * increased by (agc_step * 3)
2463  */
2464 #define EEPROM_TSSI_BOUND_A4 0x006d
2465 #define EEPROM_TSSI_BOUND_A4_PLUS2 FIELD16(0x00ff)
2466 #define EEPROM_TSSI_BOUND_A4_PLUS3 FIELD16(0xff00)
2467 
2468 /*
2469  * EEPROM temperature compensation boundaries 802.11A
2470  * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2471  * increased by (agc_step * 4)
2472  * AGC_STEP: Temperature compensation step.
2473  */
2474 #define EEPROM_TSSI_BOUND_A5 0x006e
2475 #define EEPROM_TSSI_BOUND_A5_PLUS4 FIELD16(0x00ff)
2476 #define EEPROM_TSSI_BOUND_A5_AGC_STEP FIELD16(0xff00)
2477 
2478 /*
2479  * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode
2480  */
2481 #define EEPROM_TXPOWER_BYRATE 0x006f
2482 #define EEPROM_TXPOWER_BYRATE_SIZE 9
2483 
2484 #define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f)
2485 #define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0)
2486 #define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00)
2487 #define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000)
2488 
2489 /*
2490  * EEPROM BBP.
2491  */
2492 #define EEPROM_BBP_START 0x0078
2493 #define EEPROM_BBP_SIZE 16
2494 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
2495 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
2496 
2497 /*
2498  * MCU mailbox commands.
2499  * MCU_SLEEP - go to power-save mode.
2500  * arg1: 1: save as much power as possible, 0: save less power.
2501  * status: 1: success, 2: already asleep,
2502  * 3: maybe MAC is busy so can't finish this task.
2503  * MCU_RADIO_OFF
2504  * arg0: 0: do power-saving, NOT turn off radio.
2505  */
2506 #define MCU_SLEEP 0x30
2507 #define MCU_WAKEUP 0x31
2508 #define MCU_RADIO_OFF 0x35
2509 #define MCU_CURRENT 0x36
2510 #define MCU_LED 0x50
2511 #define MCU_LED_STRENGTH 0x51
2512 #define MCU_LED_AG_CONF 0x52
2513 #define MCU_LED_ACT_CONF 0x53
2514 #define MCU_LED_LED_POLARITY 0x54
2515 #define MCU_RADAR 0x60
2516 #define MCU_BOOT_SIGNAL 0x72
2517 #define MCU_ANT_SELECT 0X73
2518 #define MCU_BBP_SIGNAL 0x80
2519 #define MCU_POWER_SAVE 0x83
2520 #define MCU_BAND_SELECT 0x91
2521 
2522 /*
2523  * MCU mailbox tokens
2524  */
2525 #define TOKEN_SLEEP 1
2526 #define TOKEN_RADIO_OFF 2
2527 #define TOKEN_WAKEUP 3
2528 
2529 
2530 /*
2531  * DMA descriptor defines.
2532  */
2533 #define TXWI_DESC_SIZE (4 * sizeof(__le32))
2534 #define RXWI_DESC_SIZE (4 * sizeof(__le32))
2535 
2536 /*
2537  * TX WI structure
2538  */
2539 
2540 /*
2541  * Word0
2542  * FRAG: 1 To inform TKIP engine this is a fragment.
2543  * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
2544  * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
2545  * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will
2546  * duplicate the frame to both channels).
2547  * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
2548  * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will
2549  * aggregate consecutive frames with the same RA and QoS TID. If
2550  * a frame A with the same RA and QoS TID but AMPDU=0 is queued
2551  * directly after a frame B with AMPDU=1, frame A might still
2552  * get aggregated into the AMPDU started by frame B. So, setting
2553  * AMPDU to 0 does _not_ necessarily mean the frame is sent as
2554  * MPDU, it can still end up in an AMPDU if the previous frame
2555  * was tagged as AMPDU.
2556  */
2557 #define TXWI_W0_FRAG FIELD32(0x00000001)
2558 #define TXWI_W0_MIMO_PS FIELD32(0x00000002)
2559 #define TXWI_W0_CF_ACK FIELD32(0x00000004)
2560 #define TXWI_W0_TS FIELD32(0x00000008)
2561 #define TXWI_W0_AMPDU FIELD32(0x00000010)
2562 #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
2563 #define TXWI_W0_TX_OP FIELD32(0x00000300)
2564 #define TXWI_W0_MCS FIELD32(0x007f0000)
2565 #define TXWI_W0_BW FIELD32(0x00800000)
2566 #define TXWI_W0_SHORT_GI FIELD32(0x01000000)
2567 #define TXWI_W0_STBC FIELD32(0x06000000)
2568 #define TXWI_W0_IFS FIELD32(0x08000000)
2569 #define TXWI_W0_PHYMODE FIELD32(0xc0000000)
2570 
2571 /*
2572  * Word1
2573  * ACK: 0: No Ack needed, 1: Ack needed
2574  * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number
2575  * BW_WIN_SIZE: BA windows size of the recipient
2576  * WIRELESS_CLI_ID: Client ID for WCID table access
2577  * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame
2578  * PACKETID: Will be latched into the TX_STA_FIFO register once the according
2579  * frame was processed. If multiple frames are aggregated together
2580  * (AMPDU==1) the reported tx status will always contain the packet
2581  * id of the first frame. 0: Don't report tx status for this frame.
2582  * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3)
2583  * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3)
2584  * This identification number is calculated by ((idx % 3) + 1).
2585  * The (+1) is required to prevent PACKETID to become 0.
2586  */
2587 #define TXWI_W1_ACK FIELD32(0x00000001)
2588 #define TXWI_W1_NSEQ FIELD32(0x00000002)
2589 #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
2590 #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
2591 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2592 #define TXWI_W1_PACKETID FIELD32(0xf0000000)
2593 #define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000)
2594 #define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000)
2595 
2596 /*
2597  * Word2
2598  */
2599 #define TXWI_W2_IV FIELD32(0xffffffff)
2600 
2601 /*
2602  * Word3
2603  */
2604 #define TXWI_W3_EIV FIELD32(0xffffffff)
2605 
2606 /*
2607  * RX WI structure
2608  */
2609 
2610 /*
2611  * Word0
2612  */
2613 #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
2614 #define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
2615 #define RXWI_W0_BSSID FIELD32(0x00001c00)
2616 #define RXWI_W0_UDF FIELD32(0x0000e000)
2617 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2618 #define RXWI_W0_TID FIELD32(0xf0000000)
2619 
2620 /*
2621  * Word1
2622  */
2623 #define RXWI_W1_FRAG FIELD32(0x0000000f)
2624 #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
2625 #define RXWI_W1_MCS FIELD32(0x007f0000)
2626 #define RXWI_W1_BW FIELD32(0x00800000)
2627 #define RXWI_W1_SHORT_GI FIELD32(0x01000000)
2628 #define RXWI_W1_STBC FIELD32(0x06000000)
2629 #define RXWI_W1_PHYMODE FIELD32(0xc0000000)
2630 
2631 /*
2632  * Word2
2633  */
2634 #define RXWI_W2_RSSI0 FIELD32(0x000000ff)
2635 #define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
2636 #define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
2637 
2638 /*
2639  * Word3
2640  */
2641 #define RXWI_W3_SNR0 FIELD32(0x000000ff)
2642 #define RXWI_W3_SNR1 FIELD32(0x0000ff00)
2643 
2644 /*
2645  * Macros for converting txpower from EEPROM to mac80211 value
2646  * and from mac80211 value to register value.
2647  */
2648 #define MIN_G_TXPOWER 0
2649 #define MIN_A_TXPOWER -7
2650 #define MAX_G_TXPOWER 31
2651 #define MAX_A_TXPOWER 15
2652 #define DEFAULT_TXPOWER 5
2653 
2654 #define TXPOWER_G_FROM_DEV(__txpower) \
2655  ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2656 
2657 #define TXPOWER_G_TO_DEV(__txpower) \
2658  clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
2659 
2660 #define TXPOWER_A_FROM_DEV(__txpower) \
2661  ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2662 
2663 #define TXPOWER_A_TO_DEV(__txpower) \
2664  clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
2665 
2666 /*
2667  * Board's maximun TX power limitation
2668  */
2669 #define EIRP_MAX_TX_POWER_LIMIT 0x50
2670 
2671 /*
2672  * Number of TBTT intervals after which we have to adjust
2673  * the hw beacon timer.
2674  */
2675 #define BCN_TBTT_OFFSET 64
2676 
2677 /*
2678  * RT2800 driver data structure
2679  */
2680 struct rt2800_drv_data {
2681  u8 calibration_bw20;
2682  u8 calibration_bw40;
2683  u8 bbp25;
2684  u8 bbp26;
2685  u8 txmixer_gain_24g;
2686  u8 txmixer_gain_5g;
2687  unsigned int tbtt_tick;
2688 };
2689 
2690 #endif /* RT2800_H */
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