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27 #define S5H1432_I2C_TOP_ADDR (0x02 >> 1)
29 #define TAIWAN_HI_IF_FREQ_44_MHZ 44000000
30 #define EUROPE_HI_IF_FREQ_36_MHZ 36000000
31 #define IF_FREQ_6_MHZ 6000000
32 #define IF_FREQ_3point3_MHZ 3300000
33 #define IF_FREQ_3point5_MHZ 3500000
34 #define IF_FREQ_4_MHZ 4000000
39 #define S5H1432_PARALLEL_OUTPUT 0
40 #define S5H1432_SERIAL_OUTPUT 1
44 #define S5H1432_GPIO_OFF 0
45 #define S5H1432_GPIO_ON 1
49 #define S5H1432_MPEGTIMING_CONTINOUS_INVERTING_CLOCK 0
50 #define S5H1432_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK 1
51 #define S5H1432_MPEGTIMING_NONCONTINOUS_INVERTING_CLOCK 2
52 #define S5H1432_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK 3
56 #define S5H1432_IF_3250 3250
57 #define S5H1432_IF_3500 3500
58 #define S5H1432_IF_4000 4000
59 #define S5H1432_IF_5380 5380
60 #define S5H1432_IF_44000 44000
61 #define S5H1432_VSB_IF_DEFAULT s5h1432_IF_44000
62 #define S5H1432_QAM_IF_DEFAULT s5h1432_IF_44000
67 #define S5H1432_INVERSION_OFF 0
68 #define S5H1432_INVERSION_ON 1
72 #define S5H1432_TUNERLOCKING 0
73 #define S5H1432_DEMODLOCKING 1
77 #if defined(CONFIG_DVB_S5H1432) || \
78 (defined(CONFIG_DVB_S5H1432_MODULE) && defined(MODULE))