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sh7785.h
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1 #ifndef __ASM_SH7785_H__
2 #define __ASM_SH7785_H__
3 
4 /* Boot Mode Pins:
5  *
6  * MODE0: CPG - Initial Pck/Bck Frequency [FRQMR1]
7  * MODE1: CPG - Initial Uck/SHck/DDRck Frequency [FRQMR1]
8  * MODE2: CPG - Reserved (L: Normal operation)
9  * MODE3: CPG - Reserved (L: Normal operation)
10  * MODE4: CPG - Initial PLL setting (72x/36x)
11  * MODE5: LBSC - Area0 Memory Type / Bus Width [CS0BCR.8]
12  * MODE6: LBSC - Area0 Memory Type / Bus Width [CS0BCR.9]
13  * MODE7: LBSC - Area0 Memory Type / Bus Width [CS0BCR.3]
14  * MODE8: LBSC - Endian Mode (L: Big, H: Little) [BCR.31]
15  * MODE9: LBSC - Master/Slave Mode (L: Slave) [BCR.30]
16  * MODE10: CPG - Clock Input (L: Ext Clk, H: Crystal)
17  * MODE11: PCI - Pin Mode (LL: PCI host, LH: PCI slave)
18  * MODE12: PCI - Pin Mode (HL: Local bus, HH: DU)
19  * MODE13: Boot Address Mode (L: 29-bit, H: 32-bit)
20  * MODE14: Reserved (H: Normal operation)
21  *
22  * More information in sh7785 manual Rev.1.00, page 1628.
23  */
24 
25 /* Pin Function Controller:
26  * GPIO_FN_xx - GPIO used to select pin function
27  * GPIO_Pxx - GPIO mapped to real I/O pin on CPU
28  */
29 enum {
30  /* PA */
33 
34  /* PB */
37 
38  /* PC */
41 
42  /* PD */
45 
46  /* PE */
49 
50  /* PF */
53 
54  /* PG */
57 
58  /* PH */
61 
62  /* PJ */
65 
66  /* PK */
69 
70  /* PL */
73 
74  /* PM */
76 
77  /* PN */
80 
81  /* PP */
84 
85  /* PQ */
88 
89  /* PR */
91 
257 };
258 
259 #endif /* __ASM_SH7785_H__ */