Go to the documentation of this file. 1 #ifndef __ASM_SH_CPU_SH5_ADDRSPACE_H
2 #define __ASM_SH_CPU_SH5_ADDRSPACE_H
4 #define PHYS_PERIPHERAL_BLOCK 0x09000000
5 #define PHYS_DMAC_BLOCK 0x0e000000
6 #define PHYS_PCI_BLOCK 0x60000000
7 #define PHYS_EMI_BLOCK 0xff000000