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sh_pfc.h
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1 /*
2  * SuperH Pin Function Controller Support
3  *
4  * Copyright (c) 2008 Magnus Damm
5  *
6  * This file is subject to the terms and conditions of the GNU General Public
7  * License. See the file "COPYING" in the main directory of this archive
8  * for more details.
9  */
10 
11 #ifndef __SH_PFC_H
12 #define __SH_PFC_H
13 
14 #include <linux/stringify.h>
15 #include <asm-generic/gpio.h>
16 
17 typedef unsigned short pinmux_enum_t;
18 typedef unsigned short pinmux_flag_t;
19 
20 enum {
21  PINMUX_TYPE_NONE,
22 
23  PINMUX_TYPE_FUNCTION,
24  PINMUX_TYPE_GPIO,
25  PINMUX_TYPE_OUTPUT,
26  PINMUX_TYPE_INPUT,
27  PINMUX_TYPE_INPUT_PULLUP,
28  PINMUX_TYPE_INPUT_PULLDOWN,
29 
30  PINMUX_FLAG_TYPE, /* must be last */
31 };
32 
33 #define PINMUX_FLAG_DBIT_SHIFT 5
34 #define PINMUX_FLAG_DBIT (0x1f << PINMUX_FLAG_DBIT_SHIFT)
35 #define PINMUX_FLAG_DREG_SHIFT 10
36 #define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT)
37 
38 struct pinmux_gpio {
39  pinmux_enum_t enum_id;
40  pinmux_flag_t flags;
41  const char *name;
42 };
43 
44 #define PINMUX_GPIO(gpio, data_or_mark) \
45  [gpio] = { .name = __stringify(gpio), .enum_id = data_or_mark, .flags = PINMUX_TYPE_NONE }
46 
47 #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
48 
49 struct pinmux_cfg_reg {
50  unsigned long reg, reg_width, field_width;
51  unsigned long *cnt;
52  pinmux_enum_t *enum_ids;
53  unsigned long *var_field_width;
54 };
55 
56 #define PINMUX_CFG_REG(name, r, r_width, f_width) \
57  .reg = r, .reg_width = r_width, .field_width = f_width, \
58  .cnt = (unsigned long [r_width / f_width]) {}, \
59  .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])
60 
61 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
62  .reg = r, .reg_width = r_width, \
63  .cnt = (unsigned long [r_width]) {}, \
64  .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
65  .enum_ids = (pinmux_enum_t [])
66 
67 struct pinmux_data_reg {
68  unsigned long reg, reg_width, reg_shadow;
69  pinmux_enum_t *enum_ids;
70  void __iomem *mapped_reg;
71 };
72 
73 #define PINMUX_DATA_REG(name, r, r_width) \
74  .reg = r, .reg_width = r_width, \
75  .enum_ids = (pinmux_enum_t [r_width]) \
76 
77 struct pinmux_irq {
78  int irq;
79  pinmux_enum_t *enum_ids;
80 };
81 
82 #define PINMUX_IRQ(irq_nr, ids...) \
83  { .irq = irq_nr, .enum_ids = (pinmux_enum_t []) { ids, 0 } } \
84 
85 struct pinmux_range {
86  pinmux_enum_t begin;
87  pinmux_enum_t end;
88  pinmux_enum_t force;
89 };
90 
91 struct pfc_window {
92  phys_addr_t phys;
93  void __iomem *virt;
94  unsigned long size;
95 };
96 
97 struct sh_pfc {
98  char *name;
99  pinmux_enum_t reserved_id;
100  struct pinmux_range data;
101  struct pinmux_range input;
102  struct pinmux_range input_pd;
103  struct pinmux_range input_pu;
104  struct pinmux_range output;
105  struct pinmux_range mark;
106  struct pinmux_range function;
107 
108  unsigned first_gpio, last_gpio;
109 
110  struct pinmux_gpio *gpios;
111  struct pinmux_cfg_reg *cfg_regs;
112  struct pinmux_data_reg *data_regs;
113 
114  pinmux_enum_t *gpio_data;
115  unsigned int gpio_data_size;
116 
117  struct pinmux_irq *gpio_irq;
118  unsigned int gpio_irq_size;
119 
120  spinlock_t lock;
121 
122  struct resource *resource;
123  unsigned int num_resources;
124  struct pfc_window *window;
125 
126  unsigned long unlock_reg;
127 };
128 
129 /* XXX compat for now */
130 #define pinmux_info sh_pfc
131 
132 /* drivers/sh/pfc/gpio.c */
133 int sh_pfc_register_gpiochip(struct sh_pfc *pfc);
134 
135 /* drivers/sh/pfc/pinctrl.c */
136 int sh_pfc_register_pinctrl(struct sh_pfc *pfc);
137 
138 /* drivers/sh/pfc/core.c */
139 int register_sh_pfc(struct sh_pfc *pfc);
140 
141 int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos);
142 void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
143  unsigned long value);
144 int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
145  struct pinmux_data_reg **drp, int *bitp);
146 int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
147  pinmux_enum_t *enum_idp);
148 int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
149  int cfg_mode);
150 
151 /* xxx */
152 static inline int register_pinmux(struct pinmux_info *pip)
153 {
154  struct sh_pfc *pfc = pip;
155  return register_sh_pfc(pfc);
156 }
157 
158 enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
159 
160 /* helper macro for port */
161 #define PORT_1(fn, pfx, sfx) fn(pfx, sfx)
162 
163 #define PORT_10(fn, pfx, sfx) \
164  PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
165  PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
166  PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \
167  PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
168  PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)
169 
170 #define PORT_90(fn, pfx, sfx) \
171  PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \
172  PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \
173  PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx), \
174  PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx), \
175  PORT_10(fn, pfx##9, sfx)
176 
177 #define _PORT_ALL(pfx, sfx) pfx##_##sfx
178 #define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
179 #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
180 #define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused)
181 #define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
182 
183 /* helper macro for pinmux_enum_t */
184 #define PORT_DATA_I(nr) \
185  PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
186 
187 #define PORT_DATA_I_PD(nr) \
188  PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
189  PORT##nr##_IN, PORT##nr##_IN_PD)
190 
191 #define PORT_DATA_I_PU(nr) \
192  PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
193  PORT##nr##_IN, PORT##nr##_IN_PU)
194 
195 #define PORT_DATA_I_PU_PD(nr) \
196  PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
197  PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
198 
199 #define PORT_DATA_O(nr) \
200  PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
201 
202 #define PORT_DATA_IO(nr) \
203  PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
204  PORT##nr##_IN)
205 
206 #define PORT_DATA_IO_PD(nr) \
207  PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
208  PORT##nr##_IN, PORT##nr##_IN_PD)
209 
210 #define PORT_DATA_IO_PU(nr) \
211  PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
212  PORT##nr##_IN, PORT##nr##_IN_PU)
213 
214 #define PORT_DATA_IO_PU_PD(nr) \
215  PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
216  PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
217 
218 /* helper macro for top 4 bits in PORTnCR */
219 #define _PCRH(in, in_pd, in_pu, out) \
220  0, (out), (in), 0, \
221  0, 0, 0, 0, \
222  0, 0, (in_pd), 0, \
223  0, 0, (in_pu), 0
224 
225 #define PORTCR(nr, reg) \
226  { \
227  PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
228  _PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \
229  PORT##nr##_IN_PU, PORT##nr##_OUT), \
230  PORT##nr##_FN0, PORT##nr##_FN1, \
231  PORT##nr##_FN2, PORT##nr##_FN3, \
232  PORT##nr##_FN4, PORT##nr##_FN5, \
233  PORT##nr##_FN6, PORT##nr##_FN7 } \
234  }
235 
236 #endif /* __SH_PFC_H */
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