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smsc75xx.h
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1  /***************************************************************************
2  *
3  * Copyright (C) 2007-2010 SMSC
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License
7  * as published by the Free Software Foundation; either version 2
8  * of the License, or (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18  *
19  *****************************************************************************/
20 
21 #ifndef _SMSC75XX_H
22 #define _SMSC75XX_H
23 
24 /* Tx command words */
25 #define TX_CMD_A_LSO (0x08000000)
26 #define TX_CMD_A_IPE (0x04000000)
27 #define TX_CMD_A_TPE (0x02000000)
28 #define TX_CMD_A_IVTG (0x01000000)
29 #define TX_CMD_A_RVTG (0x00800000)
30 #define TX_CMD_A_FCS (0x00400000)
31 #define TX_CMD_A_LEN (0x000FFFFF)
32 
33 #define TX_CMD_B_MSS (0x3FFF0000)
34 #define TX_CMD_B_MSS_SHIFT (16)
35 #define TX_MSS_MIN ((u16)8)
36 #define TX_CMD_B_VTAG (0x0000FFFF)
37 
38 /* Rx command words */
39 #define RX_CMD_A_ICE (0x80000000)
40 #define RX_CMD_A_TCE (0x40000000)
41 #define RX_CMD_A_IPV (0x20000000)
42 #define RX_CMD_A_PID (0x18000000)
43 #define RX_CMD_A_PID_NIP (0x00000000)
44 #define RX_CMD_A_PID_TCP (0x08000000)
45 #define RX_CMD_A_PID_UDP (0x10000000)
46 #define RX_CMD_A_PID_PP (0x18000000)
47 #define RX_CMD_A_PFF (0x04000000)
48 #define RX_CMD_A_BAM (0x02000000)
49 #define RX_CMD_A_MAM (0x01000000)
50 #define RX_CMD_A_FVTG (0x00800000)
51 #define RX_CMD_A_RED (0x00400000)
52 #define RX_CMD_A_RWT (0x00200000)
53 #define RX_CMD_A_RUNT (0x00100000)
54 #define RX_CMD_A_LONG (0x00080000)
55 #define RX_CMD_A_RXE (0x00040000)
56 #define RX_CMD_A_DRB (0x00020000)
57 #define RX_CMD_A_FCS (0x00010000)
58 #define RX_CMD_A_UAM (0x00008000)
59 #define RX_CMD_A_LCSM (0x00004000)
60 #define RX_CMD_A_LEN (0x00003FFF)
61 
62 #define RX_CMD_B_CSUM (0xFFFF0000)
63 #define RX_CMD_B_CSUM_SHIFT (16)
64 #define RX_CMD_B_VTAG (0x0000FFFF)
65 
66 /* SCSRs */
67 #define ID_REV (0x0000)
68 
69 #define FPGA_REV (0x0004)
70 
71 #define BOND_CTL (0x0008)
72 
73 #define INT_STS (0x000C)
74 #define INT_STS_RDFO_INT (0x00400000)
75 #define INT_STS_TXE_INT (0x00200000)
76 #define INT_STS_MACRTO_INT (0x00100000)
77 #define INT_STS_TX_DIS_INT (0x00080000)
78 #define INT_STS_RX_DIS_INT (0x00040000)
79 #define INT_STS_PHY_INT_ (0x00020000)
80 #define INT_STS_MAC_ERR_INT (0x00008000)
81 #define INT_STS_TDFU (0x00004000)
82 #define INT_STS_TDFO (0x00002000)
83 #define INT_STS_GPIOS (0x00000FFF)
84 #define INT_STS_CLEAR_ALL (0xFFFFFFFF)
85 
86 #define HW_CFG (0x0010)
87 #define HW_CFG_SMDET_STS (0x00008000)
88 #define HW_CFG_SMDET_EN (0x00004000)
89 #define HW_CFG_EEM (0x00002000)
90 #define HW_CFG_RST_PROTECT (0x00001000)
91 #define HW_CFG_PORT_SWAP (0x00000800)
92 #define HW_CFG_PHY_BOOST (0x00000600)
93 #define HW_CFG_PHY_BOOST_NORMAL (0x00000000)
94 #define HW_CFG_PHY_BOOST_4 (0x00002000)
95 #define HW_CFG_PHY_BOOST_8 (0x00004000)
96 #define HW_CFG_PHY_BOOST_12 (0x00006000)
97 #define HW_CFG_LEDB (0x00000100)
98 #define HW_CFG_BIR (0x00000080)
99 #define HW_CFG_SBP (0x00000040)
100 #define HW_CFG_IME (0x00000020)
101 #define HW_CFG_MEF (0x00000010)
102 #define HW_CFG_ETC (0x00000008)
103 #define HW_CFG_BCE (0x00000004)
104 #define HW_CFG_LRST (0x00000002)
105 #define HW_CFG_SRST (0x00000001)
106 
107 #define PMT_CTL (0x0014)
108 #define PMT_CTL_PHY_PWRUP (0x00000400)
109 #define PMT_CTL_RES_CLR_WKP_EN (0x00000100)
110 #define PMT_CTL_DEV_RDY (0x00000080)
111 #define PMT_CTL_SUS_MODE (0x00000060)
112 #define PMT_CTL_SUS_MODE_0 (0x00000000)
113 #define PMT_CTL_SUS_MODE_1 (0x00000020)
114 #define PMT_CTL_SUS_MODE_2 (0x00000040)
115 #define PMT_CTL_SUS_MODE_3 (0x00000060)
116 #define PMT_CTL_PHY_RST (0x00000010)
117 #define PMT_CTL_WOL_EN (0x00000008)
118 #define PMT_CTL_ED_EN (0x00000004)
119 #define PMT_CTL_WUPS (0x00000003)
120 #define PMT_CTL_WUPS_NO (0x00000000)
121 #define PMT_CTL_WUPS_ED (0x00000001)
122 #define PMT_CTL_WUPS_WOL (0x00000002)
123 #define PMT_CTL_WUPS_MULTI (0x00000003)
124 
125 #define LED_GPIO_CFG (0x0018)
126 #define LED_GPIO_CFG_LED2_FUN_SEL (0x80000000)
127 #define LED_GPIO_CFG_LED10_FUN_SEL (0x40000000)
128 #define LED_GPIO_CFG_LEDGPIO_EN (0x0000F000)
129 #define LED_GPIO_CFG_LEDGPIO_EN_0 (0x00001000)
130 #define LED_GPIO_CFG_LEDGPIO_EN_1 (0x00002000)
131 #define LED_GPIO_CFG_LEDGPIO_EN_2 (0x00004000)
132 #define LED_GPIO_CFG_LEDGPIO_EN_3 (0x00008000)
133 #define LED_GPIO_CFG_GPBUF (0x00000F00)
134 #define LED_GPIO_CFG_GPBUF_0 (0x00000100)
135 #define LED_GPIO_CFG_GPBUF_1 (0x00000200)
136 #define LED_GPIO_CFG_GPBUF_2 (0x00000400)
137 #define LED_GPIO_CFG_GPBUF_3 (0x00000800)
138 #define LED_GPIO_CFG_GPDIR (0x000000F0)
139 #define LED_GPIO_CFG_GPDIR_0 (0x00000010)
140 #define LED_GPIO_CFG_GPDIR_1 (0x00000020)
141 #define LED_GPIO_CFG_GPDIR_2 (0x00000040)
142 #define LED_GPIO_CFG_GPDIR_3 (0x00000080)
143 #define LED_GPIO_CFG_GPDATA (0x0000000F)
144 #define LED_GPIO_CFG_GPDATA_0 (0x00000001)
145 #define LED_GPIO_CFG_GPDATA_1 (0x00000002)
146 #define LED_GPIO_CFG_GPDATA_2 (0x00000004)
147 #define LED_GPIO_CFG_GPDATA_3 (0x00000008)
148 
149 #define GPIO_CFG (0x001C)
150 #define GPIO_CFG_SHIFT (24)
151 #define GPIO_CFG_GPEN (0xFF000000)
152 #define GPIO_CFG_GPBUF (0x00FF0000)
153 #define GPIO_CFG_GPDIR (0x0000FF00)
154 #define GPIO_CFG_GPDATA (0x000000FF)
155 
156 #define GPIO_WAKE (0x0020)
157 #define GPIO_WAKE_PHY_LINKUP_EN (0x80000000)
158 #define GPIO_WAKE_POL (0x0FFF0000)
159 #define GPIO_WAKE_POL_SHIFT (16)
160 #define GPIO_WAKE_WK (0x00000FFF)
161 
162 #define DP_SEL (0x0024)
163 #define DP_SEL_DPRDY (0x80000000)
164 #define DP_SEL_RSEL (0x0000000F)
165 #define DP_SEL_URX (0x00000000)
166 #define DP_SEL_VHF (0x00000001)
167 #define DP_SEL_VHF_HASH_LEN (16)
168 #define DP_SEL_VHF_VLAN_LEN (128)
169 #define DP_SEL_LSO_HEAD (0x00000002)
170 #define DP_SEL_FCT_RX (0x00000003)
171 #define DP_SEL_FCT_TX (0x00000004)
172 #define DP_SEL_DESCRIPTOR (0x00000005)
173 #define DP_SEL_WOL (0x00000006)
174 
175 #define DP_CMD (0x0028)
176 #define DP_CMD_WRITE (0x01)
177 #define DP_CMD_READ (0x00)
178 
179 #define DP_ADDR (0x002C)
180 
181 #define DP_DATA (0x0030)
182 
183 #define BURST_CAP (0x0034)
184 #define BURST_CAP_MASK (0x0000000F)
185 
186 #define INT_EP_CTL (0x0038)
187 #define INT_EP_CTL_INTEP_ON (0x80000000)
188 #define INT_EP_CTL_RDFO_EN (0x00400000)
189 #define INT_EP_CTL_TXE_EN (0x00200000)
190 #define INT_EP_CTL_MACROTO_EN (0x00100000)
191 #define INT_EP_CTL_TX_DIS_EN (0x00080000)
192 #define INT_EP_CTL_RX_DIS_EN (0x00040000)
193 #define INT_EP_CTL_PHY_EN_ (0x00020000)
194 #define INT_EP_CTL_MAC_ERR_EN (0x00008000)
195 #define INT_EP_CTL_TDFU_EN (0x00004000)
196 #define INT_EP_CTL_TDFO_EN (0x00002000)
197 #define INT_EP_CTL_RX_FIFO_EN (0x00001000)
198 #define INT_EP_CTL_GPIOX_EN (0x00000FFF)
199 
200 #define BULK_IN_DLY (0x003C)
201 #define BULK_IN_DLY_MASK (0xFFFF)
202 
203 #define E2P_CMD (0x0040)
204 #define E2P_CMD_BUSY (0x80000000)
205 #define E2P_CMD_MASK (0x70000000)
206 #define E2P_CMD_READ (0x00000000)
207 #define E2P_CMD_EWDS (0x10000000)
208 #define E2P_CMD_EWEN (0x20000000)
209 #define E2P_CMD_WRITE (0x30000000)
210 #define E2P_CMD_WRAL (0x40000000)
211 #define E2P_CMD_ERASE (0x50000000)
212 #define E2P_CMD_ERAL (0x60000000)
213 #define E2P_CMD_RELOAD (0x70000000)
214 #define E2P_CMD_TIMEOUT (0x00000400)
215 #define E2P_CMD_LOADED (0x00000200)
216 #define E2P_CMD_ADDR (0x000001FF)
217 
218 #define MAX_EEPROM_SIZE (512)
219 
220 #define E2P_DATA (0x0044)
221 #define E2P_DATA_MASK_ (0x000000FF)
222 
223 #define RFE_CTL (0x0060)
224 #define RFE_CTL_TCPUDP_CKM (0x00001000)
225 #define RFE_CTL_IP_CKM (0x00000800)
226 #define RFE_CTL_AB (0x00000400)
227 #define RFE_CTL_AM (0x00000200)
228 #define RFE_CTL_AU (0x00000100)
229 #define RFE_CTL_VS (0x00000080)
230 #define RFE_CTL_UF (0x00000040)
231 #define RFE_CTL_VF (0x00000020)
232 #define RFE_CTL_SPF (0x00000010)
233 #define RFE_CTL_MHF (0x00000008)
234 #define RFE_CTL_DHF (0x00000004)
235 #define RFE_CTL_DPF (0x00000002)
236 #define RFE_CTL_RST_RF (0x00000001)
237 
238 #define VLAN_TYPE (0x0064)
239 #define VLAN_TYPE_MASK (0x0000FFFF)
240 
241 #define FCT_RX_CTL (0x0090)
242 #define FCT_RX_CTL_EN (0x80000000)
243 #define FCT_RX_CTL_RST (0x40000000)
244 #define FCT_RX_CTL_SBF (0x02000000)
245 #define FCT_RX_CTL_OVERFLOW (0x01000000)
246 #define FCT_RX_CTL_FRM_DROP (0x00800000)
247 #define FCT_RX_CTL_RX_NOT_EMPTY (0x00400000)
248 #define FCT_RX_CTL_RX_EMPTY (0x00200000)
249 #define FCT_RX_CTL_RX_DISABLED (0x00100000)
250 #define FCT_RX_CTL_RXUSED (0x0000FFFF)
251 
252 #define FCT_TX_CTL (0x0094)
253 #define FCT_TX_CTL_EN (0x80000000)
254 #define FCT_TX_CTL_RST (0x40000000)
255 #define FCT_TX_CTL_TX_NOT_EMPTY (0x00400000)
256 #define FCT_TX_CTL_TX_EMPTY (0x00200000)
257 #define FCT_TX_CTL_TX_DISABLED (0x00100000)
258 #define FCT_TX_CTL_TXUSED (0x0000FFFF)
259 
260 #define FCT_RX_FIFO_END (0x0098)
261 #define FCT_RX_FIFO_END_MASK (0x0000007F)
262 
263 #define FCT_TX_FIFO_END (0x009C)
264 #define FCT_TX_FIFO_END_MASK (0x0000003F)
265 
266 #define FCT_FLOW (0x00A0)
267 #define FCT_FLOW_THRESHOLD_OFF (0x00007F00)
268 #define FCT_FLOW_THRESHOLD_OFF_SHIFT (8)
269 #define FCT_FLOW_THRESHOLD_ON (0x0000007F)
270 
271 /* MAC CSRs */
272 #define MAC_CR (0x100)
273 #define MAC_CR_ADP (0x00002000)
274 #define MAC_CR_ADD (0x00001000)
275 #define MAC_CR_ASD (0x00000800)
276 #define MAC_CR_INT_LOOP (0x00000400)
277 #define MAC_CR_BOLMT (0x000000C0)
278 #define MAC_CR_FDPX (0x00000008)
279 #define MAC_CR_CFG (0x00000006)
280 #define MAC_CR_CFG_10 (0x00000000)
281 #define MAC_CR_CFG_100 (0x00000002)
282 #define MAC_CR_CFG_1000 (0x00000004)
283 #define MAC_CR_RST (0x00000001)
284 
285 #define MAC_RX (0x104)
286 #define MAC_RX_MAX_SIZE (0x3FFF0000)
287 #define MAC_RX_MAX_SIZE_SHIFT (16)
288 #define MAC_RX_FCS_STRIP (0x00000010)
289 #define MAC_RX_FSE (0x00000004)
290 #define MAC_RX_RXD (0x00000002)
291 #define MAC_RX_RXEN (0x00000001)
292 
293 #define MAC_TX (0x108)
294 #define MAC_TX_BFCS (0x00000004)
295 #define MAC_TX_TXD (0x00000002)
296 #define MAC_TX_TXEN (0x00000001)
297 
298 #define FLOW (0x10C)
299 #define FLOW_FORCE_FC (0x80000000)
300 #define FLOW_TX_FCEN (0x40000000)
301 #define FLOW_RX_FCEN (0x20000000)
302 #define FLOW_FPF (0x10000000)
303 #define FLOW_PAUSE_TIME (0x0000FFFF)
304 
305 #define RAND_SEED (0x110)
306 #define RAND_SEED_MASK (0x0000FFFF)
307 
308 #define ERR_STS (0x114)
309 #define ERR_STS_FCS_ERR (0x00000100)
310 #define ERR_STS_LFRM_ERR (0x00000080)
311 #define ERR_STS_RUNT_ERR (0x00000040)
312 #define ERR_STS_COLLISION_ERR (0x00000010)
313 #define ERR_STS_ALIGN_ERR (0x00000008)
314 #define ERR_STS_URUN_ERR (0x00000004)
315 
316 #define RX_ADDRH (0x118)
317 #define RX_ADDRH_MASK (0x0000FFFF)
318 
319 #define RX_ADDRL (0x11C)
320 
321 #define MII_ACCESS (0x120)
322 #define MII_ACCESS_PHY_ADDR (0x0000F800)
323 #define MII_ACCESS_PHY_ADDR_SHIFT (11)
324 #define MII_ACCESS_REG_ADDR (0x000007C0)
325 #define MII_ACCESS_REG_ADDR_SHIFT (6)
326 #define MII_ACCESS_READ (0x00000000)
327 #define MII_ACCESS_WRITE (0x00000002)
328 #define MII_ACCESS_BUSY (0x00000001)
329 
330 #define MII_DATA (0x124)
331 #define MII_DATA_MASK (0x0000FFFF)
332 
333 #define WUCSR (0x140)
334 #define WUCSR_PFDA_FR (0x00000080)
335 #define WUCSR_WUFR (0x00000040)
336 #define WUCSR_MPR (0x00000020)
337 #define WUCSR_BCAST_FR (0x00000010)
338 #define WUCSR_PFDA_EN (0x00000008)
339 #define WUCSR_WUEN (0x00000004)
340 #define WUCSR_MPEN (0x00000002)
341 #define WUCSR_BCST_EN (0x00000001)
342 
343 #define WUF_CFGX (0x144)
344 #define WUF_CFGX_EN (0x80000000)
345 #define WUF_CFGX_ATYPE (0x03000000)
346 #define WUF_CFGX_ATYPE_UNICAST (0x00000000)
347 #define WUF_CFGX_ATYPE_MULTICAST (0x02000000)
348 #define WUF_CFGX_ATYPE_ALL (0x03000000)
349 #define WUF_CFGX_PATTERN_OFFSET (0x007F0000)
350 #define WUF_CFGX_PATTERN_OFFSET_SHIFT (16)
351 #define WUF_CFGX_CRC16 (0x0000FFFF)
352 #define WUF_NUM (8)
353 
354 #define WUF_MASKX (0x170)
355 #define WUF_MASKX_AVALID (0x80000000)
356 #define WUF_MASKX_ATYPE (0x40000000)
357 
358 #define ADDR_FILTX (0x300)
359 #define ADDR_FILTX_FB_VALID (0x80000000)
360 #define ADDR_FILTX_FB_TYPE (0x40000000)
361 #define ADDR_FILTX_FB_ADDRHI (0x0000FFFF)
362 #define ADDR_FILTX_SB_ADDRLO (0xFFFFFFFF)
363 
364 #define WUCSR2 (0x500)
365 #define WUCSR2_NS_RCD (0x00000040)
366 #define WUCSR2_ARP_RCD (0x00000020)
367 #define WUCSR2_TCPSYN_RCD (0x00000010)
368 #define WUCSR2_NS_OFFLOAD (0x00000004)
369 #define WUCSR2_ARP_OFFLOAD (0x00000002)
370 #define WUCSR2_TCPSYN_OFFLOAD (0x00000001)
371 
372 #define WOL_FIFO_STS (0x504)
373 
374 #define IPV6_ADDRX (0x510)
375 
376 #define IPV4_ADDRX (0x590)
377 
378 
379 /* Vendor-specific PHY Definitions */
380 
381 /* Mode Control/Status Register */
382 #define PHY_MODE_CTRL_STS (17)
383 #define MODE_CTRL_STS_EDPWRDOWN ((u16)0x2000)
384 #define MODE_CTRL_STS_ENERGYON ((u16)0x0002)
385 
386 #define PHY_INT_SRC (29)
387 #define PHY_INT_SRC_ENERGY_ON ((u16)0x0080)
388 #define PHY_INT_SRC_ANEG_COMP ((u16)0x0040)
389 #define PHY_INT_SRC_REMOTE_FAULT ((u16)0x0020)
390 #define PHY_INT_SRC_LINK_DOWN ((u16)0x0010)
391 #define PHY_INT_SRC_CLEAR_ALL ((u16)0xffff)
392 
393 #define PHY_INT_MASK (30)
394 #define PHY_INT_MASK_ENERGY_ON ((u16)0x0080)
395 #define PHY_INT_MASK_ANEG_COMP ((u16)0x0040)
396 #define PHY_INT_MASK_REMOTE_FAULT ((u16)0x0020)
397 #define PHY_INT_MASK_LINK_DOWN ((u16)0x0010)
398 #define PHY_INT_MASK_DEFAULT (PHY_INT_MASK_ANEG_COMP | \
399  PHY_INT_MASK_LINK_DOWN)
400 
401 #define PHY_SPECIAL (31)
402 #define PHY_SPECIAL_SPD ((u16)0x001C)
403 #define PHY_SPECIAL_SPD_10HALF ((u16)0x0004)
404 #define PHY_SPECIAL_SPD_10FULL ((u16)0x0014)
405 #define PHY_SPECIAL_SPD_100HALF ((u16)0x0008)
406 #define PHY_SPECIAL_SPD_100FULL ((u16)0x0018)
407 
408 /* USB Vendor Requests */
409 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
410 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
411 #define USB_VENDOR_REQUEST_GET_STATS 0xA2
412 
413 /* Interrupt Endpoint status word bitfields */
414 #define INT_ENP_RDFO_INT ((u32)BIT(22))
415 #define INT_ENP_TXE_INT ((u32)BIT(21))
416 #define INT_ENP_TX_DIS_INT ((u32)BIT(19))
417 #define INT_ENP_RX_DIS_INT ((u32)BIT(18))
418 #define INT_ENP_PHY_INT ((u32)BIT(17))
419 #define INT_ENP_MAC_ERR_INT ((u32)BIT(15))
420 #define INT_ENP_RX_FIFO_DATA_INT ((u32)BIT(12))
421 
422 #endif /* _SMSC75XX_H */